Lines Matching refs:write_reg
104 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03);
107 write_reg(par, SEPS525_REDUCE_CURRENT, 0x00);
110 write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00);
112 write_reg(par, SEPS525_OSC_CTL, 0x01);
114 write_reg(par, SEPS525_CLOCK_DIV, 0x90);
116 write_reg(par, SEPS525_IREF, 0x01);
119 write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04);
120 write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05);
121 write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05);
124 write_reg(par, SEPS525_PRECHARGE_CURRENT_R, 0x9D);
125 write_reg(par, SEPS525_PRECHARGE_CURRENT_G, 0x8C);
126 write_reg(par, SEPS525_PRECHARGE_CURRENT_B, 0x57);
129 write_reg(par, SEPS525_DRIVING_CURRENT_R, 0x56);
130 write_reg(par, SEPS525_DRIVING_CURRENT_G, 0x4D);
131 write_reg(par, SEPS525_DRIVING_CURRENT_B, 0x46);
133 write_reg(par, SEPS525_DISPLAYMODE_SET, 0xA0);
134 write_reg(par, SEPS525_RGBIF, 0x01); /* Set MCU Interface Mode */
136 write_reg(par, SEPS525_MEMORY_WRITEMODE, 0x66);
137 write_reg(par, SEPS525_DUTY, 0x7F); /* 1/128 Duty (0x0F~0x7F) */
139 write_reg(par, SEPS525_DSL, 0x00);
140 write_reg(par, SEPS525_DISP_ONOFF, 0x01); /* Display On (0x00/0x01) */
142 write_reg(par, SEPS525_SOFT_RST, 0x00);
144 write_reg(par, SEPS525_RGB_POL, 0x00);
146 write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT);
155 write_reg(par, SEPS525_MX1_ADDR, xs);
156 write_reg(par, SEPS525_MX2_ADDR, xe);
157 write_reg(par, SEPS525_MY1_ADDR, ys);
158 write_reg(par, SEPS525_MY2_ADDR, ye);
161 write_reg(par, SEPS525_MEMORY_ACCESS_POINTER_X, xs);
162 write_reg(par, SEPS525_MEMORY_ACCESS_POINTER_Y, ys);
164 write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT);
185 write_reg(par, SEPS525_DISPLAYMODE_SET, val |
188 write_reg(par, SEPS525_DDRAM_DATA_ACCESS_PORT);