Lines Matching refs:write_reg
24 write_reg(par, 0xB0, 0x80);
25 write_reg(par, 0xC0, 0x0A, 0x0A);
26 write_reg(par, 0xC1, 0x45, 0x07);
27 write_reg(par, 0xC2, 0x33);
28 write_reg(par, 0xC5, 0x00, 0x42, 0x80);
29 write_reg(par, 0xB1, 0xD0, 0x11);
30 write_reg(par, 0xB4, 0x02);
31 write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
32 write_reg(par, 0xB7, 0x07);
33 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x58);
34 write_reg(par, 0xF0, 0x36, 0xA5, 0xD3);
35 write_reg(par, 0xE5, 0x80);
36 write_reg(par, 0xE5, 0x01);
37 write_reg(par, 0xB3, 0x00);
38 write_reg(par, 0xE5, 0x00);
39 write_reg(par, 0xF0, 0x36, 0xA5, 0x53);
40 write_reg(par, 0xE0, 0x00, 0x35, 0x33, 0x00, 0x00, 0x00,
42 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);
43 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
45 write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
52 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
55 write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
58 write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
65 write_reg(par, 0xB6, 0x00, 0x02, 0x3B);
66 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x28);
69 write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
70 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x58);
73 write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
74 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x38);
77 write_reg(par, 0xB6, 0x00, 0x22, 0x3B);
78 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x08);