Lines Matching refs:write_reg
38 write_reg(par, 0xfd, 0x12); /* Command Lock */
39 write_reg(par, 0xfd, 0xb1); /* Command Lock */
40 write_reg(par, 0xae); /* Display Off */
41 write_reg(par, 0xb3, 0xf1); /* Front Clock Div */
42 write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */
43 write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */
44 write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */
45 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */
46 write_reg(par, 0xa2, 0x00); /* Set Display Offset */
47 write_reg(par, 0xb5, 0x00); /* Set GPIO */
48 write_reg(par, 0xab, 0x01); /* Set Function Selection */
49 write_reg(par, 0xb1, 0x32); /* Set Phase Length */
50 write_reg(par, 0xb4, 0xa0, 0xb5, 0x55); /* Set Segment Low Voltage */
51 write_reg(par, 0xbb, 0x17); /* Set Precharge Voltage */
52 write_reg(par, 0xbe, 0x05); /* Set VComH Voltage */
53 write_reg(par, 0xc1, 0xc8, 0x80, 0xc8); /* Set Contrast */
54 write_reg(par, 0xc7, 0x0f); /* Set Master Contrast */
55 write_reg(par, 0xb6, 0x01); /* Set Second Precharge Period */
56 write_reg(par, 0xa6); /* Set Display Mode Reset */
57 write_reg(par, 0xaf); /* Set Sleep Mode Display On */
64 write_reg(par, 0x15, xs, xe);
65 write_reg(par, 0x75, ys, ye);
66 write_reg(par, 0x5c);
85 write_reg(par, 0xA0, remap | 0x00 | BIT(4));
88 write_reg(par, 0xA0, remap | 0x03 | BIT(4));
91 write_reg(par, 0xA0, remap | 0x02);
94 write_reg(par, 0xA0, remap | 0x01);
144 write_reg(par, 0xB8,
170 write_reg(par, 0xAE);
172 write_reg(par, 0xAF);
203 write_reg(par, 0xB5, on ? 0x03 : 0x02);