/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; local 416 dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 421 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 422 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 425 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 451 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; local 494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 495 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 502 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | clk_mgr.h | 52 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 60 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 70 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 80 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 89 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk 96 uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass 174 uint32_t dcfclk; member in struct:clk_state_registers_and_bypass 189 uint32_t CLK0_CLK8_CURRENT_CNT; //dcfclk 195 uint32_t CLK0_CLK8_BYPASS_CNTL; //dcfclk bypass 204 uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
H A D | dcn_calc_auto.c | 1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; 1226 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0 * v->percent_of_ideal_drambw_received_after_urg_latency / 100.0); 1234 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { 1235 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); 1237 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0); 1239 v->return_bw =dcn_bw_min2(v->return_bw, dcn_bw_pow(4.0 * v->return_bandwidth_to_dcn * (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 * v->return_bus_width * v->dcfclk * v->urgent_latency / (v->return_bandwidth_to_dcn * v->urgent_latency + (v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0), 2)); 1241 v->return_bandwidth_to_dcn =dcn_bw_min2(v->return_bus_width * v->dcfclk, v->fabric_and_dram_bandwidth * 1000.0); 1242 if (v->dcc_enabled_any_plane == dcn_bw_yes && v->return_bandwidth_to_dcn > v->dcfclk * v->return_bus_width / 4.0) { 1243 v->return_bw =dcn_bw_min2(v->return_bw, v->return_bandwidth_to_dcn * 4.0 * (1.0 - v->urgent_latency / ((v->rob_buffer_size_in_kbyte - v->pixel_chunk_size_in_kbyte) * 1024.0 / (v->return_bandwidth_to_dcn - v->dcfclk * v->return_bus_width / 4.0) + v->urgent_latency))); 1245 v->critical_compression = 2.0 * v->return_bus_width * v->dcfclk * [all...] |
H A D | dcn_calcs.c | 494 input->clks_cfg.dcfclk_mhz = v->dcfclk; 577 v->dcfclk = v->dcfclkv_nom0p8; 598 v->dcfclk = v->dcfclkv_max0p9; 618 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; 1163 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); 1429 /*find that level conresponding dcfclk*/
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | dcn_calcs.h | 213 float dcfclk; member in struct:dcn_bw_internal_vars
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 315 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 341 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 342 regs_and_bypass->dcfclk, 376 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", 470 /* dcfclk wil be used to select WM*/
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 247 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 273 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 274 regs_and_bypass->dcfclk, 308 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 590 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - " 679 !dc->work_arounds.clock_update_disable_mask.dcfclk) { 925 //Get dcfclk in khz 926 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.c | 479 unsigned int dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; local 507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2298 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; local 2410 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; 2412 dcfclk = 615; //DCFCLK Vmin_lv 2415 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2445 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; 2447 dcfclk = 615; //DCFCLK Vmin_lv 2450 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 3187 // Calculate optimal dcfclk fo [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc.h | 297 uint8_t dcfclk : 1; member in struct:dc_bug_wa::__anon202
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