Searched refs:reg_mask (Results 1 - 25 of 42) sorted by last modified time

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/linux-master/kernel/bpf/
H A Dverifier.c3526 static void fmt_reg_mask(char *buf, ssize_t buf_sz, u32 reg_mask) argument
3534 bitmap_from_u64(mask, reg_mask);
3894 * to track above reg_mask/stack_mask needs to be independent for each frame.
4243 verbose(env, "BUG backtracking func entry subprog %d reg_mask %x stack_mask %llx\n",
4276 * and there are still reg_mask or stack_mask
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2_core.c171 value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
173 dwxgmac2_route_possibilities[packet - 1].reg_mask;
1672 mac->mii.reg_mask = GENMASK(15, 0);
1714 mac->mii.reg_mask = GENMASK(15, 0);
H A Ddwmac4_core.c172 value &= ~route_possibilities[packet - 1].reg_mask;
174 route_possibilities[packet - 1].reg_mask;
1397 mac->mii.reg_mask = GENMASK(20, 16);
H A Ddwmac100_core.c190 mac->mii.reg_mask = 0x000007C0;
H A Ddwmac1000_core.c554 mac->mii.reg_mask = 0x000007C0;
H A Ddwmac-sun8i.c1113 mac->mii.reg_mask = GENMASK(8, 4);
H A Dcommon.h582 unsigned int reg_mask; /* MII reg mask */ member in struct:mii_regs
617 u32 reg_mask; member in struct:stmmac_rx_routing
H A Dstmmac_mdio.c288 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
328 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
333 value &= ~priv->hw->mii.reg_mask;
334 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
387 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
428 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
435 value &= ~priv->hw->mii.reg_mask;
436 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
/linux-master/drivers/tty/serial/8250/
H A D8250_aspeed_vuart.c383 u32 reg_offset, u32 reg_mask)
399 aspeed_vuart_set_sirq_polarity(vuart, (value & reg_mask) == 0);
381 aspeed_vuart_auto_configure_sirq_polarity( struct aspeed_vuart *vuart, struct device_node *syscon_np, u32 reg_offset, u32 reg_mask) argument
/linux-master/sound/core/oss/
H A Dpcm_oss.c3143 pcm->oss.reg_mask |= 1;
3148 pcm->oss.reg_mask |= 2;
3160 if (pcm->oss.reg_mask & 1) {
3161 pcm->oss.reg_mask &= ~1;
3165 if (pcm->oss.reg_mask & 2) {
3166 pcm->oss.reg_mask &= ~2;
/linux-master/drivers/power/reset/
H A Datc260x-poweroff.c25 uint reg_mask, reg_val; local
44 reg_mask = ATC2603C_PMU_SYS_CTL3_EN_S2 | ATC2603C_PMU_SYS_CTL3_EN_S3;
46 ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL3, reg_mask,
54 reg_mask = restart ? ATC2603C_PMU_SYS_CTL0_RESTART_EN
60 reg_mask, reg_val);
76 uint reg_mask, reg_val; local
95 reg_mask = ATC2609A_PMU_SYS_CTL3_EN_S2 | ATC2609A_PMU_SYS_CTL3_EN_S3;
97 ret = regmap_update_bits(pwrc->regmap, ATC2609A_PMU_SYS_CTL3, reg_mask,
105 reg_mask = restart ? ATC2609A_PMU_SYS_CTL0_RESTART_EN
111 reg_mask, reg_va
[all...]
/linux-master/drivers/net/wireless/realtek/rtw89/
H A Dphy.c3749 u32 reg_mask; local
3752 reg_mask = xtal->sc_xo_mask;
3754 reg_mask = xtal->sc_xi_mask;
3756 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
3763 u32 reg_mask; local
3766 reg_mask = xtal->sc_xo_mask;
3768 reg_mask = xtal->sc_xi_mask;
3770 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
/linux-master/drivers/net/wireless/marvell/mwifiex/
H A Dfw.h2349 struct host_cmd_ds_mgmt_frame_reg reg_mask; member in union:host_cmd_ds_command::__anon1065
/linux-master/drivers/net/dsa/microchip/
H A Dksz_common.c2132 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
2237 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2251 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
H A Dksz_common.h88 u16 reg_mask; member in struct:ksz_irq
/linux-master/drivers/memory/
H A Dstm32-fmc2-ebi.c215 * @reg_mask: the bit that have to be modified in the selected register
231 u32 reg_mask; member in struct:stm32_fmc2_prop
505 regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
506 setup ? prop->reg_mask : 0);
934 .reg_mask = FMC2_BCR1_CCLKEN,
942 .reg_mask = FMC2_BCR_MUXEN,
955 .reg_mask = FMC2_BCR_WAITPOL,
962 .reg_mask = FMC2_BCR_WAITCFG,
970 .reg_mask = FMC2_BCR_WAITEN,
978 .reg_mask
[all...]
/linux-master/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.c55 unsigned long reg_mask; local
60 reg_mask = bank->pctl_offset + bank->eint_mask_offset;
62 reg_mask = our_chip->eint_mask + bank->eint_offset;
66 mask = readl(bank->eint_base + reg_mask);
68 writel(mask, bank->eint_base + reg_mask);
93 unsigned long reg_mask; local
109 reg_mask = bank->pctl_offset + bank->eint_mask_offset;
111 reg_mask = our_chip->eint_mask + bank->eint_offset;
115 mask = readl(bank->eint_base + reg_mask);
117 writel(mask, bank->eint_base + reg_mask);
[all...]
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-al.c126 u8 reg_mask; member in struct:al_pcie_target_bus_cfg
225 unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
233 target_bus_cfg->reg_mask);
268 target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
269 target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;
272 target_bus_cfg->reg_mask);
/linux-master/drivers/pmdomain/qcom/
H A Dcpr.c462 u32 val, error_steps, reg_mask; local
498 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
499 reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
500 val = reg_mask;
501 cpr_ctl_modify(drv, reg_mask, val);
535 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
538 cpr_ctl_modify(drv, reg_mask, val);
567 reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
571 reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
572 reg_mask <<
[all...]
/linux-master/drivers/net/phy/
H A Dnxp-tja11xx.c291 u16 reg_mask, reg_val; local
304 reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
309 reg_mask |= MII_CFG1_INTERFACE_MODE_MASK;
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
320 reg_mask = MII_CFG1_INTERFACE_MODE_MASK;
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
/linux-master/drivers/media/i2c/
H A Dmt9m111.c142 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ macro
225 unsigned int reg_mask; member in struct:mt9m111_mode_info
258 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
267 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
277 .reg_mask = MT9M111_RM_PWR_MASK | MT9M111_RM_SKIP2_MASK,
939 mt9m111->current_mode->reg_mask);
/linux-master/drivers/gpu/drm/imagination/
H A Dpvr_device.h564 * @reg_mask: Mask of bits valid for comparison with @reg_value.
573 u32 reg_mask, u64 timeout_usec)
578 (value & reg_mask) == reg_value, 0, timeout_usec);
587 * @reg_mask: Mask of bits valid for comparison with @reg_value.
596 u64 reg_mask, u64 timeout_usec)
601 (value & reg_mask) == reg_value, 0, timeout_usec);
572 pvr_cr_poll_reg32(struct pvr_device *pvr_dev, u32 reg_addr, u32 reg_value, u32 reg_mask, u64 timeout_usec) argument
595 pvr_cr_poll_reg64(struct pvr_device *pvr_dev, u32 reg_addr, u64 reg_value, u64 reg_mask, u64 timeout_usec) argument
/linux-master/drivers/clk/samsung/
H A Dclk-pll.c80 unsigned int reg_mask)
99 if (readl_relaxed(pll->con_reg) & reg_mask)
107 val & reg_mask, 0, PLL_TIMEOUT_US);
79 samsung_pll_lock_wait(struct samsung_clk_pll *pll, unsigned int reg_mask) argument
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dqat_hal.c1378 unsigned short reg_mask; local
1396 reg_mask = (unsigned short)~0x1f;
1398 reg_mask = (unsigned short)~0xf;
1400 if (reg_num & reg_mask)
/linux-master/drivers/pinctrl/ti/
H A Dpinctrl-ti-iodelay.c219 u32 reg_mask, reg_val, tmp_val; local
238 reg_mask = reg->signature_mask;
241 reg_mask |= reg->binary_data_coarse_mask;
250 reg_mask |= reg->binary_data_fine_mask;
265 reg_mask |= reg->lock_mask;
267 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val);

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