Searched refs:reg_base (Results 1 - 25 of 407) sorted by last modified time

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/linux-master/sound/soc/codecs/
H A Drt722-sdca.h46 unsigned int reg_base; member in struct:rt722_sdca_dmic_kctrl_priv
H A Drt722-sdca.c606 regmap_read(rt722->mbq_regmap, p->reg_base + i, &regvalue);
643 regmap_read(rt722->mbq_regmap, p->reg_base + i, &regvalue[i]);
664 err = regmap_write(rt722->mbq_regmap, p->reg_base + i, gain_val[i]);
667 __func__, p->reg_base + i);
675 {.reg_base = xreg_base, .count = xcount, .max = xmax, \
678 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
683 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
685 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
693 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
H A Drt715-sdca.c171 unsigned int reg_base = p->reg_base, k_changed = 0; local
188 ret = regmap_write(rt715->mbq_regmap, reg_base + i,
192 __func__, reg_base + i, gain_val);
207 unsigned int reg_base = p->reg_base, i, k_changed = 0; local
224 reg = i < 7 ? reg_base + i : (reg_base - 1) | BIT(15);
266 unsigned int reg_base = p->reg_base, local
291 unsigned int reg_base = p->reg_base; local
328 unsigned int reg_base = p->reg_base; local
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H A Drt712-sdca-dmic.c262 regmap_read(rt712->mbq_regmap, p->reg_base + i, &regvalue);
297 regmap_read(rt712->mbq_regmap, p->reg_base + i, &regvalue[i]);
318 err = regmap_write(rt712->mbq_regmap, p->reg_base + i, gain_val[i]);
321 __func__, p->reg_base + i);
399 {.reg_base = xreg_base, .count = xcount, .max = xmax, \
402 #define RT712_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
407 .private_value = RT712_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
409 #define RT712_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
417 .private_value = RT712_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
/linux-master/include/linux/
H A Dregmap.h260 * @reg_base: Value to be added to every register address before performing any
398 unsigned int reg_base; member in struct:regmap_config
/linux-master/drivers/base/regmap/
H A Dregmap.c759 map->reg_base = config->reg_base;
1589 reg += map->reg_base;
/linux-master/drivers/dma/xilinx/
H A Dxdma.c1204 void __iomem *reg_base; local
1235 reg_base = devm_ioremap_resource(&pdev->dev, res);
1236 if (IS_ERR(reg_base)) {
1241 xdev->rmap = devm_regmap_init_mmio(&pdev->dev, reg_base,
/linux-master/drivers/dma/idxd/
H A Dirq.c369 idxd->reg_base + IDXD_EVLSTATUS_OFFSET + sizeof(u32));
370 evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
382 iowrite32(evl_status.bits_lower32, idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
397 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET);
401 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET);
409 idxd->sw_err.bits[i] = ioread64(idxd->reg_base +
413 idxd->reg_base + IDXD_SWERR_OFFSET);
487 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
H A Didxd.h329 void __iomem *reg_base; member in struct:idxd_device
513 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
515 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET);
H A Dinit.c430 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
431 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
461 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
465 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
482 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
492 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
498 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
509 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
517 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
736 idxd->reg_base
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H A Ddevice.c25 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
28 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
35 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET);
38 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET);
312 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
316 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
350 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset);
353 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset);
435 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET);
446 gensts.bits = ioread32(idxd->reg_base
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H A Dcdev.c346 status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
H A Ddebugfs.c71 evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET);
/linux-master/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt.c9113 u32 reg_base = 0xffffffff; local
9124 if (reg_base == 0xffffffff)
9125 reg_base = reg & BNXT_GRC_BASE_MASK;
9126 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
9132 if (reg_base == 0xffffffff)
9135 __bnxt_map_fw_health_reg(bp, reg_base);
/linux-master/drivers/mtd/nand/raw/
H A Dqcom_nandc.c776 int reg_base = NAND_READ_LOCATION_0; local
779 reg_base = NAND_READ_LOCATION_LAST_CW_0;
781 reg_base += reg * 4;
784 return nandc_set_read_loc_last(chip, reg_base, cw_offset,
787 return nandc_set_read_loc_first(chip, reg_base, cw_offset,
/linux-master/drivers/gpio/
H A Dgpio-tangier.c69 return priv->reg_base + reg + reg_offset * 4;
80 return priv->reg_base + reg + reg_offset * 4;
H A Dgpio-lpc32xx.c165 void __iomem *reg_base; member in struct:lpc32xx_gpio_chip
170 return __raw_readl(group->reg_base + offset);
175 __raw_writel(val, group->reg_base + offset);
508 void __iomem *reg_base; local
510 reg_base = devm_platform_ioremap_resource(pdev, 0);
511 if (IS_ERR(reg_base))
512 return PTR_ERR(reg_base);
519 lpc32xx_gpiochip[i].reg_base = reg_base;
/linux-master/drivers/net/ethernet/ti/
H A Dam65-cpsw-nuss.c2044 void __iomem *reg_base; local
2055 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE;
2056 cpts = am65_cpts_create(dev, reg_base, node);
/linux-master/drivers/net/ethernet/mediatek/
H A Dmtk_wed.c2487 ring->reg_base = MTK_WED_RING_TX(idx);
2532 ring->reg_base = MTK_WED_RING_RX(index);
2562 ring->reg_base = MTK_WED_RING_RX_DATA(idx);
/linux-master/drivers/media/platform/mediatek/vcodec/encoder/
H A Dmtk_vcodec_enc_drv.c103 addr = dev->reg_base[core_id] + MTK_VENC_IRQ_ACK_OFFSET;
105 ctx->irq_status = readl(dev->reg_base[core_id] +
274 dev->reg_base[dev->venc_pdata->core_id] =
276 if (IS_ERR(dev->reg_base[dev->venc_pdata->core_id])) {
277 ret = PTR_ERR(dev->reg_base[dev->venc_pdata->core_id]);
H A Dmtk_vcodec_enc_drv.h173 * @reg_base: Mapped address of MTK Vcodec registers.
200 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE]; member in struct:mtk_vcodec_enc_dev
/linux-master/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp8_if.c144 * @reg_base : HW register base address
158 struct vdec_vp8_hw_reg_base reg_base; member in struct:vdec_vp8_inst
167 void __iomem **reg_base = inst->ctx->dev->reg_base; local
169 inst->reg_base.top = mtk_vcodec_get_reg_addr(reg_base, VDEC_TOP);
170 inst->reg_base.cm = mtk_vcodec_get_reg_addr(reg_base, VDEC_CM);
171 inst->reg_base.hwd = mtk_vcodec_get_reg_addr(reg_base, VDEC_HW
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/linux-master/drivers/media/platform/mediatek/vcodec/decoder/
H A Dmtk_vcodec_dec_drv.h235 * @reg_base: Mapped address of MTK Vcodec registers.
276 void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE]; member in struct:mtk_vcodec_dec_dev
H A Dmtk_vcodec_dec_drv.c50 cg_status = readl(dev->reg_base[VDEC_SYS] + VDEC_HW_ACTIVE_ADDR);
59 void __iomem *vdec_misc_addr = dev->reg_base[VDEC_MISC] +
77 dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG);
79 dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG);
134 dev->reg_base[i] = devm_platform_ioremap_resource(pdev, i);
135 if (IS_ERR(dev->reg_base[i]))
136 return PTR_ERR(dev->reg_base[i]);
138 dev_dbg(&pdev->dev, "reg[%d] base=%p", i, dev->reg_base[i]);
142 dev->reg_base[i+1] = devm_platform_ioremap_resource_byname(pdev, mtk_dec_reg_names[i]);
143 if (IS_ERR(dev->reg_base[
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/linux-master/drivers/spi/
H A Dspi-pci1xxxx.c160 void __iomem *reg_base; member in struct:pci1xxxx_spi
196 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG);
197 return readl(par->reg_base + SPI_SYSLOCK_REG);
211 writel(0x0, par->reg_base + SPI_SYSLOCK_REG);
231 regval = readl(spi_bus->reg_base + DEV_REV_REG);
234 regval = readl(spi_bus->reg_base +
309 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
317 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));
388 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));
397 writel(regval, par->reg_base
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Completed in 298 milliseconds

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