/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_resource_helpers.c | 317 uint8_t pipe_cnt = 0; local 368 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 371 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; 372 pipe_cnt++; 383 int i, pipe_cnt; local 388 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 394 pipe_cnt++; 401 if (pipe_cnt == 1) { 746 int i, pipe_cnt; local 750 for (i = 0, pipe_cnt [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 994 int pipe_cnt, i; local 998 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1006 pipes[pipe_cnt].dout.num_active_wb++; 1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1011 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; 1012 pipes[pipe_cnt] 1030 dcn20_fpu_set_wb_arb_params(struct mcif_arb_params *wb_arb_params, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int i) argument 1140 dcn20_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 1319 int pipe_cnt, i; local 1735 int pipe_cnt, i, pipe_idx; local 2035 int pipe_cnt = 0; local 2158 uint32_t pipe_cnt; local 2204 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 2241 int pipe_cnt, i, pipe_idx; local 2327 int pipe_cnt = 0; local 2477 int pipe_cnt, i, j; local [all...] |
H A D | dcn20_fpu.h | 38 int pipe_cnt, int i); 42 int pipe_cnt,
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 260 int pipe_cnt, i, j; local 267 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 275 pipes[pipe_cnt].dout.wb_enable = 0; 276 pipes[pipe_cnt].dout.num_active_wb = 0; 282 pipes[pipe_cnt].dout.wb_enable = 1; 283 pipes[pipe_cnt].dout.num_active_wb++; 326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 333 pipes[pipe_cnt].pipe.dest.htotal, 338 pipes[pipe_cnt].dout.wb = dout_wb; 343 pipe_cnt 347 dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt, int cur_pipe) argument 379 dcn30_fpu_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 691 dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
H A D | dcn30_fpu.h | 41 int pipe_cnt, 49 int pipe_cnt, 69 int pipe_cnt,
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
H A D | dcn301_fpu.c | 297 int pipe_cnt) 311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 312 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 317 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 318 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 415 int pipe_cnt, 292 calculate_wm_set_for_vlevel(int vlevel, struct wm_range_table_entry *table_entry, struct dcn_watermarks *wm_set, struct display_mode_lib *dml, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 412 dcn301_calculate_wm_and_dlg_fp(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel_req) argument [all...] |
H A D | dcn301_fpu.h | 40 int pipe_cnt,
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 446 int pipe_cnt) 450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; 451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; 485 int pipe_cnt, 501 if (pipe_cnt == 0) { 511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 513 if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_time && 523 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 524 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 525 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 100 445 dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 482 dcn31_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument [all...] |
H A D | dcn31_fpu.h | 36 int pipe_cnt); 44 int pipe_cnt,
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | dcn314_fpu.c | 311 int i, pipe_cnt; local 321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; 336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; 340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 346 pipes[pipe_cnt].pipe.dest.vblank_nom = 347 max(pipes[pipe_cnt] [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.c | 278 int pipe_cnt, 293 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 327 * @pipe_cnt: [in] DML pipe count 336 int pipe_cnt) 350 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 352 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 354 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 356 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 451 * @pipe_cnt: number of DML pipes 471 unsigned int pipe_cnt, 275 dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 333 dcn32_helper_populate_phantom_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 466 dcn32_set_phantom_stream_timing(struct dc *dc, struct dc_state *context, struct pipe_ctx *ref_pipe, struct dc_stream_state *phantom_stream, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument 1387 try_odm_power_optimization_and_revalidate( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *split, bool *merge, unsigned int *vlevel, int pipe_cnt) argument 1431 dcn32_full_validate_bw_helper(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *vlevel, int *split, bool *merge, int *pipe_cnt, bool *repopulate_pipes) argument 1637 dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 2141 int pipe_cnt, i, pipe_idx; local 2292 dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 3351 dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, int pipe_cnt) argument [all...] |
H A D | dcn32_fpu.h | 37 int pipe_cnt); 44 unsigned int pipe_cnt, 56 int pipe_cnt, 64 int pipe_cnt, 70 int pipe_cnt);
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
H A D | dcn35_fpu.c | 440 int i, pipe_cnt; local 449 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 466 pipes[pipe_cnt].pipe.dest.vtotal = 468 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - 469 pipes[pipe_cnt].pipe.dest.vactive; 472 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 473 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 478 pipes[pipe_cnt] [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
H A D | dcn351_fpu.c | 474 int i, pipe_cnt; local 483 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 500 pipes[pipe_cnt].pipe.dest.vtotal = 502 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - 503 pipes[pipe_cnt].pipe.dest.vactive; 506 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; 507 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); 512 pipes[pipe_cnt] [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
H A D | display_mode_lib.c | 163 int pipe_cnt) 173 for (i = 0; i < pipe_cnt; i++) { 160 dml_log_pipe_params( struct display_mode_lib *mode_lib, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
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H A D | display_mode_lib.h | 106 int pipe_cnt);
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/linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
H A D | dml2_utils.c | 287 void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt) argument 307 if (unbounded_req_enabled && pipe_cnt > 1) { 315 for (dc_pipe_ctx_index = 0; dc_pipe_ctx_index < pipe_cnt; dc_pipe_ctx_index++) {
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H A D | dml2_utils.h | 116 * @pipe_cnt : DML functions to obtain RQ, TTu and DLG params need a pipe_index. 117 * This helps provide pipe_index in the pipe_cnt loop. 122 void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *context, struct resource_context *out_new_hw_state, struct dml2_context *in_ctx, unsigned int pipe_cnt);
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | core_types.h | 88 int pipe_cnt, 178 int pipe_cnt); 203 unsigned int pipe_cnt,
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
H A D | dcn20_resource.c | 1617 int pipe_cnt) 1646 dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i); 2036 int pipe_cnt, i, pipe_idx, vlevel; local 2045 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 2048 *pipe_cnt_out = pipe_cnt; 2050 if (!pipe_cnt) { 2055 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1613 dcn20_set_mcif_arb_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
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H A D | dcn20_resource.h | 121 int pipe_cnt);
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
H A D | dcn21_resource.c | 777 int pipe_cnt, i, pipe_idx, vlevel; local 786 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 789 *pipe_cnt_out = pipe_cnt; 791 if (!pipe_cnt) { 802 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 814 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
H A D | dcn30_resource.c | 1325 int i, pipe_cnt; local 1332 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1336 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = 1340 return pipe_cnt; 1378 int pipe_cnt) 1408 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); 1642 int pipe_cnt, i, pipe_idx, vlevel = 0; local 1653 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1655 if (!pipe_cnt) { 1660 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1374 dcn30_set_mcif_arb_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument 2027 dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument 2047 int pipe_cnt = 0; local [all...] |
H A D | dcn30_resource.h | 52 int pipe_cnt); 72 int pipe_cnt, 106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
H A D | dcn301_resource.c | 1369 int pipe_cnt, 1373 dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1366 dcn301_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
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