Searched refs:new_ctx (Results 1 - 25 of 50) sorted by path

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/linux-master/arch/powerpc/include/asm/
H A Dsyscalls.h54 struct ucontext __user *new_ctx, long ctx_size);
76 struct ucontext32 __user *new_ctx,
/linux-master/arch/powerpc/kernel/
H A Dsignal_32.c991 struct ucontext __user *, new_ctx, int, ctx_size)
994 struct ucontext __user *, new_ctx, long, ctx_size)
1003 if (new_ctx) {
1012 if (__get_user(cmcp, &new_ctx->uc_regs))
1061 if (new_ctx == NULL)
1063 if (!access_ok(new_ctx, ctx_size) ||
1064 fault_in_readable((char __user *)new_ctx, ctx_size))
1078 if (do_setcontext(new_ctx, regs, 0)) {
H A Dsignal_64.c658 struct ucontext __user *, new_ctx, long, ctx_size)
664 if (new_ctx &&
665 get_user(new_msr, &new_ctx->uc_mcontext.gp_regs[PT_MSR]))
696 if (new_ctx == NULL)
698 if (!access_ok(new_ctx, ctx_size) ||
699 fault_in_readable((char __user *)new_ctx, ctx_size))
714 if (__get_user_sigset(&set, &new_ctx->uc_sigmask)) {
720 if (!user_read_access_begin(new_ctx, ctx_size))
722 if (__unsafe_restore_sigcontext(current, NULL, 0, &new_ctx->uc_mcontext)) {
/linux-master/arch/sparc/mm/
H A Dinit_64.c769 unsigned long new_ver, new_ctx, old_ctx; local
806 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
807 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
808 mm->context.sparc64_ctx_val = new_ctx;
825 unsigned long ctx, new_ctx; local
835 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
836 if (new_ctx >= (1 << CTX_NR_BITS)) {
837 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
838 if (new_ctx >= ctx) {
845 mmu_context_bmap[new_ctx>>
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2511 enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx, argument
2517 return dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
2640 struct dc_state *new_ctx,
2655 new_ctx,
2661 &new_ctx->res_ctx, pool,
2665 sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
2692 struct dc_state *new_ctx,
2701 plane_state, new_ctx);
2704 otg_master_pipe, plane_state, new_ctx,
2709 plane_state, new_ctx, poo
2637 acquire_secondary_dpp_pipes_and_add_plane( struct pipe_ctx *otg_master_pipe, struct dc_plane_state *plane_state, struct dc_state *new_ctx, struct dc_state *cur_ctx, struct resource_pool *pool) argument
2691 resource_append_dpp_pipes_for_plane_composition( struct dc_state *new_ctx, struct dc_state *cur_ctx, struct resource_pool *pool, struct pipe_ctx *otg_master_pipe, struct dc_plane_state *plane_state) argument
2778 acquire_pipes_and_add_odm_slice( struct pipe_ctx *otg_master_pipe, struct dc_state *new_ctx, const struct dc_state *cur_ctx, const struct resource_pool *pool) argument
2917 acquire_dpp_pipe_and_add_mpc_slice( struct pipe_ctx *dpp_pipe, struct dc_state *new_ctx, const struct dc_state *cur_ctx, const struct resource_pool *pool) argument
3005 resource_update_pipes_for_stream_with_slice_count( struct dc_state *new_ctx, const struct dc_state *cur_ctx, const struct resource_pool *pool, const struct dc_stream_state *stream, int new_slice_count) argument
3035 resource_update_pipes_for_plane_with_slice_count( struct dc_state *new_ctx, const struct dc_state *cur_ctx, const struct resource_pool *pool, const struct dc_plane_state *plane, int new_slice_count) argument
3430 acquire_otg_master_pipe_for_stream( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, struct dc_stream_state *stream) argument
3905 dc_validate_global_state( struct dc *dc, struct dc_state *new_ctx, bool fast_validate) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc.h1501 struct dc_state *new_ctx,
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_wrapper.h78 struct dc_state *new_ctx,
84 struct dc_state *new_ctx,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c1665 const struct dc_state *new_ctx)
1673 new_pipe = &new_ctx->res_ctx.pipe_ctx[i];
1663 dcn32_is_pipe_topology_transition_seamless(struct dc *dc, const struct dc_state *cur_ctx, const struct dc_state *new_ctx) argument
H A Ddcn32_hwseq.h127 const struct dc_state *new_ctx);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h432 const struct dc_state *new_ctx);
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h135 struct dc_state *new_ctx,
141 struct dc_state *new_ctx,
155 struct dc_state *new_ctx,
160 struct dc_state *new_ctx,
H A Dresource.h283 enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
292 void resource_remove_otg_master_for_stream_output(struct dc_state *new_ctx,
302 struct dc_state *new_ctx,
329 * an indication of insufficient validation in caller's stack. new_ctx will be
330 * invalid. Caller may attempt to restore new_ctx by calling this function
334 struct dc_state *new_ctx,
353 * an indication of insufficient validation in caller's stack. new_ctx will be
354 * invalid. Caller may attempt to restore new_ctx by calling this function
358 struct dc_state *new_ctx,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c896 struct dc_state *new_ctx,
901 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
904 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
907 result = build_mapped_resource(dc, new_ctx, dc_stream);
894 dce100_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
H A Ddce100_resource.h46 struct dc_state *new_ctx,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c1104 struct dc_state *new_ctx,
1109 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1112 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
1116 result = build_mapped_resource(dc, new_ctx, dc_stream);
1123 struct dc_state *new_ctx,
1130 struct resource_context *res_ctx = &new_ctx->res_ctx;
1178 new_ctx->stream_count);
1102 dce110_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1121 dce110_acquire_underlay( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) argument
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c1015 struct dc_state *new_ctx,
1020 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1023 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1027 result = build_mapped_resource(dc, new_ctx, dc_stream);
1013 dce112_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
H A Ddce112_resource.h52 struct dc_state *new_ctx,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c1074 struct dc_state *new_ctx,
1079 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1082 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1086 result = build_mapped_resource(dc, new_ctx, dc_stream);
1093 struct dc_state *new_ctx,
1097 struct resource_context *res_ctx = &new_ctx->res_ctx;
1072 dcn10_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1091 dcn10_acquire_free_pipe_for_layer( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) argument
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1402 struct dc_state *new_ctx,
1409 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1410 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1413 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1424 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1428 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1431 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1435 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1438 result = dcn20_build_mapped_resource(dc, new_ctx, dc_strea
1401 remove_dsc_from_stream_resource(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1444 dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1665 dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) argument
2165 dcn20_acquire_free_pipe_for_layer( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head) argument
[all...]
H A Ddcn20_resource.h63 struct dc_state *new_ctx,
135 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx);
164 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
166 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c1000 struct dc_state *new_ctx,
1004 struct resource_context *res_ctx = &new_ctx->res_ctx;
998 dcn201_acquire_free_pipe_for_layer( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) argument
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1281 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1284 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
H A Ddcn30_resource.h98 struct dc_state *new_ctx,
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c2726 struct dc_state *new_ctx,
2736 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
2739 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2742 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2763 struct dc_state *new_ctx,
2768 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2773 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2787 &new_ctx->res_ctx,
2724 dcn32_acquire_free_pipe_as_secondary_dpp_pipe( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) argument
2761 dcn32_acquire_free_pipe_as_secondary_opp_head( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *otg_master) argument
H A Ddcn32_resource.h148 struct dc_state *new_ctx,
154 struct dc_state *new_ctx,

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