Searched refs:gws_size (Results 1 - 23 of 23) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/include/
H A Dmes_v11_api_def.h284 uint32_t gws_size; member in struct:MESAPI__ADD_QUEUE::__anon416
517 uint32_t gws_size; member in struct:MESAPI__PROGRAM_GDS::__anon431
546 uint32_t gws_size; member in struct:MESAPI__SET_DEBUG_VMID::__anon432
H A Dmes_api_def.h252 uint32_t gws_size; member in struct:MESAPI__ADD_QUEUE::__anon263
464 uint32_t gws_size; member in struct:MESAPI__PROGRAM_GDS::__anon278
492 uint32_t gws_size; member in struct:MESAPI__SET_DEBUG_VMID::__anon279
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device.c541 node->adev->gds.gws_size, &node->gws);
569 node->adev->gds.gws_size);
H A Dkfd_topology.c2024 dev->gpu->adev->gds.gws_size : 0;
H A Dkfd_process_queue_manager.c149 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c291 mes_add_queue_pkt.gws_size = input->gws_size;
H A Dmes_v10_1.c181 mes_add_queue_pkt.gws_size = input->gws_size;
H A Dgfx_v9_4_3.c2216 uint32_t gws_base, uint32_t gws_size,
2234 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4162 adev->gds.gws_size = 64;
2213 gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) argument
H A Dgfx_v9_0.c4035 uint32_t gws_base, uint32_t gws_size,
4053 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7160 adev->gds.gws_size = 64;
4032 gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) argument
H A Dgfx_v8_0.c5156 uint32_t gws_base, uint32_t gws_size,
5181 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7054 adev->gds.gws_size = 64;
5153 gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) argument
H A Dgfx_v7_0.c4039 uint32_t gws_base, uint32_t gws_size,
4064 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5090 adev->gds.gws_size = 64;
4036 gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) argument
H A Dgfx_v11_0.c4685 uint32_t gws_base, uint32_t gws_size,
4703 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
6363 adev->gds.gws_size = 64;
4682 gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) argument
H A Dgfx_v10_0.c7522 uint32_t gws_base, uint32_t gws_size,
7540 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
9519 adev->gds.gws_size = 64;
7519 gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, uint32_t vmid, uint32_t gds_base, uint32_t gds_size, uint32_t gws_base, uint32_t gws_size, uint32_t oa_base, uint32_t oa_size) argument
H A Damdgpu_vm.c709 job->gws_size, job->oa_base,
H A Damdgpu_ttm.c1983 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
H A Damdgpu_mes.h235 uint32_t gws_size; member in struct:mes_add_queue_input
H A Damdgpu_kms.c716 gds_info.gws_per_compute_partition = adev->gds.gws_size;
H A Damdgpu_job.c156 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
H A Damdgpu_ring.h201 uint32_t gws_base, uint32_t gws_size,
H A Damdgpu_ids.c174 id->gws_size != job->gws_size ||
446 id->gws_size = job->gws_size;
516 id->gws_size = 0;
H A Damdgpu_job.h62 uint32_t gws_base, gws_size; member in struct:amdgpu_job
H A Damdgpu_ids.h57 uint32_t gws_size; member in struct:amdgpu_vmid
H A Damdgpu_gds.h32 uint32_t gws_size; member in struct:amdgpu_gds

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