1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#include <linux/bsearch.h> 25#include <linux/pci.h> 26#include <linux/slab.h> 27#include "kfd_priv.h" 28#include "kfd_device_queue_manager.h" 29#include "kfd_pm4_headers_vi.h" 30#include "kfd_pm4_headers_aldebaran.h" 31#include "cwsr_trap_handler.h" 32#include "amdgpu_amdkfd.h" 33#include "kfd_smi_events.h" 34#include "kfd_svm.h" 35#include "kfd_migrate.h" 36#include "amdgpu.h" 37#include "amdgpu_xcp.h" 38 39#define MQD_SIZE_ALIGNED 768 40 41/* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46static int kfd_locked; 47 48#ifdef CONFIG_DRM_AMDGPU_CIK 49extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50#endif 51extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 60static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 61 unsigned int chunk_size); 62static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 63 64static int kfd_resume(struct kfd_node *kfd); 65 66static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 67{ 68 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 69 70 switch (sdma_version) { 71 case IP_VERSION(4, 0, 0):/* VEGA10 */ 72 case IP_VERSION(4, 0, 1):/* VEGA12 */ 73 case IP_VERSION(4, 1, 0):/* RAVEN */ 74 case IP_VERSION(4, 1, 1):/* RAVEN */ 75 case IP_VERSION(4, 1, 2):/* RENOIR */ 76 case IP_VERSION(5, 2, 1):/* VANGOGH */ 77 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 78 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 79 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 80 kfd->device_info.num_sdma_queues_per_engine = 2; 81 break; 82 case IP_VERSION(4, 2, 0):/* VEGA20 */ 83 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 84 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 85 case IP_VERSION(4, 4, 2): 86 case IP_VERSION(5, 0, 0):/* NAVI10 */ 87 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 88 case IP_VERSION(5, 0, 2):/* NAVI14 */ 89 case IP_VERSION(5, 0, 5):/* NAVI12 */ 90 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 91 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 92 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 93 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 94 case IP_VERSION(6, 0, 0): 95 case IP_VERSION(6, 0, 1): 96 case IP_VERSION(6, 0, 2): 97 case IP_VERSION(6, 0, 3): 98 case IP_VERSION(6, 1, 0): 99 case IP_VERSION(6, 1, 1): 100 kfd->device_info.num_sdma_queues_per_engine = 8; 101 break; 102 default: 103 dev_warn(kfd_device, 104 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 105 sdma_version); 106 kfd->device_info.num_sdma_queues_per_engine = 8; 107 } 108 109 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); 110 111 switch (sdma_version) { 112 case IP_VERSION(6, 0, 0): 113 case IP_VERSION(6, 0, 1): 114 case IP_VERSION(6, 0, 2): 115 case IP_VERSION(6, 0, 3): 116 case IP_VERSION(6, 1, 0): 117 case IP_VERSION(6, 1, 1): 118 /* Reserve 1 for paging and 1 for gfx */ 119 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 120 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ 121 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, 122 kfd->adev->sdma.num_instances * 123 kfd->device_info.num_reserved_sdma_queues_per_engine); 124 break; 125 default: 126 break; 127 } 128} 129 130static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 131{ 132 uint32_t gc_version = KFD_GC_VERSION(kfd); 133 134 switch (gc_version) { 135 case IP_VERSION(9, 0, 1): /* VEGA10 */ 136 case IP_VERSION(9, 1, 0): /* RAVEN */ 137 case IP_VERSION(9, 2, 1): /* VEGA12 */ 138 case IP_VERSION(9, 2, 2): /* RAVEN */ 139 case IP_VERSION(9, 3, 0): /* RENOIR */ 140 case IP_VERSION(9, 4, 0): /* VEGA20 */ 141 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 142 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 143 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 144 break; 145 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 146 kfd->device_info.event_interrupt_class = 147 &event_interrupt_class_v9_4_3; 148 break; 149 case IP_VERSION(10, 3, 1): /* VANGOGH */ 150 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 151 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 152 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 153 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 154 case IP_VERSION(10, 1, 4): 155 case IP_VERSION(10, 1, 10): /* NAVI10 */ 156 case IP_VERSION(10, 1, 2): /* NAVI12 */ 157 case IP_VERSION(10, 1, 1): /* NAVI14 */ 158 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 159 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 160 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 161 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 162 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 163 break; 164 case IP_VERSION(11, 0, 0): 165 case IP_VERSION(11, 0, 1): 166 case IP_VERSION(11, 0, 2): 167 case IP_VERSION(11, 0, 3): 168 case IP_VERSION(11, 0, 4): 169 case IP_VERSION(11, 5, 0): 170 case IP_VERSION(11, 5, 1): 171 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 172 break; 173 default: 174 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 175 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 176 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 177 } 178} 179 180static void kfd_device_info_init(struct kfd_dev *kfd, 181 bool vf, uint32_t gfx_target_version) 182{ 183 uint32_t gc_version = KFD_GC_VERSION(kfd); 184 uint32_t asic_type = kfd->adev->asic_type; 185 186 kfd->device_info.max_pasid_bits = 16; 187 kfd->device_info.max_no_of_hqd = 24; 188 kfd->device_info.num_of_watch_points = 4; 189 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 190 kfd->device_info.gfx_target_version = gfx_target_version; 191 192 if (KFD_IS_SOC15(kfd)) { 193 kfd->device_info.doorbell_size = 8; 194 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 195 kfd->device_info.supports_cwsr = true; 196 197 kfd_device_info_set_sdma_info(kfd); 198 199 kfd_device_info_set_event_interrupt_class(kfd); 200 201 if (gc_version < IP_VERSION(11, 0, 0)) { 202 /* Navi2x+, Navi1x+ */ 203 if (gc_version == IP_VERSION(10, 3, 6)) 204 kfd->device_info.no_atomic_fw_version = 14; 205 else if (gc_version == IP_VERSION(10, 3, 7)) 206 kfd->device_info.no_atomic_fw_version = 3; 207 else if (gc_version >= IP_VERSION(10, 3, 0)) 208 kfd->device_info.no_atomic_fw_version = 92; 209 else if (gc_version >= IP_VERSION(10, 1, 1)) 210 kfd->device_info.no_atomic_fw_version = 145; 211 212 /* Navi1x+ */ 213 if (gc_version >= IP_VERSION(10, 1, 1)) 214 kfd->device_info.needs_pci_atomics = true; 215 } else if (gc_version < IP_VERSION(12, 0, 0)) { 216 /* 217 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 218 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 219 * PCIe atomics support. 220 */ 221 kfd->device_info.needs_pci_atomics = true; 222 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 223 } 224 } else { 225 kfd->device_info.doorbell_size = 4; 226 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 227 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 228 kfd->device_info.num_sdma_queues_per_engine = 2; 229 230 if (asic_type != CHIP_KAVERI && 231 asic_type != CHIP_HAWAII && 232 asic_type != CHIP_TONGA) 233 kfd->device_info.supports_cwsr = true; 234 235 if (asic_type != CHIP_HAWAII && !vf) 236 kfd->device_info.needs_pci_atomics = true; 237 } 238} 239 240struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 241{ 242 struct kfd_dev *kfd = NULL; 243 const struct kfd2kgd_calls *f2g = NULL; 244 uint32_t gfx_target_version = 0; 245 246 switch (adev->asic_type) { 247#ifdef CONFIG_DRM_AMDGPU_CIK 248 case CHIP_KAVERI: 249 gfx_target_version = 70000; 250 if (!vf) 251 f2g = &gfx_v7_kfd2kgd; 252 break; 253#endif 254 case CHIP_CARRIZO: 255 gfx_target_version = 80001; 256 if (!vf) 257 f2g = &gfx_v8_kfd2kgd; 258 break; 259#ifdef CONFIG_DRM_AMDGPU_CIK 260 case CHIP_HAWAII: 261 gfx_target_version = 70001; 262 if (!amdgpu_exp_hw_support) 263 pr_info( 264 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 265 ); 266 else if (!vf) 267 f2g = &gfx_v7_kfd2kgd; 268 break; 269#endif 270 case CHIP_TONGA: 271 gfx_target_version = 80002; 272 if (!vf) 273 f2g = &gfx_v8_kfd2kgd; 274 break; 275 case CHIP_FIJI: 276 case CHIP_POLARIS10: 277 gfx_target_version = 80003; 278 f2g = &gfx_v8_kfd2kgd; 279 break; 280 case CHIP_POLARIS11: 281 case CHIP_POLARIS12: 282 case CHIP_VEGAM: 283 gfx_target_version = 80003; 284 if (!vf) 285 f2g = &gfx_v8_kfd2kgd; 286 break; 287 default: 288 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 289 /* Vega 10 */ 290 case IP_VERSION(9, 0, 1): 291 gfx_target_version = 90000; 292 f2g = &gfx_v9_kfd2kgd; 293 break; 294 /* Raven */ 295 case IP_VERSION(9, 1, 0): 296 case IP_VERSION(9, 2, 2): 297 gfx_target_version = 90002; 298 if (!vf) 299 f2g = &gfx_v9_kfd2kgd; 300 break; 301 /* Vega12 */ 302 case IP_VERSION(9, 2, 1): 303 gfx_target_version = 90004; 304 if (!vf) 305 f2g = &gfx_v9_kfd2kgd; 306 break; 307 /* Renoir */ 308 case IP_VERSION(9, 3, 0): 309 gfx_target_version = 90012; 310 if (!vf) 311 f2g = &gfx_v9_kfd2kgd; 312 break; 313 /* Vega20 */ 314 case IP_VERSION(9, 4, 0): 315 gfx_target_version = 90006; 316 if (!vf) 317 f2g = &gfx_v9_kfd2kgd; 318 break; 319 /* Arcturus */ 320 case IP_VERSION(9, 4, 1): 321 gfx_target_version = 90008; 322 f2g = &arcturus_kfd2kgd; 323 break; 324 /* Aldebaran */ 325 case IP_VERSION(9, 4, 2): 326 gfx_target_version = 90010; 327 f2g = &aldebaran_kfd2kgd; 328 break; 329 case IP_VERSION(9, 4, 3): 330 gfx_target_version = adev->rev_id >= 1 ? 90402 331 : adev->flags & AMD_IS_APU ? 90400 332 : 90401; 333 f2g = &gc_9_4_3_kfd2kgd; 334 break; 335 /* Navi10 */ 336 case IP_VERSION(10, 1, 10): 337 gfx_target_version = 100100; 338 if (!vf) 339 f2g = &gfx_v10_kfd2kgd; 340 break; 341 /* Navi12 */ 342 case IP_VERSION(10, 1, 2): 343 gfx_target_version = 100101; 344 f2g = &gfx_v10_kfd2kgd; 345 break; 346 /* Navi14 */ 347 case IP_VERSION(10, 1, 1): 348 gfx_target_version = 100102; 349 if (!vf) 350 f2g = &gfx_v10_kfd2kgd; 351 break; 352 /* Cyan Skillfish */ 353 case IP_VERSION(10, 1, 3): 354 case IP_VERSION(10, 1, 4): 355 gfx_target_version = 100103; 356 if (!vf) 357 f2g = &gfx_v10_kfd2kgd; 358 break; 359 /* Sienna Cichlid */ 360 case IP_VERSION(10, 3, 0): 361 gfx_target_version = 100300; 362 f2g = &gfx_v10_3_kfd2kgd; 363 break; 364 /* Navy Flounder */ 365 case IP_VERSION(10, 3, 2): 366 gfx_target_version = 100301; 367 f2g = &gfx_v10_3_kfd2kgd; 368 break; 369 /* Van Gogh */ 370 case IP_VERSION(10, 3, 1): 371 gfx_target_version = 100303; 372 if (!vf) 373 f2g = &gfx_v10_3_kfd2kgd; 374 break; 375 /* Dimgrey Cavefish */ 376 case IP_VERSION(10, 3, 4): 377 gfx_target_version = 100302; 378 f2g = &gfx_v10_3_kfd2kgd; 379 break; 380 /* Beige Goby */ 381 case IP_VERSION(10, 3, 5): 382 gfx_target_version = 100304; 383 f2g = &gfx_v10_3_kfd2kgd; 384 break; 385 /* Yellow Carp */ 386 case IP_VERSION(10, 3, 3): 387 gfx_target_version = 100305; 388 if (!vf) 389 f2g = &gfx_v10_3_kfd2kgd; 390 break; 391 case IP_VERSION(10, 3, 6): 392 case IP_VERSION(10, 3, 7): 393 gfx_target_version = 100306; 394 if (!vf) 395 f2g = &gfx_v10_3_kfd2kgd; 396 break; 397 case IP_VERSION(11, 0, 0): 398 gfx_target_version = 110000; 399 f2g = &gfx_v11_kfd2kgd; 400 break; 401 case IP_VERSION(11, 0, 1): 402 case IP_VERSION(11, 0, 4): 403 gfx_target_version = 110003; 404 f2g = &gfx_v11_kfd2kgd; 405 break; 406 case IP_VERSION(11, 0, 2): 407 gfx_target_version = 110002; 408 f2g = &gfx_v11_kfd2kgd; 409 break; 410 case IP_VERSION(11, 0, 3): 411 if ((adev->pdev->device == 0x7460 && 412 adev->pdev->revision == 0x00) || 413 (adev->pdev->device == 0x7461 && 414 adev->pdev->revision == 0x00)) 415 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */ 416 gfx_target_version = 110005; 417 else 418 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 419 gfx_target_version = 110001; 420 f2g = &gfx_v11_kfd2kgd; 421 break; 422 case IP_VERSION(11, 5, 0): 423 gfx_target_version = 110500; 424 f2g = &gfx_v11_kfd2kgd; 425 break; 426 case IP_VERSION(11, 5, 1): 427 gfx_target_version = 110501; 428 f2g = &gfx_v11_kfd2kgd; 429 break; 430 default: 431 break; 432 } 433 break; 434 } 435 436 if (!f2g) { 437 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 438 dev_err(kfd_device, 439 "GC IP %06x %s not supported in kfd\n", 440 amdgpu_ip_version(adev, GC_HWIP, 0), 441 vf ? "VF" : ""); 442 else 443 dev_err(kfd_device, "%s %s not supported in kfd\n", 444 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 445 return NULL; 446 } 447 448 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 449 if (!kfd) 450 return NULL; 451 452 kfd->adev = adev; 453 kfd_device_info_init(kfd, vf, gfx_target_version); 454 kfd->init_complete = false; 455 kfd->kfd2kgd = f2g; 456 atomic_set(&kfd->compute_profile, 0); 457 458 mutex_init(&kfd->doorbell_mutex); 459 460 ida_init(&kfd->doorbell_ida); 461 462 return kfd; 463} 464 465static void kfd_cwsr_init(struct kfd_dev *kfd) 466{ 467 if (cwsr_enable && kfd->device_info.supports_cwsr) { 468 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 469 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 470 > KFD_CWSR_TMA_OFFSET); 471 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 472 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 473 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 474 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 475 > KFD_CWSR_TMA_OFFSET); 476 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 477 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 478 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 479 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 480 > KFD_CWSR_TMA_OFFSET); 481 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 482 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 483 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) { 484 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 485 > KFD_CWSR_TMA_OFFSET); 486 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 487 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 488 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 489 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 490 > KFD_CWSR_TMA_OFFSET); 491 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 492 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 493 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 494 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 495 > KFD_CWSR_TMA_OFFSET); 496 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 497 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 498 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 499 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 500 > KFD_CWSR_TMA_OFFSET); 501 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 502 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 503 } else { 504 /* The gfx11 cwsr trap handler must fit inside a single 505 page. */ 506 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 507 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 508 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 509 } 510 511 kfd->cwsr_enabled = true; 512 } 513} 514 515static int kfd_gws_init(struct kfd_node *node) 516{ 517 int ret = 0; 518 struct kfd_dev *kfd = node->kfd; 519 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 520 521 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 522 return 0; 523 524 if (hws_gws_support || (KFD_IS_SOC15(node) && 525 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 526 && kfd->mec2_fw_version >= 0x81b3) || 527 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 528 && kfd->mec2_fw_version >= 0x1b3) || 529 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 530 && kfd->mec2_fw_version >= 0x30) || 531 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 532 && kfd->mec2_fw_version >= 0x28) || 533 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) || 534 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 535 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 536 && kfd->mec2_fw_version >= 0x6b) || 537 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 538 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 539 && mes_rev >= 68)))) 540 ret = amdgpu_amdkfd_alloc_gws(node->adev, 541 node->adev->gds.gws_size, &node->gws); 542 543 return ret; 544} 545 546static void kfd_smi_init(struct kfd_node *dev) 547{ 548 INIT_LIST_HEAD(&dev->smi_clients); 549 spin_lock_init(&dev->smi_lock); 550} 551 552static int kfd_init_node(struct kfd_node *node) 553{ 554 int err = -1; 555 556 if (kfd_interrupt_init(node)) { 557 dev_err(kfd_device, "Error initializing interrupts\n"); 558 goto kfd_interrupt_error; 559 } 560 561 node->dqm = device_queue_manager_init(node); 562 if (!node->dqm) { 563 dev_err(kfd_device, "Error initializing queue manager\n"); 564 goto device_queue_manager_error; 565 } 566 567 if (kfd_gws_init(node)) { 568 dev_err(kfd_device, "Could not allocate %d gws\n", 569 node->adev->gds.gws_size); 570 goto gws_error; 571 } 572 573 if (kfd_resume(node)) 574 goto kfd_resume_error; 575 576 if (kfd_topology_add_device(node)) { 577 dev_err(kfd_device, "Error adding device to topology\n"); 578 goto kfd_topology_add_device_error; 579 } 580 581 kfd_smi_init(node); 582 583 return 0; 584 585kfd_topology_add_device_error: 586kfd_resume_error: 587gws_error: 588 device_queue_manager_uninit(node->dqm); 589device_queue_manager_error: 590 kfd_interrupt_exit(node); 591kfd_interrupt_error: 592 if (node->gws) 593 amdgpu_amdkfd_free_gws(node->adev, node->gws); 594 595 /* Cleanup the node memory here */ 596 kfree(node); 597 return err; 598} 599 600static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 601{ 602 struct kfd_node *knode; 603 unsigned int i; 604 605 for (i = 0; i < num_nodes; i++) { 606 knode = kfd->nodes[i]; 607 device_queue_manager_uninit(knode->dqm); 608 kfd_interrupt_exit(knode); 609 kfd_topology_remove_device(knode); 610 if (knode->gws) 611 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 612 kfree(knode); 613 kfd->nodes[i] = NULL; 614 } 615} 616 617static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 618 unsigned int kfd_node_idx) 619{ 620 struct amdgpu_device *adev = node->adev; 621 uint32_t xcc_mask = node->xcc_mask; 622 uint32_t xcc, mapped_xcc; 623 /* 624 * Interrupt bitmap is setup for processing interrupts from 625 * different XCDs and AIDs. 626 * Interrupt bitmap is defined as follows: 627 * 1. Bits 0-15 - correspond to the NodeId field. 628 * Each bit corresponds to NodeId number. For example, if 629 * a KFD node has interrupt bitmap set to 0x7, then this 630 * KFD node will process interrupts with NodeId = 0, 1 and 2 631 * in the IH cookie. 632 * 2. Bits 16-31 - unused. 633 * 634 * Please note that the kfd_node_idx argument passed to this 635 * function is not related to NodeId field received in the 636 * IH cookie. 637 * 638 * In CPX mode, a KFD node will process an interrupt if: 639 * - the Node Id matches the corresponding bit set in 640 * Bits 0-15. 641 * - AND VMID reported in the interrupt lies within the 642 * VMID range of the node. 643 */ 644 for_each_inst(xcc, xcc_mask) { 645 mapped_xcc = GET_INST(GC, xcc); 646 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 647 } 648 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 649 node->interrupt_bitmap); 650} 651 652bool kgd2kfd_device_init(struct kfd_dev *kfd, 653 const struct kgd2kfd_shared_resources *gpu_resources) 654{ 655 unsigned int size, map_process_packet_size, i; 656 struct kfd_node *node; 657 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 658 unsigned int max_proc_per_quantum; 659 int partition_mode; 660 int xcp_idx; 661 662 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 663 KGD_ENGINE_MEC1); 664 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 665 KGD_ENGINE_MEC2); 666 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 667 KGD_ENGINE_SDMA1); 668 kfd->shared_resources = *gpu_resources; 669 670 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 671 672 if (kfd->num_nodes == 0) { 673 dev_err(kfd_device, 674 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 675 kfd->adev->gfx.num_xcc_per_xcp); 676 goto out; 677 } 678 679 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 680 * 32 and 64-bit requests are possible and must be 681 * supported. 682 */ 683 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 684 if (!kfd->pci_atomic_requested && 685 kfd->device_info.needs_pci_atomics && 686 (!kfd->device_info.no_atomic_fw_version || 687 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 688 dev_info(kfd_device, 689 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 690 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 691 kfd->mec_fw_version, 692 kfd->device_info.no_atomic_fw_version); 693 return false; 694 } 695 696 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 697 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 698 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 699 700 /* For GFX9.4.3, we need special handling for VMIDs depending on 701 * partition mode. 702 * In CPX mode, the VMID range needs to be shared between XCDs. 703 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 704 * divide them equally, we change starting VMID to 4 and not use 705 * VMID 3. 706 * If the VMID range changes for GFX9.4.3, then this code MUST be 707 * revisited. 708 */ 709 if (kfd->adev->xcp_mgr) { 710 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 711 AMDGPU_XCP_FL_LOCKED); 712 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 713 kfd->num_nodes != 1) { 714 vmid_num_kfd /= 2; 715 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 716 } 717 } 718 719 /* Verify module parameters regarding mapped process number*/ 720 if (hws_max_conc_proc >= 0) 721 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 722 else 723 max_proc_per_quantum = vmid_num_kfd; 724 725 /* calculate max size of mqds needed for queues */ 726 size = max_num_of_queues_per_device * 727 kfd->device_info.mqd_size_aligned; 728 729 /* 730 * calculate max size of runlist packet. 731 * There can be only 2 packets at once 732 */ 733 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 734 sizeof(struct pm4_mes_map_process_aldebaran) : 735 sizeof(struct pm4_mes_map_process); 736 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 737 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 738 + sizeof(struct pm4_mes_runlist)) * 2; 739 740 /* Add size of HIQ & DIQ */ 741 size += KFD_KERNEL_QUEUE_SIZE * 2; 742 743 /* add another 512KB for all other allocations on gart (HPD, fences) */ 744 size += 512 * 1024; 745 746 if (amdgpu_amdkfd_alloc_gtt_mem( 747 kfd->adev, size, &kfd->gtt_mem, 748 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 749 false)) { 750 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 751 goto alloc_gtt_mem_failure; 752 } 753 754 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 755 756 /* Initialize GTT sa with 512 byte chunk size */ 757 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 758 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 759 goto kfd_gtt_sa_init_error; 760 } 761 762 if (kfd_doorbell_init(kfd)) { 763 dev_err(kfd_device, 764 "Error initializing doorbell aperture\n"); 765 goto kfd_doorbell_error; 766 } 767 768 if (amdgpu_use_xgmi_p2p) 769 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 770 771 /* 772 * For GFX9.4.3, the KFD abstracts all partitions within a socket as 773 * xGMI connected in the topology so assign a unique hive id per 774 * device based on the pci device location if device is in PCIe mode. 775 */ 776 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1) 777 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 778 779 kfd->noretry = kfd->adev->gmc.noretry; 780 781 kfd_cwsr_init(kfd); 782 783 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 784 kfd->num_nodes); 785 786 /* Allocate the KFD nodes */ 787 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 788 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 789 if (!node) 790 goto node_alloc_error; 791 792 node->node_id = i; 793 node->adev = kfd->adev; 794 node->kfd = kfd; 795 node->kfd2kgd = kfd->kfd2kgd; 796 node->vm_info.vmid_num_kfd = vmid_num_kfd; 797 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 798 /* TODO : Check if error handling is needed */ 799 if (node->xcp) { 800 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 801 &node->xcc_mask); 802 ++xcp_idx; 803 } else { 804 node->xcc_mask = 805 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 806 } 807 808 if (node->xcp) { 809 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 810 node->node_id, node->xcp->mem_id, 811 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 812 } 813 814 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) && 815 partition_mode == AMDGPU_CPX_PARTITION_MODE && 816 kfd->num_nodes != 1) { 817 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range 818 * 4-9 and second XCD gets VMID range 10-15. 819 */ 820 821 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 822 first_vmid_kfd : 823 first_vmid_kfd+vmid_num_kfd; 824 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 825 last_vmid_kfd-vmid_num_kfd : 826 last_vmid_kfd; 827 node->compute_vmid_bitmap = 828 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 829 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 830 } else { 831 node->vm_info.first_vmid_kfd = first_vmid_kfd; 832 node->vm_info.last_vmid_kfd = last_vmid_kfd; 833 node->compute_vmid_bitmap = 834 gpu_resources->compute_vmid_bitmap; 835 } 836 node->max_proc_per_quantum = max_proc_per_quantum; 837 atomic_set(&node->sram_ecc_flag, 0); 838 839 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 840 &node->local_mem_info, node->xcp); 841 842 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) 843 kfd_setup_interrupt_bitmap(node, i); 844 845 /* Initialize the KFD node */ 846 if (kfd_init_node(node)) { 847 dev_err(kfd_device, "Error initializing KFD node\n"); 848 goto node_init_error; 849 } 850 kfd->nodes[i] = node; 851 } 852 853 svm_range_set_max_pages(kfd->adev); 854 855 spin_lock_init(&kfd->watch_points_lock); 856 857 kfd->init_complete = true; 858 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 859 kfd->adev->pdev->device); 860 861 pr_debug("Starting kfd with the following scheduling policy %d\n", 862 node->dqm->sched_policy); 863 864 goto out; 865 866node_init_error: 867node_alloc_error: 868 kfd_cleanup_nodes(kfd, i); 869 kfd_doorbell_fini(kfd); 870kfd_doorbell_error: 871 kfd_gtt_sa_fini(kfd); 872kfd_gtt_sa_init_error: 873 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 874alloc_gtt_mem_failure: 875 dev_err(kfd_device, 876 "device %x:%x NOT added due to errors\n", 877 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 878out: 879 return kfd->init_complete; 880} 881 882void kgd2kfd_device_exit(struct kfd_dev *kfd) 883{ 884 if (kfd->init_complete) { 885 /* Cleanup KFD nodes */ 886 kfd_cleanup_nodes(kfd, kfd->num_nodes); 887 /* Cleanup common/shared resources */ 888 kfd_doorbell_fini(kfd); 889 ida_destroy(&kfd->doorbell_ida); 890 kfd_gtt_sa_fini(kfd); 891 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem); 892 } 893 894 kfree(kfd); 895} 896 897int kgd2kfd_pre_reset(struct kfd_dev *kfd) 898{ 899 struct kfd_node *node; 900 int i; 901 902 if (!kfd->init_complete) 903 return 0; 904 905 for (i = 0; i < kfd->num_nodes; i++) { 906 node = kfd->nodes[i]; 907 kfd_smi_event_update_gpu_reset(node, false); 908 node->dqm->ops.pre_reset(node->dqm); 909 } 910 911 kgd2kfd_suspend(kfd, false); 912 913 for (i = 0; i < kfd->num_nodes; i++) 914 kfd_signal_reset_event(kfd->nodes[i]); 915 916 return 0; 917} 918 919/* 920 * Fix me. KFD won't be able to resume existing process for now. 921 * We will keep all existing process in a evicted state and 922 * wait the process to be terminated. 923 */ 924 925int kgd2kfd_post_reset(struct kfd_dev *kfd) 926{ 927 int ret; 928 struct kfd_node *node; 929 int i; 930 931 if (!kfd->init_complete) 932 return 0; 933 934 for (i = 0; i < kfd->num_nodes; i++) { 935 ret = kfd_resume(kfd->nodes[i]); 936 if (ret) 937 return ret; 938 } 939 940 mutex_lock(&kfd_processes_mutex); 941 --kfd_locked; 942 mutex_unlock(&kfd_processes_mutex); 943 944 for (i = 0; i < kfd->num_nodes; i++) { 945 node = kfd->nodes[i]; 946 atomic_set(&node->sram_ecc_flag, 0); 947 kfd_smi_event_update_gpu_reset(node, true); 948 } 949 950 return 0; 951} 952 953bool kfd_is_locked(void) 954{ 955 lockdep_assert_held(&kfd_processes_mutex); 956 return (kfd_locked > 0); 957} 958 959void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 960{ 961 struct kfd_node *node; 962 int i; 963 964 if (!kfd->init_complete) 965 return; 966 967 /* for runtime suspend, skip locking kfd */ 968 if (!run_pm) { 969 mutex_lock(&kfd_processes_mutex); 970 /* For first KFD device suspend all the KFD processes */ 971 if (++kfd_locked == 1) 972 kfd_suspend_all_processes(); 973 mutex_unlock(&kfd_processes_mutex); 974 } 975 976 for (i = 0; i < kfd->num_nodes; i++) { 977 node = kfd->nodes[i]; 978 node->dqm->ops.stop(node->dqm); 979 } 980} 981 982int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 983{ 984 int ret, i; 985 986 if (!kfd->init_complete) 987 return 0; 988 989 for (i = 0; i < kfd->num_nodes; i++) { 990 ret = kfd_resume(kfd->nodes[i]); 991 if (ret) 992 return ret; 993 } 994 995 /* for runtime resume, skip unlocking kfd */ 996 if (!run_pm) { 997 mutex_lock(&kfd_processes_mutex); 998 if (--kfd_locked == 0) 999 ret = kfd_resume_all_processes(); 1000 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1001 mutex_unlock(&kfd_processes_mutex); 1002 } 1003 1004 return ret; 1005} 1006 1007static int kfd_resume(struct kfd_node *node) 1008{ 1009 int err = 0; 1010 1011 err = node->dqm->ops.start(node->dqm); 1012 if (err) 1013 dev_err(kfd_device, 1014 "Error starting queue manager for device %x:%x\n", 1015 node->adev->pdev->vendor, node->adev->pdev->device); 1016 1017 return err; 1018} 1019 1020static inline void kfd_queue_work(struct workqueue_struct *wq, 1021 struct work_struct *work) 1022{ 1023 int cpu, new_cpu; 1024 1025 cpu = new_cpu = smp_processor_id(); 1026 do { 1027 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; 1028 if (cpu_to_node(new_cpu) == numa_node_id()) 1029 break; 1030 } while (cpu != new_cpu); 1031 1032 queue_work_on(new_cpu, wq, work); 1033} 1034 1035/* This is called directly from KGD at ISR. */ 1036void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1037{ 1038 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1039 bool is_patched = false; 1040 unsigned long flags; 1041 struct kfd_node *node; 1042 1043 if (!kfd->init_complete) 1044 return; 1045 1046 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1047 dev_err_once(kfd_device, "Ring entry too small\n"); 1048 return; 1049 } 1050 1051 for (i = 0; i < kfd->num_nodes; i++) { 1052 node = kfd->nodes[i]; 1053 spin_lock_irqsave(&node->interrupt_lock, flags); 1054 1055 if (node->interrupts_active 1056 && interrupt_is_wanted(node, ih_ring_entry, 1057 patched_ihre, &is_patched) 1058 && enqueue_ih_ring_entry(node, 1059 is_patched ? patched_ihre : ih_ring_entry)) { 1060 kfd_queue_work(node->ih_wq, &node->interrupt_work); 1061 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1062 return; 1063 } 1064 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1065 } 1066 1067} 1068 1069int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1070{ 1071 struct kfd_process *p; 1072 int r; 1073 1074 /* Because we are called from arbitrary context (workqueue) as opposed 1075 * to process context, kfd_process could attempt to exit while we are 1076 * running so the lookup function increments the process ref count. 1077 */ 1078 p = kfd_lookup_process_by_mm(mm); 1079 if (!p) 1080 return -ESRCH; 1081 1082 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1083 r = kfd_process_evict_queues(p, trigger); 1084 1085 kfd_unref_process(p); 1086 return r; 1087} 1088 1089int kgd2kfd_resume_mm(struct mm_struct *mm) 1090{ 1091 struct kfd_process *p; 1092 int r; 1093 1094 /* Because we are called from arbitrary context (workqueue) as opposed 1095 * to process context, kfd_process could attempt to exit while we are 1096 * running so the lookup function increments the process ref count. 1097 */ 1098 p = kfd_lookup_process_by_mm(mm); 1099 if (!p) 1100 return -ESRCH; 1101 1102 r = kfd_process_restore_queues(p); 1103 1104 kfd_unref_process(p); 1105 return r; 1106} 1107 1108/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1109 * prepare for safe eviction of KFD BOs that belong to the specified 1110 * process. 1111 * 1112 * @mm: mm_struct that identifies the specified KFD process 1113 * @fence: eviction fence attached to KFD process BOs 1114 * 1115 */ 1116int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1117 struct dma_fence *fence) 1118{ 1119 struct kfd_process *p; 1120 unsigned long active_time; 1121 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1122 1123 if (!fence) 1124 return -EINVAL; 1125 1126 if (dma_fence_is_signaled(fence)) 1127 return 0; 1128 1129 p = kfd_lookup_process_by_mm(mm); 1130 if (!p) 1131 return -ENODEV; 1132 1133 if (fence->seqno == p->last_eviction_seqno) 1134 goto out; 1135 1136 p->last_eviction_seqno = fence->seqno; 1137 1138 /* Avoid KFD process starvation. Wait for at least 1139 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1140 */ 1141 active_time = get_jiffies_64() - p->last_restore_timestamp; 1142 if (delay_jiffies > active_time) 1143 delay_jiffies -= active_time; 1144 else 1145 delay_jiffies = 0; 1146 1147 /* During process initialization eviction_work.dwork is initialized 1148 * to kfd_evict_bo_worker 1149 */ 1150 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1151 p->lead_thread->pid, delay_jiffies); 1152 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1153out: 1154 kfd_unref_process(p); 1155 return 0; 1156} 1157 1158static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1159 unsigned int chunk_size) 1160{ 1161 if (WARN_ON(buf_size < chunk_size)) 1162 return -EINVAL; 1163 if (WARN_ON(buf_size == 0)) 1164 return -EINVAL; 1165 if (WARN_ON(chunk_size == 0)) 1166 return -EINVAL; 1167 1168 kfd->gtt_sa_chunk_size = chunk_size; 1169 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1170 1171 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1172 GFP_KERNEL); 1173 if (!kfd->gtt_sa_bitmap) 1174 return -ENOMEM; 1175 1176 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1177 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1178 1179 mutex_init(&kfd->gtt_sa_lock); 1180 1181 return 0; 1182} 1183 1184static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1185{ 1186 mutex_destroy(&kfd->gtt_sa_lock); 1187 bitmap_free(kfd->gtt_sa_bitmap); 1188} 1189 1190static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1191 unsigned int bit_num, 1192 unsigned int chunk_size) 1193{ 1194 return start_addr + bit_num * chunk_size; 1195} 1196 1197static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1198 unsigned int bit_num, 1199 unsigned int chunk_size) 1200{ 1201 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1202} 1203 1204int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1205 struct kfd_mem_obj **mem_obj) 1206{ 1207 unsigned int found, start_search, cur_size; 1208 struct kfd_dev *kfd = node->kfd; 1209 1210 if (size == 0) 1211 return -EINVAL; 1212 1213 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1214 return -ENOMEM; 1215 1216 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1217 if (!(*mem_obj)) 1218 return -ENOMEM; 1219 1220 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1221 1222 start_search = 0; 1223 1224 mutex_lock(&kfd->gtt_sa_lock); 1225 1226kfd_gtt_restart_search: 1227 /* Find the first chunk that is free */ 1228 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1229 kfd->gtt_sa_num_of_chunks, 1230 start_search); 1231 1232 pr_debug("Found = %d\n", found); 1233 1234 /* If there wasn't any free chunk, bail out */ 1235 if (found == kfd->gtt_sa_num_of_chunks) 1236 goto kfd_gtt_no_free_chunk; 1237 1238 /* Update fields of mem_obj */ 1239 (*mem_obj)->range_start = found; 1240 (*mem_obj)->range_end = found; 1241 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1242 kfd->gtt_start_gpu_addr, 1243 found, 1244 kfd->gtt_sa_chunk_size); 1245 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1246 kfd->gtt_start_cpu_ptr, 1247 found, 1248 kfd->gtt_sa_chunk_size); 1249 1250 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1251 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1252 1253 /* If we need only one chunk, mark it as allocated and get out */ 1254 if (size <= kfd->gtt_sa_chunk_size) { 1255 pr_debug("Single bit\n"); 1256 __set_bit(found, kfd->gtt_sa_bitmap); 1257 goto kfd_gtt_out; 1258 } 1259 1260 /* Otherwise, try to see if we have enough contiguous chunks */ 1261 cur_size = size - kfd->gtt_sa_chunk_size; 1262 do { 1263 (*mem_obj)->range_end = 1264 find_next_zero_bit(kfd->gtt_sa_bitmap, 1265 kfd->gtt_sa_num_of_chunks, ++found); 1266 /* 1267 * If next free chunk is not contiguous than we need to 1268 * restart our search from the last free chunk we found (which 1269 * wasn't contiguous to the previous ones 1270 */ 1271 if ((*mem_obj)->range_end != found) { 1272 start_search = found; 1273 goto kfd_gtt_restart_search; 1274 } 1275 1276 /* 1277 * If we reached end of buffer, bail out with error 1278 */ 1279 if (found == kfd->gtt_sa_num_of_chunks) 1280 goto kfd_gtt_no_free_chunk; 1281 1282 /* Check if we don't need another chunk */ 1283 if (cur_size <= kfd->gtt_sa_chunk_size) 1284 cur_size = 0; 1285 else 1286 cur_size -= kfd->gtt_sa_chunk_size; 1287 1288 } while (cur_size > 0); 1289 1290 pr_debug("range_start = %d, range_end = %d\n", 1291 (*mem_obj)->range_start, (*mem_obj)->range_end); 1292 1293 /* Mark the chunks as allocated */ 1294 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1295 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1296 1297kfd_gtt_out: 1298 mutex_unlock(&kfd->gtt_sa_lock); 1299 return 0; 1300 1301kfd_gtt_no_free_chunk: 1302 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1303 mutex_unlock(&kfd->gtt_sa_lock); 1304 kfree(*mem_obj); 1305 return -ENOMEM; 1306} 1307 1308int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1309{ 1310 struct kfd_dev *kfd = node->kfd; 1311 1312 /* Act like kfree when trying to free a NULL object */ 1313 if (!mem_obj) 1314 return 0; 1315 1316 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1317 mem_obj, mem_obj->range_start, mem_obj->range_end); 1318 1319 mutex_lock(&kfd->gtt_sa_lock); 1320 1321 /* Mark the chunks as free */ 1322 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1323 mem_obj->range_end - mem_obj->range_start + 1); 1324 1325 mutex_unlock(&kfd->gtt_sa_lock); 1326 1327 kfree(mem_obj); 1328 return 0; 1329} 1330 1331void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1332{ 1333 /* 1334 * TODO: Currently update SRAM ECC flag for first node. 1335 * This needs to be updated later when we can 1336 * identify SRAM ECC error on other nodes also. 1337 */ 1338 if (kfd) 1339 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1340} 1341 1342void kfd_inc_compute_active(struct kfd_node *node) 1343{ 1344 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1345 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1346} 1347 1348void kfd_dec_compute_active(struct kfd_node *node) 1349{ 1350 int count = atomic_dec_return(&node->kfd->compute_profile); 1351 1352 if (count == 0) 1353 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1354 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1355} 1356 1357void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1358{ 1359 /* 1360 * TODO: For now, raise the throttling event only on first node. 1361 * This will need to change after we are able to determine 1362 * which node raised the throttling event. 1363 */ 1364 if (kfd && kfd->init_complete) 1365 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1366 throttle_bitmask); 1367} 1368 1369/* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1370 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1371 * When the device has more than two engines, we reserve two for PCIe to enable 1372 * full-duplex and the rest are used as XGMI. 1373 */ 1374unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1375{ 1376 /* If XGMI is not supported, all SDMA engines are PCIe */ 1377 if (!node->adev->gmc.xgmi.supported) 1378 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1379 1380 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1381} 1382 1383unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1384{ 1385 /* After reserved for PCIe, the rest of engines are XGMI */ 1386 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1387 kfd_get_num_sdma_engines(node); 1388} 1389 1390int kgd2kfd_check_and_lock_kfd(void) 1391{ 1392 mutex_lock(&kfd_processes_mutex); 1393 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) { 1394 mutex_unlock(&kfd_processes_mutex); 1395 return -EBUSY; 1396 } 1397 1398 ++kfd_locked; 1399 mutex_unlock(&kfd_processes_mutex); 1400 1401 return 0; 1402} 1403 1404void kgd2kfd_unlock_kfd(void) 1405{ 1406 mutex_lock(&kfd_processes_mutex); 1407 --kfd_locked; 1408 mutex_unlock(&kfd_processes_mutex); 1409} 1410 1411#if defined(CONFIG_DEBUG_FS) 1412 1413/* This function will send a package to HIQ to hang the HWS 1414 * which will trigger a GPU reset and bring the HWS back to normal state 1415 */ 1416int kfd_debugfs_hang_hws(struct kfd_node *dev) 1417{ 1418 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1419 pr_err("HWS is not enabled"); 1420 return -EINVAL; 1421 } 1422 1423 return dqm_debugfs_hang_hws(dev->dqm); 1424} 1425 1426#endif 1427