/linux-master/drivers/gpu/drm/radeon/ |
H A D | si_dpm.c | 4735 u32 fbdiv; local 4747 fbdiv = (u32) tmp; 4757 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4767 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
|
H A D | rv770_dpm.c | 504 u32 fbdiv; local 521 fbdiv = (u32) tmp; 536 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 546 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
|
H A D | ni_dpm.c | 2014 u32 fbdiv; local 2027 fbdiv = (u32) tmp; 2037 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 2047 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
|
H A D | ci_dpm.c | 3127 u32 fbdiv; local 3137 fbdiv = dividers.fb_div & 0x3FFFFFF; 3140 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 3150 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
|
H A D | rv740_dpm.c | 132 u32 fbdiv; local 144 fbdiv = (u32) tmp; 154 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 164 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
|
/linux-master/drivers/clk/rockchip/ |
H A D | clk.h | 296 .fbdiv = _fbdiv, \ 359 unsigned int fbdiv; member in struct:rockchip_pll_rate_table::__anon365::__anon367
|
/linux-master/sound/soc/codecs/ |
H A D | madera.c | 4423 int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; local 4447 fbdiv = 256; 4449 fbdiv = 4; 4453 fbdiv = 1; 4457 fbdiv = 1; 4482 while (ratio / fbdiv < min_n) { 4483 fbdiv /= 2; 4484 if (fbdiv < 1) { 4485 madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv); 4489 while (frac && (ratio / fbdiv > max_ [all...] |
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/ |
H A D | si_dpm.c | 5281 u32 fbdiv; local 5293 fbdiv = (u32) tmp; 5303 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 5313 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
|
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | iceland_smumgr.c | 807 uint32_t fbdiv; local 822 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; 832 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); 851 /* clkv = 2 * D * fbdiv / NS */ 852 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
|
H A D | ci_smumgr.c | 309 uint32_t fbdiv; local 324 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; 334 SPLL_FB_DIV, fbdiv); 350 fbdiv / (clk_s * 10000);
|
H A D | tonga_smumgr.c | 550 uint32_t fbdiv; local 565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; 575 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); 594 /* clkv = 2 * D * fbdiv / NS */ 595 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
|
H A D | fiji_smumgr.c | 867 uint32_t fbdiv; local 882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; 892 SPLL_FB_DIV, fbdiv); 913 /* clkv = 2 * D * fbdiv / NS */ 915 fbdiv / (clk_s * 10000);
|
/linux-master/drivers/clk/ |
H A D | clk-sp7021.c | 405 u32 fbdiv; local 408 fbdiv = DIV_ROUND_CLOSEST(rate, clk->brate); 409 if (fbdiv > max) 410 fbdiv = max; 412 return fbdiv; 473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1; local 475 ret = clk->brate * fbdiv; 497 u32 fbdiv = sp_pll_calc_div(clk, rate); local 501 reg |= ((fbdiv - 1) << clk->div_shift) & mask;
|
H A D | clk-hsdk-pll.c | 49 u32 fbdiv; member in struct:hsdk_pll_cfg 142 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; 172 u32 idiv, fbdiv, odiv; local 189 /* fb divider = 2*(reg.fbdiv + 1) */ 190 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); 194 rate = (u64)parent_rate * fbdiv;
|
H A D | clk-bm1880.c | 477 u32 fbdiv, refdiv; local 480 fbdiv = (regval >> 16) & 0xfff; 485 numerator = parent_rate * fbdiv;
|
H A D | clk-axm5516.c | 52 unsigned long rate, fbdiv, refdiv, postdiv; local 57 fbdiv = ((control >> 4) & 0xfff) + 3; 59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
|
/linux-master/arch/arm/common/ |
H A D | sa1111.c | 1180 unsigned int skcdr, fbdiv, ipdiv, opdiv; local 1184 fbdiv = (skcdr & 0x007f) + 2; 1188 return 3686400 * fbdiv / (ipdiv * opdiv);
|
/linux-master/drivers/clk/analogbits/ |
H A D | wrpll-cln28hpc.c | 232 u8 fbdiv, divq, best_r, r; local 268 fbdiv = __wrpll_calc_fbdiv(c); 280 f >>= (fbdiv - 1); 283 vco_pre = fbdiv * post_divr_freq; 339 u8 fbdiv; local 347 fbdiv = __wrpll_calc_fbdiv(c); 348 n = parent_rate * fbdiv * (c->divf + 1);
|
/linux-master/drivers/phy/rockchip/ |
H A D | phy-rockchip-inno-hdmi.c | 254 u16 fbdiv; member in struct:pre_pll_config 269 u16 fbdiv; member in struct:post_pll_config 797 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | 800 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); 958 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); 959 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); 1073 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); 1074 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); 1181 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); 1183 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | [all...] |
H A D | phy-rockchip-inno-dsidphy.c | 221 u16 fbdiv; member in struct:inno_dsidphy::__anon40 359 inno->pll.fbdiv = best_fbdiv; 387 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); 389 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 530 u16 fbdiv = 28; local 545 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); 547 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
|
/linux-master/drivers/clk/xilinx/ |
H A D | xlnx_vcu.c | 82 * @fbdiv: The integer portion of the feedback divider to the PLL 90 u32 fbdiv; member in struct:xvcu_pll_cfg 279 if (xvcu_pll_cfg[i].fbdiv == div) 298 vcu_pll_ctrl |= FIELD_PREP(VCU_PLL_CTRL_FBDIV, cfg->fbdiv);
|
/linux-master/drivers/clk/starfive/ |
H A D | clk-starfive-jh7110-pll.c | 15 * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0]. 83 unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ member in struct:jh7110_pll_preset 95 unsigned int fbdiv; member in struct:jh7110_pll_info::__anon200 102 u32 fbdiv; member in struct:jh7110_pll_info::__anon201 107 char fbdiv; member in struct:jh7110_pll_info::__anon202 118 .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \ 125 .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \ 130 .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \ 149 u32 fbdiv; member in struct:jh7110_pll_regvals [all...] |
/linux-master/drivers/clk/ralink/ |
H A D | clk-mt7621.c | 262 u32 pll, prediv, fbdiv; local 278 fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll); 280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
|
/linux-master/drivers/clk/axs10x/ |
H A D | pll_clock.c | 69 u32 fbdiv; member in struct:axs10x_pll_cfg 139 u32 idiv, fbdiv, odiv; local 143 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV)); 146 rate = (u64)parent_rate * fbdiv; 185 axs10x_encode_div(pll_cfg[i].fbdiv, 0));
|
/linux-master/drivers/clk/zynqmp/ |
H A D | pll.c | 104 u32 fbdiv; local 117 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); 118 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { 119 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); 120 rate = *prate * fbdiv; 139 u32 fbdiv, data; local 145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); 156 rate = parent_rate * fbdiv; 183 u32 fbdiv; local [all...] |