clk/zynqmp/pll.c

104 	u32 fbdiv;
117 	fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
118 	if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) {
119 		fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
120 		rate = *prate * fbdiv;
139 	u32 fbdiv, data;
145 	ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
156 	rate =  parent_rate * fbdiv;
183 	u32 fbdiv;
209 	fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
210 	fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
211 	ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
216 	return parent_rate * fbdiv;