Searched refs:enable_bit (Results 1 - 25 of 58) sorted by last modified time

123

/linux-master/tools/testing/selftests/user_events/
H A Dftrace_test.c178 reg.enable_bit = 31;
243 reg.enable_bit = 31;
260 reg.enable_bit = 30;
265 reg.enable_bit = 29;
271 reg.enable_bit = 29;
283 ASSERT_EQ(1 << reg.enable_bit, self->check);
314 reg.enable_bit = 31;
350 ASSERT_NE(1 << reg.enable_bit, self->check);
371 reg.enable_bit = 31;
388 ASSERT_EQ(1 << reg.enable_bit, sel
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H A Dabi_test.c157 reg.enable_bit = bit;
180 reg.enable_bit = bit;
H A Ddyn_test.c62 reg.enable_bit = bit;
H A Dperf_test.c144 reg.enable_bit = 31;
174 ASSERT_EQ(1 << reg.enable_bit, self->check);
208 reg.enable_bit = 31;
236 ASSERT_EQ(1 << reg.enable_bit, self->check);
/linux-master/kernel/trace/
H A Dtrace_events_user.c902 enabler->values = reg->enable_bit;
2443 if (kreg->enable_bit > (kreg->enable_size * BITS_PER_BYTE) - 1)
2482 reg.enable_bit))
/linux-master/drivers/clk/renesas/
H A Dclk-sh73a0.c89 u32 enable_bit = name[3] - '0'; local
92 switch (enable_bit) {
108 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
111 if (enable_bit == 1 || enable_bit == 2)
/linux-master/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_mbox.c117 int enable_bit, int time_window)
143 data |= BIT(enable_bit);
145 data &= ~BIT(enable_bit);
116 processor_thermal_mbox_interrupt_config(struct pci_dev *pdev, bool enable, int enable_bit, int time_window) argument
H A Dprocessor_thermal_device.h108 int processor_thermal_mbox_interrupt_config(struct pci_dev *pdev, bool enable, int enable_bit,
/linux-master/drivers/spi/
H A Dspi-rspi.c459 u8 enable_bit)
467 rspi_enable_irq(rspi, enable_bit);
458 rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, u8 enable_bit) argument
/linux-master/drivers/perf/
H A Dxgene_pmu.c1463 int enable_bit; local
1501 enable_bit = 0;
1503 enable_bit = (int) obj->integer.value;
1505 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1513 inf->enable_mask = 1 << enable_bit;
1630 int enable_bit; local
1648 if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
1649 enable_bit = 0;
1651 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1660 inf->enable_mask = 1 << enable_bit;
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/linux-master/drivers/net/ethernet/broadcom/
H A Dtg3.c8889 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) argument
8912 val &= ~enable_bit;
8919 "ofs=%lx enable_bit=%x\n",
8920 ofs, enable_bit);
8926 if ((val & enable_bit) == 0)
8932 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8933 ofs, enable_bit);
/linux-master/drivers/tty/serial/
H A Dmsm_serial.c167 u32 enable_bit; member in struct:msm_dma
265 val &= ~dma->enable_bit;
330 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
332 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
382 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
384 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
459 val &= ~dma->enable_bit;
526 val |= dma->enable_bit;
560 val &= ~dma->enable_bit;
659 val |= dma->enable_bit;
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/linux-master/include/linux/clk/
H A Dti.h157 * @enable_reg: register to write to enable the clock (see @enable_bit)
158 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
172 u8 enable_bit; member in struct:clk_hw_omap
/linux-master/drivers/clk/ti/
H A Dgate.c108 clk_hw->enable_bit = bit_idx;
134 u8 enable_bit = 0; local
142 enable_bit = reg.bit;
160 enable_bit, clk_gate_flags, ops, hw_ops);
179 gate->enable_bit = gate->enable_reg.bit;
H A Dinterface.c44 clk_hw->enable_bit = bit_idx;
67 u8 enable_bit = 0; local
73 enable_bit = reg.bit;
83 enable_bit, ops);
H A Dapll.c379 clk_hw->enable_bit = ti_clk_get_legacy_bit_shift(node);
380 ad->enable_mask = 0x3 << clk_hw->enable_bit;
381 ad->autoidle_mask = 0x3 << clk_hw->enable_bit;
H A Dclkctrl.c148 if (!clk->enable_bit)
154 val |= clk->enable_bit;
178 if (!clk->enable_bit)
211 if (val & clk->enable_bit)
344 clk_hw->enable_bit = data->bit;
663 hw->enable_bit = MODULEMODE_SWCTRL;
665 hw->enable_bit = MODULEMODE_HWCTRL;
/linux-master/include/uapi/linux/
H A Duser_events.h44 __u8 enable_bit; member in struct:user_reg
/linux-master/drivers/xen/xen-pciback/
H A Dconf_space_capability.c193 u16 enable_bit; /* bit for enabling MSI/MSI-X */ member in struct:msi_msix_field_config
197 .enable_bit = PCI_MSI_FLAGS_ENABLE,
201 .enable_bit = PCI_MSIX_FLAGS_ENABLE,
238 if (new_value & field_config->enable_bit) {
/linux-master/drivers/regulator/
H A Dmc13xxx.h16 int enable_bit; member in struct:mc13xxx_regulator
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c345 u32 enable_bit; member in struct:usb3phy_reg
564 u32 val = en << reg->enable_bit;
899 if (!(val & BIT(reg->enable_bit))) {
/linux-master/drivers/clk/spear/
H A Dspear1340_clock.c344 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
H A Dspear1310_clock.c305 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
/linux-master/drivers/clk/ingenic/
H A Dcgu.c239 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))
257 if (pll_info->enable_bit < 0)
271 ctl |= BIT(pll_info->enable_bit);
290 if (pll_info->enable_bit < 0)
296 ctl &= ~BIT(pll_info->enable_bit);
310 if (pll_info->enable_bit < 0)
315 return !!(ctl & BIT(pll_info->enable_bit));
/linux-master/drivers/clk/
H A Dclk-max9485.c73 u8 enable_bit; member in struct:max9485_clk_hw
115 clk_hw->enable_bit,
116 clk_hw->enable_bit);
123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
206 u8 enable_bit; member in struct:max9485_clk
213 .enable_bit = MAX9485_MCLK_ENABLE,
231 .enable_bit = MAX9485_CLKOUT1_ENABLE,
240 .enable_bit = MAX9485_CLKOUT2_ENABLE,
321 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
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