1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * arch/arm/mach-spear13xx/spear1310_clock.c 4 * 5 * SPEAr1310 machine clock framework source file 6 * 7 * Copyright (C) 2012 ST Microelectronics 8 * Viresh Kumar <vireshk@kernel.org> 9 */ 10 11#include <linux/clkdev.h> 12#include <linux/clk/spear.h> 13#include <linux/err.h> 14#include <linux/io.h> 15#include <linux/spinlock_types.h> 16#include "clk.h" 17 18/* PLL related registers and bit values */ 19#define SPEAR1310_PLL_CFG (misc_base + 0x210) 20 /* PLL_CFG bit values */ 21 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 22 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 23 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2 24 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29 25 #define SPEAR1310_RAS_SYNT_CLK_MASK 2 26 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27 27 #define SPEAR1310_PLL_CLK_MASK 2 28 #define SPEAR1310_PLL3_CLK_SHIFT 24 29 #define SPEAR1310_PLL2_CLK_SHIFT 22 30 #define SPEAR1310_PLL1_CLK_SHIFT 20 31 32#define SPEAR1310_PLL1_CTR (misc_base + 0x214) 33#define SPEAR1310_PLL1_FRQ (misc_base + 0x218) 34#define SPEAR1310_PLL2_CTR (misc_base + 0x220) 35#define SPEAR1310_PLL2_FRQ (misc_base + 0x224) 36#define SPEAR1310_PLL3_CTR (misc_base + 0x22C) 37#define SPEAR1310_PLL3_FRQ (misc_base + 0x230) 38#define SPEAR1310_PLL4_CTR (misc_base + 0x238) 39#define SPEAR1310_PLL4_FRQ (misc_base + 0x23C) 40#define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244) 41 /* PERIP_CLK_CFG bit values */ 42 #define SPEAR1310_GPT_OSC24_VAL 0 43 #define SPEAR1310_GPT_APB_VAL 1 44 #define SPEAR1310_GPT_CLK_MASK 1 45 #define SPEAR1310_GPT3_CLK_SHIFT 11 46 #define SPEAR1310_GPT2_CLK_SHIFT 10 47 #define SPEAR1310_GPT1_CLK_SHIFT 9 48 #define SPEAR1310_GPT0_CLK_SHIFT 8 49 #define SPEAR1310_UART_CLK_PLL5_VAL 0 50 #define SPEAR1310_UART_CLK_OSC24_VAL 1 51 #define SPEAR1310_UART_CLK_SYNT_VAL 2 52 #define SPEAR1310_UART_CLK_MASK 2 53 #define SPEAR1310_UART_CLK_SHIFT 4 54 55 #define SPEAR1310_AUX_CLK_PLL5_VAL 0 56 #define SPEAR1310_AUX_CLK_SYNT_VAL 1 57 #define SPEAR1310_CLCD_CLK_MASK 2 58 #define SPEAR1310_CLCD_CLK_SHIFT 2 59 #define SPEAR1310_C3_CLK_MASK 1 60 #define SPEAR1310_C3_CLK_SHIFT 1 61 62#define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248) 63 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 64 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 65 #define SPEAR1310_GMAC_PHY_CLK_MASK 1 66 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3 67 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 69 70#define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C) 71 /* I2S_CLK_CFG register mask */ 72 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F 73 #define SPEAR1310_I2S_SCLK_X_SHIFT 27 74 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F 75 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22 76 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21 77 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20 78 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF 79 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12 80 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF 81 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4 82 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3 83 #define SPEAR1310_I2S_REF_SEL_MASK 1 84 #define SPEAR1310_I2S_REF_SHIFT 2 85 #define SPEAR1310_I2S_SRC_CLK_MASK 2 86 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 87 88#define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250) 89#define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254) 90#define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258) 91#define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C) 92#define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260) 93#define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264) 94#define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268) 95#define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270) 96#define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280) 97#define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288) 98#define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290) 99#define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298) 100 /* Check Fractional synthesizer reg masks */ 101 102#define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300) 103 /* PERIP1_CLK_ENB register masks */ 104 #define SPEAR1310_RTC_CLK_ENB 31 105 #define SPEAR1310_ADC_CLK_ENB 30 106 #define SPEAR1310_C3_CLK_ENB 29 107 #define SPEAR1310_JPEG_CLK_ENB 28 108 #define SPEAR1310_CLCD_CLK_ENB 27 109 #define SPEAR1310_DMA_CLK_ENB 25 110 #define SPEAR1310_GPIO1_CLK_ENB 24 111 #define SPEAR1310_GPIO0_CLK_ENB 23 112 #define SPEAR1310_GPT1_CLK_ENB 22 113 #define SPEAR1310_GPT0_CLK_ENB 21 114 #define SPEAR1310_I2S0_CLK_ENB 20 115 #define SPEAR1310_I2S1_CLK_ENB 19 116 #define SPEAR1310_I2C0_CLK_ENB 18 117 #define SPEAR1310_SSP_CLK_ENB 17 118 #define SPEAR1310_UART_CLK_ENB 15 119 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14 120 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13 121 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12 122 #define SPEAR1310_UOC_CLK_ENB 11 123 #define SPEAR1310_UHC1_CLK_ENB 10 124 #define SPEAR1310_UHC0_CLK_ENB 9 125 #define SPEAR1310_GMAC_CLK_ENB 8 126 #define SPEAR1310_CFXD_CLK_ENB 7 127 #define SPEAR1310_SDHCI_CLK_ENB 6 128 #define SPEAR1310_SMI_CLK_ENB 5 129 #define SPEAR1310_FSMC_CLK_ENB 4 130 #define SPEAR1310_SYSRAM0_CLK_ENB 3 131 #define SPEAR1310_SYSRAM1_CLK_ENB 2 132 #define SPEAR1310_SYSROM_CLK_ENB 1 133 #define SPEAR1310_BUS_CLK_ENB 0 134 135#define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304) 136 /* PERIP2_CLK_ENB register masks */ 137 #define SPEAR1310_THSENS_CLK_ENB 8 138 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 139 #define SPEAR1310_ACP_CLK_ENB 6 140 #define SPEAR1310_GPT3_CLK_ENB 5 141 #define SPEAR1310_GPT2_CLK_ENB 4 142 #define SPEAR1310_KBD_CLK_ENB 3 143 #define SPEAR1310_CPU_DBG_CLK_ENB 2 144 #define SPEAR1310_DDR_CORE_CLK_ENB 1 145 #define SPEAR1310_DDR_CTRL_CLK_ENB 0 146 147#define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310) 148 /* RAS_CLK_ENB register masks */ 149 #define SPEAR1310_SYNT3_CLK_ENB 17 150 #define SPEAR1310_SYNT2_CLK_ENB 16 151 #define SPEAR1310_SYNT1_CLK_ENB 15 152 #define SPEAR1310_SYNT0_CLK_ENB 14 153 #define SPEAR1310_PCLK3_CLK_ENB 13 154 #define SPEAR1310_PCLK2_CLK_ENB 12 155 #define SPEAR1310_PCLK1_CLK_ENB 11 156 #define SPEAR1310_PCLK0_CLK_ENB 10 157 #define SPEAR1310_PLL3_CLK_ENB 9 158 #define SPEAR1310_PLL2_CLK_ENB 8 159 #define SPEAR1310_C125M_PAD_CLK_ENB 7 160 #define SPEAR1310_C30M_CLK_ENB 6 161 #define SPEAR1310_C48M_CLK_ENB 5 162 #define SPEAR1310_OSC_25M_CLK_ENB 4 163 #define SPEAR1310_OSC_32K_CLK_ENB 3 164 #define SPEAR1310_OSC_24M_CLK_ENB 2 165 #define SPEAR1310_PCLK_CLK_ENB 1 166 #define SPEAR1310_ACLK_CLK_ENB 0 167 168/* RAS Area Control Register */ 169#define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000) 170 #define SPEAR1310_SSP1_CLK_MASK 3 171 #define SPEAR1310_SSP1_CLK_SHIFT 26 172 #define SPEAR1310_TDM_CLK_MASK 1 173 #define SPEAR1310_TDM2_CLK_SHIFT 24 174 #define SPEAR1310_TDM1_CLK_SHIFT 23 175 #define SPEAR1310_I2C_CLK_MASK 1 176 #define SPEAR1310_I2C7_CLK_SHIFT 22 177 #define SPEAR1310_I2C6_CLK_SHIFT 21 178 #define SPEAR1310_I2C5_CLK_SHIFT 20 179 #define SPEAR1310_I2C4_CLK_SHIFT 19 180 #define SPEAR1310_I2C3_CLK_SHIFT 18 181 #define SPEAR1310_I2C2_CLK_SHIFT 17 182 #define SPEAR1310_I2C1_CLK_SHIFT 16 183 #define SPEAR1310_GPT64_CLK_MASK 1 184 #define SPEAR1310_GPT64_CLK_SHIFT 15 185 #define SPEAR1310_RAS_UART_CLK_MASK 1 186 #define SPEAR1310_UART5_CLK_SHIFT 14 187 #define SPEAR1310_UART4_CLK_SHIFT 13 188 #define SPEAR1310_UART3_CLK_SHIFT 12 189 #define SPEAR1310_UART2_CLK_SHIFT 11 190 #define SPEAR1310_UART1_CLK_SHIFT 10 191 #define SPEAR1310_PCI_CLK_MASK 1 192 #define SPEAR1310_PCI_CLK_SHIFT 0 193 194#define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004) 195 #define SPEAR1310_PHY_CLK_MASK 0x3 196 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 197 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 198 199#define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148) 200 #define SPEAR1310_CAN1_CLK_ENB 25 201 #define SPEAR1310_CAN0_CLK_ENB 24 202 #define SPEAR1310_GPT64_CLK_ENB 23 203 #define SPEAR1310_SSP1_CLK_ENB 22 204 #define SPEAR1310_I2C7_CLK_ENB 21 205 #define SPEAR1310_I2C6_CLK_ENB 20 206 #define SPEAR1310_I2C5_CLK_ENB 19 207 #define SPEAR1310_I2C4_CLK_ENB 18 208 #define SPEAR1310_I2C3_CLK_ENB 17 209 #define SPEAR1310_I2C2_CLK_ENB 16 210 #define SPEAR1310_I2C1_CLK_ENB 15 211 #define SPEAR1310_UART5_CLK_ENB 14 212 #define SPEAR1310_UART4_CLK_ENB 13 213 #define SPEAR1310_UART3_CLK_ENB 12 214 #define SPEAR1310_UART2_CLK_ENB 11 215 #define SPEAR1310_UART1_CLK_ENB 10 216 #define SPEAR1310_RS485_1_CLK_ENB 9 217 #define SPEAR1310_RS485_0_CLK_ENB 8 218 #define SPEAR1310_TDM2_CLK_ENB 7 219 #define SPEAR1310_TDM1_CLK_ENB 6 220 #define SPEAR1310_PCI_CLK_ENB 5 221 #define SPEAR1310_GMII_CLK_ENB 4 222 #define SPEAR1310_MII2_CLK_ENB 3 223 #define SPEAR1310_MII1_CLK_ENB 2 224 #define SPEAR1310_MII0_CLK_ENB 1 225 #define SPEAR1310_ESRAM_CLK_ENB 0 226 227static DEFINE_SPINLOCK(_lock); 228 229/* pll rate configuration table, in ascending order of rates */ 230static struct pll_rate_tbl pll_rtbl[] = { 231 /* PCLK 24MHz */ 232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ 233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ 234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ 235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ 237 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ 238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 239}; 240 241/* vco-pll4 rate configuration table, in ascending order of rates */ 242static struct pll_rate_tbl pll4_rtbl[] = { 243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ 244 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ 245 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ 246 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 247}; 248 249/* aux rate configuration table, in ascending order of rates */ 250static struct aux_rate_tbl aux_rtbl[] = { 251 /* For VCO1div2 = 500 MHz */ 252 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ 253 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ 254 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ 255 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ 256 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ 257 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ 258}; 259 260/* gmac rate configuration table, in ascending order of rates */ 261static struct aux_rate_tbl gmac_rtbl[] = { 262 /* For gmac phy input clk */ 263 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 264 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 265 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 266 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 267}; 268 269/* clcd rate configuration table, in ascending order of rates */ 270static struct frac_rate_tbl clcd_rtbl[] = { 271 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 272 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 273 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 274 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 275 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 276 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 277 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 278 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 279 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 280 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 281}; 282 283/* i2s prescaler1 masks */ 284static const struct aux_clk_masks i2s_prs1_masks = { 285 .eq_sel_mask = AUX_EQ_SEL_MASK, 286 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, 287 .eq1_mask = AUX_EQ1_SEL, 288 .eq2_mask = AUX_EQ2_SEL, 289 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK, 290 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT, 291 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK, 292 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT, 293}; 294 295/* i2s sclk (bit clock) syynthesizers masks */ 296static struct aux_clk_masks i2s_sclk_masks = { 297 .eq_sel_mask = AUX_EQ_SEL_MASK, 298 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT, 299 .eq1_mask = AUX_EQ1_SEL, 300 .eq2_mask = AUX_EQ2_SEL, 301 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK, 302 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT, 303 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK, 304 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT, 305 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB, 306}; 307 308/* i2s prs1 aux rate configuration table, in ascending order of rates */ 309static struct aux_rate_tbl i2s_prs1_rtbl[] = { 310 /* For parent clk = 49.152 MHz */ 311 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ 312 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ 313 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ 314 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ 315 316 /* 317 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz 318 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz 319 */ 320 {.xscale = 1, .yscale = 3, .eq = 0}, 321 322 /* For parent clk = 49.152 MHz */ 323 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ 324 325 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ 326}; 327 328/* i2s sclk aux rate configuration table, in ascending order of rates */ 329static struct aux_rate_tbl i2s_sclk_rtbl[] = { 330 /* For i2s_ref_clk = 12.288MHz */ 331 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */ 332 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */ 333}; 334 335/* adc rate configuration table, in ascending order of rates */ 336/* possible adc range is 2.5 MHz to 20 MHz. */ 337static struct aux_rate_tbl adc_rtbl[] = { 338 /* For ahb = 166.67 MHz */ 339 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 340 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 341 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 342 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 343}; 344 345/* General synth rate configuration table, in ascending order of rates */ 346static struct frac_rate_tbl gen_rtbl[] = { 347 /* For vco1div4 = 250 MHz */ 348 {.div = 0x14000}, /* 25 MHz */ 349 {.div = 0x0A000}, /* 50 MHz */ 350 {.div = 0x05000}, /* 100 MHz */ 351 {.div = 0x02000}, /* 250 MHz */ 352}; 353 354/* clock parents */ 355static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 356static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 357static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; 358static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; 359static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", 360 "osc_25m_clk", }; 361static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; 362static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 363static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; 364static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", 365 "i2s_src_pad_clk", }; 366static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; 367static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 368 "pll3_clk", }; 369static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 370 "pll2_clk", }; 371static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", 372 "ras_pll2_clk", "ras_syn0_clk", }; 373static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", 374 "ras_pll2_clk", "ras_syn0_clk", }; 375static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; 376static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", }; 377static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk", 378 "ras_plclk0_clk", }; 379static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; 380static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; 381 382void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) 383{ 384 struct clk *clk, *clk1; 385 386 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); 387 clk_register_clkdev(clk, "osc_32k_clk", NULL); 388 389 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); 390 clk_register_clkdev(clk, "osc_24m_clk", NULL); 391 392 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); 393 clk_register_clkdev(clk, "osc_25m_clk", NULL); 394 395 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); 396 clk_register_clkdev(clk, "gmii_pad_clk", NULL); 397 398 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, 399 12288000); 400 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); 401 402 /* clock derived from 32 KHz osc clk */ 403 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 404 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, 405 &_lock); 406 clk_register_clkdev(clk, NULL, "e0580000.rtc"); 407 408 /* clock derived from 24 or 25 MHz osc clk */ 409 /* vco-pll */ 410 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 411 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 412 SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT, 413 SPEAR1310_PLL_CLK_MASK, 0, &_lock); 414 clk_register_clkdev(clk, "vco1_mclk", NULL); 415 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 416 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 417 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 418 clk_register_clkdev(clk, "vco1_clk", NULL); 419 clk_register_clkdev(clk1, "pll1_clk", NULL); 420 421 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 422 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 423 SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT, 424 SPEAR1310_PLL_CLK_MASK, 0, &_lock); 425 clk_register_clkdev(clk, "vco2_mclk", NULL); 426 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 427 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 428 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 429 clk_register_clkdev(clk, "vco2_clk", NULL); 430 clk_register_clkdev(clk1, "pll2_clk", NULL); 431 432 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 433 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 434 SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT, 435 SPEAR1310_PLL_CLK_MASK, 0, &_lock); 436 clk_register_clkdev(clk, "vco3_mclk", NULL); 437 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 438 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 439 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 440 clk_register_clkdev(clk, "vco3_clk", NULL); 441 clk_register_clkdev(clk1, "pll3_clk", NULL); 442 443 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 444 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, 445 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); 446 clk_register_clkdev(clk, "vco4_clk", NULL); 447 clk_register_clkdev(clk1, "pll4_clk", NULL); 448 449 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 450 48000000); 451 clk_register_clkdev(clk, "pll5_clk", NULL); 452 453 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 454 25000000); 455 clk_register_clkdev(clk, "pll6_clk", NULL); 456 457 /* vco div n clocks */ 458 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 459 2); 460 clk_register_clkdev(clk, "vco1div2_clk", NULL); 461 462 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 463 4); 464 clk_register_clkdev(clk, "vco1div4_clk", NULL); 465 466 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 467 2); 468 clk_register_clkdev(clk, "vco2div2_clk", NULL); 469 470 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 471 2); 472 clk_register_clkdev(clk, "vco3div2_clk", NULL); 473 474 /* peripherals */ 475 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 476 128); 477 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 478 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, 479 &_lock); 480 clk_register_clkdev(clk, NULL, "spear_thermal"); 481 482 /* clock derived from pll4 clk */ 483 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 484 1); 485 clk_register_clkdev(clk, "ddr_clk", NULL); 486 487 /* clock derived from pll1 clk */ 488 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 489 CLK_SET_RATE_PARENT, 1, 2); 490 clk_register_clkdev(clk, "cpu_clk", NULL); 491 492 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 493 2); 494 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 495 496 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 497 2); 498 clk_register_clkdev(clk, NULL, "smp_twd"); 499 500 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 501 6); 502 clk_register_clkdev(clk, "ahb_clk", NULL); 503 504 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, 505 12); 506 clk_register_clkdev(clk, "apb_clk", NULL); 507 508 /* gpt clocks */ 509 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 510 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 511 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT, 512 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 513 clk_register_clkdev(clk, "gpt0_mclk", NULL); 514 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 515 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 516 &_lock); 517 clk_register_clkdev(clk, NULL, "gpt0"); 518 519 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 520 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 521 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT, 522 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 523 clk_register_clkdev(clk, "gpt1_mclk", NULL); 524 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 525 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 526 &_lock); 527 clk_register_clkdev(clk, NULL, "gpt1"); 528 529 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 530 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 531 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT, 532 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 533 clk_register_clkdev(clk, "gpt2_mclk", NULL); 534 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 535 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 536 &_lock); 537 clk_register_clkdev(clk, NULL, "gpt2"); 538 539 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 540 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 541 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT, 542 SPEAR1310_GPT_CLK_MASK, 0, &_lock); 543 clk_register_clkdev(clk, "gpt3_mclk", NULL); 544 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 545 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 546 &_lock); 547 clk_register_clkdev(clk, NULL, "gpt3"); 548 549 /* others */ 550 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", 551 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, 552 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 553 clk_register_clkdev(clk, "uart_syn_clk", NULL); 554 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 555 556 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 557 ARRAY_SIZE(uart0_parents), 558 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 559 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, 560 SPEAR1310_UART_CLK_MASK, 0, &_lock); 561 clk_register_clkdev(clk, "uart0_mclk", NULL); 562 563 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 564 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 565 SPEAR1310_UART_CLK_ENB, 0, &_lock); 566 clk_register_clkdev(clk, NULL, "e0000000.serial"); 567 568 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 569 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, 570 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 571 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 572 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 573 574 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 575 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 576 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); 577 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 578 579 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 580 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, 581 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 582 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 583 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 584 585 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 586 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 587 SPEAR1310_CFXD_CLK_ENB, 0, &_lock); 588 clk_register_clkdev(clk, NULL, "b2800000.cf"); 589 clk_register_clkdev(clk, NULL, "arasan_xd"); 590 591 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 592 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, 593 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 594 clk_register_clkdev(clk, "c3_syn_clk", NULL); 595 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 596 597 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 598 ARRAY_SIZE(c3_parents), 599 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 600 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, 601 SPEAR1310_C3_CLK_MASK, 0, &_lock); 602 clk_register_clkdev(clk, "c3_mclk", NULL); 603 604 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, 605 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, 606 &_lock); 607 clk_register_clkdev(clk, NULL, "c3"); 608 609 /* gmac */ 610 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 611 ARRAY_SIZE(gmac_phy_input_parents), 612 CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG, 613 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 614 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 615 clk_register_clkdev(clk, "phy_input_mclk", NULL); 616 617 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 618 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, 619 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 620 clk_register_clkdev(clk, "phy_syn_clk", NULL); 621 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 622 623 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 624 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, 625 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 626 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 627 clk_register_clkdev(clk, "stmmacphy.0", NULL); 628 629 /* clcd */ 630 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 631 ARRAY_SIZE(clcd_synth_parents), 632 CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT, 633 SPEAR1310_CLCD_SYNT_CLK_SHIFT, 634 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 635 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 636 637 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, 638 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, 639 ARRAY_SIZE(clcd_rtbl), &_lock); 640 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 641 642 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 643 ARRAY_SIZE(clcd_pixel_parents), 644 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 645 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 646 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 647 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 648 649 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 650 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, 651 &_lock); 652 clk_register_clkdev(clk, NULL, "e1000000.clcd"); 653 654 /* i2s */ 655 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 656 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, 657 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT, 658 SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock); 659 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 660 661 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 662 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 663 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 664 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 665 666 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 667 ARRAY_SIZE(i2s_ref_parents), 668 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 669 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, 670 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); 671 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 672 673 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 674 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 675 0, &_lock); 676 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 677 678 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", 679 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, 680 &i2s_sclk_masks, i2s_sclk_rtbl, 681 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 682 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 683 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); 684 685 /* clock derived from ahb clk */ 686 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 687 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, 688 &_lock); 689 clk_register_clkdev(clk, NULL, "e0280000.i2c"); 690 691 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, 692 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, 693 &_lock); 694 clk_register_clkdev(clk, NULL, "ea800000.dma"); 695 clk_register_clkdev(clk, NULL, "eb000000.dma"); 696 697 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, 698 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, 699 &_lock); 700 clk_register_clkdev(clk, NULL, "b2000000.jpeg"); 701 702 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, 703 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, 704 &_lock); 705 clk_register_clkdev(clk, NULL, "e2000000.eth"); 706 707 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, 708 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, 709 &_lock); 710 clk_register_clkdev(clk, NULL, "b0000000.flash"); 711 712 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, 713 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, 714 &_lock); 715 clk_register_clkdev(clk, NULL, "ea000000.flash"); 716 717 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 718 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, 719 &_lock); 720 clk_register_clkdev(clk, NULL, "e4000000.ohci"); 721 clk_register_clkdev(clk, NULL, "e4800000.ehci"); 722 723 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 724 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, 725 &_lock); 726 clk_register_clkdev(clk, NULL, "e5000000.ohci"); 727 clk_register_clkdev(clk, NULL, "e5800000.ehci"); 728 729 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 730 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, 731 &_lock); 732 clk_register_clkdev(clk, NULL, "e3800000.otg"); 733 734 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, 735 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 736 0, &_lock); 737 clk_register_clkdev(clk, NULL, "b1000000.pcie"); 738 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 739 740 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, 741 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 742 0, &_lock); 743 clk_register_clkdev(clk, NULL, "b1800000.pcie"); 744 clk_register_clkdev(clk, NULL, "b1800000.ahci"); 745 746 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, 747 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 748 0, &_lock); 749 clk_register_clkdev(clk, NULL, "b4000000.pcie"); 750 clk_register_clkdev(clk, NULL, "b4000000.ahci"); 751 752 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 753 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, 754 &_lock); 755 clk_register_clkdev(clk, "sysram0_clk", NULL); 756 757 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, 758 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, 759 &_lock); 760 clk_register_clkdev(clk, "sysram1_clk", NULL); 761 762 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 763 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, 764 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 765 clk_register_clkdev(clk, "adc_syn_clk", NULL); 766 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 767 768 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 769 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 770 SPEAR1310_ADC_CLK_ENB, 0, &_lock); 771 clk_register_clkdev(clk, NULL, "e0080000.adc"); 772 773 /* clock derived from apb clk */ 774 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, 775 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, 776 &_lock); 777 clk_register_clkdev(clk, NULL, "e0100000.spi"); 778 779 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, 780 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, 781 &_lock); 782 clk_register_clkdev(clk, NULL, "e0600000.gpio"); 783 784 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, 785 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, 786 &_lock); 787 clk_register_clkdev(clk, NULL, "e0680000.gpio"); 788 789 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, 790 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, 791 &_lock); 792 clk_register_clkdev(clk, NULL, "e0180000.i2s"); 793 794 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, 795 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, 796 &_lock); 797 clk_register_clkdev(clk, NULL, "e0200000.i2s"); 798 799 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 800 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, 801 &_lock); 802 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 803 804 /* RAS clks */ 805 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 806 ARRAY_SIZE(gen_synth0_1_parents), 807 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, 808 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 809 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 810 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 811 812 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 813 ARRAY_SIZE(gen_synth2_3_parents), 814 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG, 815 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 816 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 817 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 818 819 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, 820 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 821 &_lock); 822 clk_register_clkdev(clk, "gen_syn0_clk", NULL); 823 824 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, 825 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 826 &_lock); 827 clk_register_clkdev(clk, "gen_syn1_clk", NULL); 828 829 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, 830 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 831 &_lock); 832 clk_register_clkdev(clk, "gen_syn2_clk", NULL); 833 834 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, 835 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 836 &_lock); 837 clk_register_clkdev(clk, "gen_syn3_clk", NULL); 838 839 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, 840 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, 841 &_lock); 842 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); 843 844 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, 845 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, 846 &_lock); 847 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); 848 849 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, 850 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, 851 &_lock); 852 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); 853 854 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, 855 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, 856 &_lock); 857 clk_register_clkdev(clk, "ras_pll2_clk", NULL); 858 859 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, 860 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, 861 &_lock); 862 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 863 864 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, 865 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, 866 &_lock); 867 clk_register_clkdev(clk, "ras_tx125_clk", NULL); 868 869 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, 870 30000000); 871 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, 872 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, 873 &_lock); 874 clk_register_clkdev(clk, "ras_30m_clk", NULL); 875 876 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, 877 48000000); 878 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, 879 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, 880 &_lock); 881 clk_register_clkdev(clk, "ras_48m_clk", NULL); 882 883 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, 884 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, 885 &_lock); 886 clk_register_clkdev(clk, "ras_ahb_clk", NULL); 887 888 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, 889 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, 890 &_lock); 891 clk_register_clkdev(clk, "ras_apb_clk", NULL); 892 893 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0, 894 50000000); 895 896 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000); 897 898 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, 899 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, 900 &_lock); 901 clk_register_clkdev(clk, NULL, "c_can_platform.0"); 902 903 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, 904 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, 905 &_lock); 906 clk_register_clkdev(clk, NULL, "c_can_platform.1"); 907 908 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, 909 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, 910 &_lock); 911 clk_register_clkdev(clk, NULL, "5c400000.eth"); 912 913 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, 914 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, 915 &_lock); 916 clk_register_clkdev(clk, NULL, "5c500000.eth"); 917 918 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, 919 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, 920 &_lock); 921 clk_register_clkdev(clk, NULL, "5c600000.eth"); 922 923 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, 924 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, 925 &_lock); 926 clk_register_clkdev(clk, NULL, "5c700000.eth"); 927 928 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", 929 smii_rgmii_phy_parents, 930 ARRAY_SIZE(smii_rgmii_phy_parents), 931 CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1, 932 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 933 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 934 clk_register_clkdev(clk, "stmmacphy.1", NULL); 935 clk_register_clkdev(clk, "stmmacphy.2", NULL); 936 clk_register_clkdev(clk, "stmmacphy.4", NULL); 937 938 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 939 ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT, 940 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 941 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 942 clk_register_clkdev(clk, "stmmacphy.3", NULL); 943 944 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 945 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 946 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT, 947 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 948 clk_register_clkdev(clk, "uart1_mclk", NULL); 949 950 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 951 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, 952 &_lock); 953 clk_register_clkdev(clk, NULL, "5c800000.serial"); 954 955 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, 956 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 957 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT, 958 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 959 clk_register_clkdev(clk, "uart2_mclk", NULL); 960 961 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, 962 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, 963 &_lock); 964 clk_register_clkdev(clk, NULL, "5c900000.serial"); 965 966 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, 967 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 968 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT, 969 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 970 clk_register_clkdev(clk, "uart3_mclk", NULL); 971 972 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, 973 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, 974 &_lock); 975 clk_register_clkdev(clk, NULL, "5ca00000.serial"); 976 977 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, 978 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 979 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT, 980 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 981 clk_register_clkdev(clk, "uart4_mclk", NULL); 982 983 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, 984 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, 985 &_lock); 986 clk_register_clkdev(clk, NULL, "5cb00000.serial"); 987 988 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, 989 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 990 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT, 991 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock); 992 clk_register_clkdev(clk, "uart5_mclk", NULL); 993 994 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, 995 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, 996 &_lock); 997 clk_register_clkdev(clk, NULL, "5cc00000.serial"); 998 999 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, 1000 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1001 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT, 1002 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1003 clk_register_clkdev(clk, "i2c1_mclk", NULL); 1004 1005 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, 1006 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, 1007 &_lock); 1008 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 1009 1010 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, 1011 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1012 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT, 1013 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1014 clk_register_clkdev(clk, "i2c2_mclk", NULL); 1015 1016 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, 1017 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, 1018 &_lock); 1019 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 1020 1021 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, 1022 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1023 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT, 1024 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1025 clk_register_clkdev(clk, "i2c3_mclk", NULL); 1026 1027 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, 1028 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, 1029 &_lock); 1030 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 1031 1032 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, 1033 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1034 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT, 1035 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1036 clk_register_clkdev(clk, "i2c4_mclk", NULL); 1037 1038 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, 1039 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, 1040 &_lock); 1041 clk_register_clkdev(clk, NULL, "5d000000.i2c"); 1042 1043 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, 1044 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1045 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT, 1046 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1047 clk_register_clkdev(clk, "i2c5_mclk", NULL); 1048 1049 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, 1050 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, 1051 &_lock); 1052 clk_register_clkdev(clk, NULL, "5d100000.i2c"); 1053 1054 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, 1055 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1056 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT, 1057 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1058 clk_register_clkdev(clk, "i2c6_mclk", NULL); 1059 1060 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, 1061 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, 1062 &_lock); 1063 clk_register_clkdev(clk, NULL, "5d200000.i2c"); 1064 1065 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, 1066 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT, 1067 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT, 1068 SPEAR1310_I2C_CLK_MASK, 0, &_lock); 1069 clk_register_clkdev(clk, "i2c7_mclk", NULL); 1070 1071 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, 1072 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, 1073 &_lock); 1074 clk_register_clkdev(clk, NULL, "5d300000.i2c"); 1075 1076 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, 1077 ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT, 1078 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT, 1079 SPEAR1310_SSP1_CLK_MASK, 0, &_lock); 1080 clk_register_clkdev(clk, "ssp1_mclk", NULL); 1081 1082 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, 1083 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, 1084 &_lock); 1085 clk_register_clkdev(clk, NULL, "5d400000.spi"); 1086 1087 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, 1088 ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT, 1089 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT, 1090 SPEAR1310_PCI_CLK_MASK, 0, &_lock); 1091 clk_register_clkdev(clk, "pci_mclk", NULL); 1092 1093 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, 1094 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, 1095 &_lock); 1096 clk_register_clkdev(clk, NULL, "pci"); 1097 1098 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, 1099 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, 1100 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT, 1101 SPEAR1310_TDM_CLK_MASK, 0, &_lock); 1102 clk_register_clkdev(clk, "tdm1_mclk", NULL); 1103 1104 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, 1105 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, 1106 &_lock); 1107 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 1108 1109 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, 1110 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT, 1111 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT, 1112 SPEAR1310_TDM_CLK_MASK, 0, &_lock); 1113 clk_register_clkdev(clk, "tdm2_mclk", NULL); 1114 1115 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, 1116 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, 1117 &_lock); 1118 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); 1119} 1120