Searched refs:controller (Results 1 - 25 of 633) sorted by last modified time

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/linux-master/net/devlink/
H A Dport.c246 attrs->pci_pf.controller) ||
254 attrs->pci_vf.controller) ||
263 attrs->pci_sf.controller) ||
925 new_attrs.controller =
1378 * @controller: associated controller number for the devlink port instance
1380 * @external: indicates if the port is for an external controller
1382 void devlink_port_attrs_pci_pf_set(struct devlink_port *devlink_port, u32 controller, argument
1394 attrs->pci_pf.controller = controller;
1409 devlink_port_attrs_pci_vf_set(struct devlink_port *devlink_port, u32 controller, u16 pf, u16 vf, bool external) argument
1437 devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port, u32 controller, u16 pf, u32 sf, bool external) argument
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/linux-master/include/net/
H A Ddevlink.h37 * @controller: Associated controller number
39 * @external: when set, indicates if a port is for an external controller
42 u32 controller; member in struct:devlink_port_pci_pf_attrs
49 * @controller: Associated controller number
52 * @external: when set, indicates if a port is for an external controller
55 u32 controller; member in struct:devlink_port_pci_vf_attrs
63 * @controller: Associated controller numbe
69 u32 controller; member in struct:devlink_port_pci_sf_attrs
159 u32 controller; member in struct:devlink_port_new_attrs
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/linux-master/include/linux/spi/
H A Dspi.h133 * @controller: SPI controller used with the device.
154 * @controller_data: Board-specific definitions for controller, such as
167 * @cs_setup: delay to be introduced by the controller after CS is asserted
168 * @cs_hold: delay to be introduced by the controller before CS is deasserted
169 * @cs_inactive: delay to be introduced by the controller after CS is
180 * to its controller. One example might be an identifier for a chip
186 struct spi_controller *controller; member in struct:spi_device
196 * controller on MOSI. Detecting the wait state in software is only
200 * control is expected from SPI controller
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/linux-master/drivers/ufs/host/
H A Dufs-qcom.c16 #include <linux/reset-controller.h>
290 * ufs_qcom_host_reset - reset host controller and PHY
402 * The UTP controller has a number of internal clock gating cells (CGCs).
403 * Internal hardware sub-modules within the UTP controller control the CGCs.
405 * in a specific operation, UTP controller CGCs are by default disabled and
454 * @hba: host controller instance
472 * UTP controller uses SYS1CLK_1US_REG register for Interrupt
475 * controller V4.0.0 onwards.
843 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
844 * @hba: host controller instanc
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H A Dufs-qcom.h8 #include <linux/reset-controller.h>
27 /* QCOM UFS host controller vendor specific registers */
48 * QCOM UFS host controller vendor specific registers
58 /* QCOM UFS host controller vendor specific debug registers */
129 /* QCOM UFS host controller core clk frequencies */
171 /* Host controller hardware version: major.minor.step */
/linux-master/drivers/spi/
H A Dspi.c51 spi_controller_put(spi->controller);
528 * would make them board-specific. Similarly with SPI controller drivers.
559 * spi_device structure to add it to the SPI controller. If the caller
585 spi->controller = ctlr;
611 dev_set_name(&spi->dev, "%s.%u", dev_name(&spi->controller->dev),
655 if (spi->controller == new_spi->controller) {
667 if (spi->controller->cleanup)
668 spi->controller->cleanup(spi);
673 struct spi_controller *ctlr = spi->controller;
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H A Dspi-sun6i.c184 struct sun6i_spi *sspi = spi_controller_get_devdata(spi->controller);
313 * SPI controller. (See spi-sun4i.c)
414 * There are three work modes depending on the controller clock
699 dev_err(&pdev->dev, "Couldn't get reset controller\n");
824 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
H A Dspi-xlp.c141 xspi = spi_controller_get_devdata(spi->controller);
418 /* register spi controller */
448 MODULE_DESCRIPTION("Netlogic XLP SPI controller driver");
H A Dspi-s3c64xx.c150 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
151 * @clk_from_cmu: True, if the controller does not include a clock mux and
157 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
185 * @cntrlr_info: Platform specific data for the controller this driver manages.
188 * @sfr_start: BUS address of SPI controller regs.
189 * @regs: Pointer to ioremap'ed controller registers.
191 * @cur_mode: Stores the active configuration of the controller.
356 spi_controller_get_devdata(spi->controller);
657 * If the receive length is bigger than the controller fifo
791 struct spi_controller *ctlr = spi->controller;
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H A Dspi-sun4i.c164 struct sun4i_spi *sspi = spi_controller_get_devdata(spi->controller);
549 MODULE_DESCRIPTION("Allwinner A1X/A20 SPI controller driver");
H A Dspi-rspi.c949 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
H A Dspi-pxa2xx.c373 spi_controller_get_devdata(spi->controller);
396 (drv_data->controller->max_speed_hz / 2));
403 spi_controller_get_devdata(spi->controller);
439 spi_controller_get_devdata(spi->controller);
453 spi_controller_get_devdata(spi->controller);
596 if (drv_data->controller->cur_msg) {
597 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
637 drv_data->controller->cur_msg->status = err;
638 spi_finalize_current_transfer(drv_data->controller);
645 spi_finalize_current_transfer(drv_data->controller);
941 pxa2xx_spi_can_dma(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *xfer) argument
952 pxa2xx_spi_transfer_one(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *transfer) argument
1111 pxa2xx_spi_target_abort(struct spi_controller *controller) argument
1120 pxa2xx_spi_handle_err(struct spi_controller *controller, struct spi_message *msg) argument
1141 pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) argument
1375 pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, unsigned int cs) argument
1408 struct spi_controller *controller; local
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H A Dspi-pxa2xx.h20 * The platform data for SSP controller devices
48 struct spi_controller *controller; member in struct:driver_data
H A Dspi-pxa2xx-dma.c28 struct spi_message *msg = drv_data->controller->cur_msg;
57 spi_finalize_current_transfer(drv_data->controller);
98 chan = drv_data->controller->dma_tx;
105 chan = drv_data->controller->dma_rx;
126 dmaengine_terminate_async(drv_data->controller->dma_rx);
127 dmaengine_terminate_async(drv_data->controller->dma_tx);
165 dmaengine_terminate_async(drv_data->controller->dma_tx);
172 dma_async_issue_pending(drv_data->controller->dma_rx);
173 dma_async_issue_pending(drv_data->controller->dma_tx);
181 dmaengine_terminate_sync(drv_data->controller
188 struct spi_controller *controller = drv_data->controller; local
213 struct spi_controller *controller = drv_data->controller; local
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H A Dspi-omap2-mcspi.c3 * OMAP2 McSPI controller driver
121 /* Virtual base address of the controller */
241 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
244 /* The controller handles the inverted chip selects
307 struct spi_controller *ctlr = spi->controller;
394 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
406 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
423 mcspi = spi_controller_get_devdata(spi->controller);
461 mcspi = spi_controller_get_devdata(spi->controller);
606 mcspi = spi_controller_get_devdata(spi->controller);
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H A Dspi-pic32-sqi.c3 * PIC32 Quad SPI controller driver.
96 /* PESQI controller buffer descriptor */
123 * @bd: PESQI controller buffer descriptor
124 * @bd_dma: DMA address of PESQI controller buffer descriptor
437 spi_finalize_current_message(spi->controller);
512 /* Soft-reset of PESQI controller triggers interrupt.
691 MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SQI controller.");
H A Dspi-mt7621.c3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
67 return spi_controller_get_devdata(spi->controller);
132 * This SPI controller seems to be tested on SPI flash only and some
277 * This controller will shift some extra data out
H A Dspi-oc-tiny.c56 return spi_controller_get_devdata(sdev->controller);
259 /* register our spi controller */
H A Dspi-mux.c21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
28 * spi controller
48 /* should not get called when the parent controller is doing a transfer */
51 struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller);
78 struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller);
159 ctlr->mode_bits = spi->controller->mode_bits;
160 ctlr->flags = spi->controller->flags;
H A Dspi-mt65xx.c116 * @need_pad_sel: Enable pad (pins) selection in SPI controller
134 * @base: Start address of the SPI controller registers
135 * @state: SPI controller state
286 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller);
465 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller);
703 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller);
734 struct mtk_spi *mdata = spi_controller_get_devdata(spi->controller);
915 struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller);
945 struct mtk_spi *mdata = spi_controller_get_devdata(mem->spi->controller);
954 mtk_spi_hw_init(mem->spi->controller, me
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H A Dspi-loopback-test.c48 "if set controller will be asked to enable test loop mode. " \
49 "If controller supported it, MISO and MOSI will be connected");
331 * This should be large enough for the controller driver to
1033 (spi->controller->dma_alignment ? \
1034 spi->controller->dma_alignment : \
H A Dspi-imx.c93 struct spi_controller *controller; member in struct:spi_imx_data
233 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi, argument
236 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
238 if (!use_dma || controller->fallback)
241 if (!controller->dma_rx)
524 return spi->controller->unused_native_cs;
1209 static int spi_imx_dma_configure(struct spi_controller *controller) argument
1214 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1234 ret = dmaengine_slave_config(controller->dma_tx, &tx);
1244 ret = dmaengine_slave_config(controller
1324 struct spi_controller *controller = spi_imx->controller; local
1337 spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, struct spi_controller *controller) argument
1409 struct spi_controller *controller = spi_imx->controller; local
1623 spi_imx_transfer_one(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *transfer) argument
1674 spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg) argument
1695 spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg) argument
1704 spi_imx_target_abort(struct spi_controller *controller) argument
1717 struct spi_controller *controller; local
1897 struct spi_controller *controller = platform_get_drvdata(pdev); local
1918 struct spi_controller *controller = dev_get_drvdata(dev); local
1939 struct spi_controller *controller = dev_get_drvdata(dev); local
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H A Dspi-fsl-spi.c3 * Freescale SPI controller driver.
91 struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);
186 mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
254 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
345 static int fsl_spi_transfer_one(struct spi_controller *controller, argument
362 static int fsl_spi_unprepare_message(struct spi_controller *controller, argument
387 mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
481 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
600 /* SPI controller initializations */
H A Dspi-fsl-lpspi.c173 static bool fsl_lpspi_can_dma(struct spi_controller *controller, argument
179 if (!controller->dma_rx)
196 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) argument
199 spi_controller_get_devdata(controller);
211 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) argument
214 spi_controller_get_devdata(controller);
336 static int fsl_lpspi_dma_configure(struct spi_controller *controller) argument
342 spi_controller_get_devdata(controller);
362 ret = dmaengine_slave_config(controller->dma_tx, &tx);
373 ret = dmaengine_slave_config(controller
416 fsl_lpspi_setup_transfer(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *t) argument
464 fsl_lpspi_target_abort(struct spi_controller *controller) argument
480 fsl_lpspi_wait_for_completion(struct spi_controller *controller) argument
550 fsl_lpspi_dma_transfer(struct spi_controller *controller, struct fsl_lpspi_data *fsl_lpspi, struct spi_transfer *transfer) argument
643 fsl_lpspi_dma_exit(struct spi_controller *controller) argument
656 fsl_lpspi_dma_init(struct device *dev, struct fsl_lpspi_data *fsl_lpspi, struct spi_controller *controller) argument
691 fsl_lpspi_pio_transfer(struct spi_controller *controller, struct spi_transfer *t) argument
716 fsl_lpspi_transfer_one(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *t) argument
777 struct spi_controller *controller = dev_get_drvdata(dev); local
798 struct spi_controller *controller = dev_get_drvdata(dev); local
824 struct spi_controller *controller; local
954 struct spi_controller *controller = platform_get_drvdata(pdev); local
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H A Dspi-fsl-dspi.c999 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1041 "DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",
1084 spi->controller->bus_num, spi_get_chipselect(spi, 0));

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