1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 4 * Copyright (C) 2013, 2021 Intel Corporation 5 */ 6 7#include <linux/acpi.h> 8#include <linux/bitops.h> 9#include <linux/clk.h> 10#include <linux/delay.h> 11#include <linux/device.h> 12#include <linux/dmaengine.h> 13#include <linux/err.h> 14#include <linux/errno.h> 15#include <linux/gpio/consumer.h> 16#include <linux/init.h> 17#include <linux/interrupt.h> 18#include <linux/ioport.h> 19#include <linux/kernel.h> 20#include <linux/module.h> 21#include <linux/mod_devicetable.h> 22#include <linux/of.h> 23#include <linux/platform_device.h> 24#include <linux/pm_runtime.h> 25#include <linux/property.h> 26#include <linux/slab.h> 27 28#include <linux/spi/pxa2xx_spi.h> 29#include <linux/spi/spi.h> 30 31#include "spi-pxa2xx.h" 32 33MODULE_AUTHOR("Stephen Street"); 34MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 35MODULE_LICENSE("GPL"); 36MODULE_ALIAS("platform:pxa2xx-spi"); 37 38#define TIMOUT_DFLT 1000 39 40/* 41 * For testing SSCR1 changes that require SSP restart, basically 42 * everything except the service and interrupt enables, the PXA270 developer 43 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 44 * list, but the PXA255 developer manual says all bits without really meaning 45 * the service and interrupt enables. 46 */ 47#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 48 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 49 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 50 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 51 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 52 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 53 54#define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 55 | QUARK_X1000_SSCR1_EFWR \ 56 | QUARK_X1000_SSCR1_RFT \ 57 | QUARK_X1000_SSCR1_TFT \ 58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 59 60#define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 64 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 66 67#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 68#define LPSS_CS_CONTROL_SW_MODE BIT(0) 69#define LPSS_CS_CONTROL_CS_HIGH BIT(1) 70#define LPSS_CAPS_CS_EN_SHIFT 9 71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 72 73#define LPSS_PRIV_CLOCK_GATE 0x38 74#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 75#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 76 77struct lpss_config { 78 /* LPSS offset from drv_data->ioaddr */ 79 unsigned offset; 80 /* Register offsets from drv_data->lpss_base or -1 */ 81 int reg_general; 82 int reg_ssp; 83 int reg_cs_ctrl; 84 int reg_capabilities; 85 /* FIFO thresholds */ 86 u32 rx_threshold; 87 u32 tx_threshold_lo; 88 u32 tx_threshold_hi; 89 /* Chip select control */ 90 unsigned cs_sel_shift; 91 unsigned cs_sel_mask; 92 unsigned cs_num; 93 /* Quirks */ 94 unsigned cs_clk_stays_gated : 1; 95}; 96 97/* Keep these sorted with enum pxa_ssp_type */ 98static const struct lpss_config lpss_platforms[] = { 99 { /* LPSS_LPT_SSP */ 100 .offset = 0x800, 101 .reg_general = 0x08, 102 .reg_ssp = 0x0c, 103 .reg_cs_ctrl = 0x18, 104 .reg_capabilities = -1, 105 .rx_threshold = 64, 106 .tx_threshold_lo = 160, 107 .tx_threshold_hi = 224, 108 }, 109 { /* LPSS_BYT_SSP */ 110 .offset = 0x400, 111 .reg_general = 0x08, 112 .reg_ssp = 0x0c, 113 .reg_cs_ctrl = 0x18, 114 .reg_capabilities = -1, 115 .rx_threshold = 64, 116 .tx_threshold_lo = 160, 117 .tx_threshold_hi = 224, 118 }, 119 { /* LPSS_BSW_SSP */ 120 .offset = 0x400, 121 .reg_general = 0x08, 122 .reg_ssp = 0x0c, 123 .reg_cs_ctrl = 0x18, 124 .reg_capabilities = -1, 125 .rx_threshold = 64, 126 .tx_threshold_lo = 160, 127 .tx_threshold_hi = 224, 128 .cs_sel_shift = 2, 129 .cs_sel_mask = 1 << 2, 130 .cs_num = 2, 131 }, 132 { /* LPSS_SPT_SSP */ 133 .offset = 0x200, 134 .reg_general = -1, 135 .reg_ssp = 0x20, 136 .reg_cs_ctrl = 0x24, 137 .reg_capabilities = -1, 138 .rx_threshold = 1, 139 .tx_threshold_lo = 32, 140 .tx_threshold_hi = 56, 141 }, 142 { /* LPSS_BXT_SSP */ 143 .offset = 0x200, 144 .reg_general = -1, 145 .reg_ssp = 0x20, 146 .reg_cs_ctrl = 0x24, 147 .reg_capabilities = 0xfc, 148 .rx_threshold = 1, 149 .tx_threshold_lo = 16, 150 .tx_threshold_hi = 48, 151 .cs_sel_shift = 8, 152 .cs_sel_mask = 3 << 8, 153 .cs_clk_stays_gated = true, 154 }, 155 { /* LPSS_CNL_SSP */ 156 .offset = 0x200, 157 .reg_general = -1, 158 .reg_ssp = 0x20, 159 .reg_cs_ctrl = 0x24, 160 .reg_capabilities = 0xfc, 161 .rx_threshold = 1, 162 .tx_threshold_lo = 32, 163 .tx_threshold_hi = 56, 164 .cs_sel_shift = 8, 165 .cs_sel_mask = 3 << 8, 166 .cs_clk_stays_gated = true, 167 }, 168}; 169 170static inline const struct lpss_config 171*lpss_get_config(const struct driver_data *drv_data) 172{ 173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 174} 175 176static bool is_lpss_ssp(const struct driver_data *drv_data) 177{ 178 switch (drv_data->ssp_type) { 179 case LPSS_LPT_SSP: 180 case LPSS_BYT_SSP: 181 case LPSS_BSW_SSP: 182 case LPSS_SPT_SSP: 183 case LPSS_BXT_SSP: 184 case LPSS_CNL_SSP: 185 return true; 186 default: 187 return false; 188 } 189} 190 191static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 192{ 193 return drv_data->ssp_type == QUARK_X1000_SSP; 194} 195 196static bool is_mmp2_ssp(const struct driver_data *drv_data) 197{ 198 return drv_data->ssp_type == MMP2_SSP; 199} 200 201static bool is_mrfld_ssp(const struct driver_data *drv_data) 202{ 203 return drv_data->ssp_type == MRFLD_SSP; 204} 205 206static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value) 207{ 208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value) 209 pxa2xx_spi_write(drv_data, reg, value & mask); 210} 211 212static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 213{ 214 switch (drv_data->ssp_type) { 215 case QUARK_X1000_SSP: 216 return QUARK_X1000_SSCR1_CHANGE_MASK; 217 case CE4100_SSP: 218 return CE4100_SSCR1_CHANGE_MASK; 219 default: 220 return SSCR1_CHANGE_MASK; 221 } 222} 223 224static u32 225pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 226{ 227 switch (drv_data->ssp_type) { 228 case QUARK_X1000_SSP: 229 return RX_THRESH_QUARK_X1000_DFLT; 230 case CE4100_SSP: 231 return RX_THRESH_CE4100_DFLT; 232 default: 233 return RX_THRESH_DFLT; 234 } 235} 236 237static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 238{ 239 u32 mask; 240 241 switch (drv_data->ssp_type) { 242 case QUARK_X1000_SSP: 243 mask = QUARK_X1000_SSSR_TFL_MASK; 244 break; 245 case CE4100_SSP: 246 mask = CE4100_SSSR_TFL_MASK; 247 break; 248 default: 249 mask = SSSR_TFL_MASK; 250 break; 251 } 252 253 return read_SSSR_bits(drv_data, mask) == mask; 254} 255 256static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 257 u32 *sccr1_reg) 258{ 259 u32 mask; 260 261 switch (drv_data->ssp_type) { 262 case QUARK_X1000_SSP: 263 mask = QUARK_X1000_SSCR1_RFT; 264 break; 265 case CE4100_SSP: 266 mask = CE4100_SSCR1_RFT; 267 break; 268 default: 269 mask = SSCR1_RFT; 270 break; 271 } 272 *sccr1_reg &= ~mask; 273} 274 275static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 276 u32 *sccr1_reg, u32 threshold) 277{ 278 switch (drv_data->ssp_type) { 279 case QUARK_X1000_SSP: 280 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 281 break; 282 case CE4100_SSP: 283 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 284 break; 285 default: 286 *sccr1_reg |= SSCR1_RxTresh(threshold); 287 break; 288 } 289} 290 291static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 292 u32 clk_div, u8 bits) 293{ 294 switch (drv_data->ssp_type) { 295 case QUARK_X1000_SSP: 296 return clk_div 297 | QUARK_X1000_SSCR0_Motorola 298 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits); 299 default: 300 return clk_div 301 | SSCR0_Motorola 302 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 303 | (bits > 16 ? SSCR0_EDSS : 0); 304 } 305} 306 307/* 308 * Read and write LPSS SSP private registers. Caller must first check that 309 * is_lpss_ssp() returns true before these can be called. 310 */ 311static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 312{ 313 WARN_ON(!drv_data->lpss_base); 314 return readl(drv_data->lpss_base + offset); 315} 316 317static void __lpss_ssp_write_priv(struct driver_data *drv_data, 318 unsigned offset, u32 value) 319{ 320 WARN_ON(!drv_data->lpss_base); 321 writel(value, drv_data->lpss_base + offset); 322} 323 324/* 325 * lpss_ssp_setup - perform LPSS SSP specific setup 326 * @drv_data: pointer to the driver private data 327 * 328 * Perform LPSS SSP specific setup. This function must be called first if 329 * one is going to use LPSS SSP private registers. 330 */ 331static void lpss_ssp_setup(struct driver_data *drv_data) 332{ 333 const struct lpss_config *config; 334 u32 value; 335 336 config = lpss_get_config(drv_data); 337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; 338 339 /* Enable software chip select control */ 340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 341 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 342 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 344 345 /* Enable multiblock DMA transfers */ 346 if (drv_data->controller_info->enable_dma) { 347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 348 349 if (config->reg_general >= 0) { 350 value = __lpss_ssp_read_priv(drv_data, 351 config->reg_general); 352 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 353 __lpss_ssp_write_priv(drv_data, 354 config->reg_general, value); 355 } 356 } 357} 358 359static void lpss_ssp_select_cs(struct spi_device *spi, 360 const struct lpss_config *config) 361{ 362 struct driver_data *drv_data = 363 spi_controller_get_devdata(spi->controller); 364 u32 value, cs; 365 366 if (!config->cs_sel_mask) 367 return; 368 369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 370 371 cs = spi_get_chipselect(spi, 0); 372 cs <<= config->cs_sel_shift; 373 if (cs != (value & config->cs_sel_mask)) { 374 /* 375 * When switching another chip select output active the 376 * output must be selected first and wait 2 ssp_clk cycles 377 * before changing state to active. Otherwise a short 378 * glitch will occur on the previous chip select since 379 * output select is latched but state control is not. 380 */ 381 value &= ~config->cs_sel_mask; 382 value |= cs; 383 __lpss_ssp_write_priv(drv_data, 384 config->reg_cs_ctrl, value); 385 ndelay(1000000000 / 386 (drv_data->controller->max_speed_hz / 2)); 387 } 388} 389 390static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) 391{ 392 struct driver_data *drv_data = 393 spi_controller_get_devdata(spi->controller); 394 const struct lpss_config *config; 395 u32 value; 396 397 config = lpss_get_config(drv_data); 398 399 if (enable) 400 lpss_ssp_select_cs(spi, config); 401 402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 403 if (enable) 404 value &= ~LPSS_CS_CONTROL_CS_HIGH; 405 else 406 value |= LPSS_CS_CONTROL_CS_HIGH; 407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 408 if (config->cs_clk_stays_gated) { 409 u32 clkgate; 410 411 /* 412 * Changing CS alone when dynamic clock gating is on won't 413 * actually flip CS at that time. This ruins SPI transfers 414 * that specify delays, or have no data. Toggle the clock mode 415 * to force on briefly to poke the CS pin to move. 416 */ 417 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE); 418 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) | 419 LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON; 420 421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value); 422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate); 423 } 424} 425 426static void cs_assert(struct spi_device *spi) 427{ 428 struct driver_data *drv_data = 429 spi_controller_get_devdata(spi->controller); 430 431 if (drv_data->ssp_type == CE4100_SSP) { 432 pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); 433 return; 434 } 435 436 if (is_lpss_ssp(drv_data)) 437 lpss_ssp_cs_control(spi, true); 438} 439 440static void cs_deassert(struct spi_device *spi) 441{ 442 struct driver_data *drv_data = 443 spi_controller_get_devdata(spi->controller); 444 unsigned long timeout; 445 446 if (drv_data->ssp_type == CE4100_SSP) 447 return; 448 449 /* Wait until SSP becomes idle before deasserting the CS */ 450 timeout = jiffies + msecs_to_jiffies(10); 451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 452 !time_after(jiffies, timeout)) 453 cpu_relax(); 454 455 if (is_lpss_ssp(drv_data)) 456 lpss_ssp_cs_control(spi, false); 457} 458 459static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) 460{ 461 if (level) 462 cs_deassert(spi); 463 else 464 cs_assert(spi); 465} 466 467int pxa2xx_spi_flush(struct driver_data *drv_data) 468{ 469 unsigned long limit = loops_per_jiffy << 1; 470 471 do { 472 while (read_SSSR_bits(drv_data, SSSR_RNE)) 473 pxa2xx_spi_read(drv_data, SSDR); 474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 475 write_SSSR_CS(drv_data, SSSR_ROR); 476 477 return limit; 478} 479 480static void pxa2xx_spi_off(struct driver_data *drv_data) 481{ 482 /* On MMP, disabling SSE seems to corrupt the Rx FIFO */ 483 if (is_mmp2_ssp(drv_data)) 484 return; 485 486 pxa_ssp_disable(drv_data->ssp); 487} 488 489static int null_writer(struct driver_data *drv_data) 490{ 491 u8 n_bytes = drv_data->n_bytes; 492 493 if (pxa2xx_spi_txfifo_full(drv_data) 494 || (drv_data->tx == drv_data->tx_end)) 495 return 0; 496 497 pxa2xx_spi_write(drv_data, SSDR, 0); 498 drv_data->tx += n_bytes; 499 500 return 1; 501} 502 503static int null_reader(struct driver_data *drv_data) 504{ 505 u8 n_bytes = drv_data->n_bytes; 506 507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 508 pxa2xx_spi_read(drv_data, SSDR); 509 drv_data->rx += n_bytes; 510 } 511 512 return drv_data->rx == drv_data->rx_end; 513} 514 515static int u8_writer(struct driver_data *drv_data) 516{ 517 if (pxa2xx_spi_txfifo_full(drv_data) 518 || (drv_data->tx == drv_data->tx_end)) 519 return 0; 520 521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 522 ++drv_data->tx; 523 524 return 1; 525} 526 527static int u8_reader(struct driver_data *drv_data) 528{ 529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 531 ++drv_data->rx; 532 } 533 534 return drv_data->rx == drv_data->rx_end; 535} 536 537static int u16_writer(struct driver_data *drv_data) 538{ 539 if (pxa2xx_spi_txfifo_full(drv_data) 540 || (drv_data->tx == drv_data->tx_end)) 541 return 0; 542 543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 544 drv_data->tx += 2; 545 546 return 1; 547} 548 549static int u16_reader(struct driver_data *drv_data) 550{ 551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 553 drv_data->rx += 2; 554 } 555 556 return drv_data->rx == drv_data->rx_end; 557} 558 559static int u32_writer(struct driver_data *drv_data) 560{ 561 if (pxa2xx_spi_txfifo_full(drv_data) 562 || (drv_data->tx == drv_data->tx_end)) 563 return 0; 564 565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 566 drv_data->tx += 4; 567 568 return 1; 569} 570 571static int u32_reader(struct driver_data *drv_data) 572{ 573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { 574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 575 drv_data->rx += 4; 576 } 577 578 return drv_data->rx == drv_data->rx_end; 579} 580 581static void reset_sccr1(struct driver_data *drv_data) 582{ 583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; 584 struct chip_data *chip; 585 586 if (drv_data->controller->cur_msg) { 587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); 588 threshold = chip->threshold; 589 } else { 590 threshold = 0; 591 } 592 593 switch (drv_data->ssp_type) { 594 case QUARK_X1000_SSP: 595 mask |= QUARK_X1000_SSCR1_RFT; 596 break; 597 case CE4100_SSP: 598 mask |= CE4100_SSCR1_RFT; 599 break; 600 default: 601 mask |= SSCR1_RFT; 602 break; 603 } 604 605 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold); 606} 607 608static void int_stop_and_reset(struct driver_data *drv_data) 609{ 610 /* Clear and disable interrupts */ 611 write_SSSR_CS(drv_data, drv_data->clear_sr); 612 reset_sccr1(drv_data); 613 if (pxa25x_ssp_comp(drv_data)) 614 return; 615 616 pxa2xx_spi_write(drv_data, SSTO, 0); 617} 618 619static void int_error_stop(struct driver_data *drv_data, const char *msg, int err) 620{ 621 int_stop_and_reset(drv_data); 622 pxa2xx_spi_flush(drv_data); 623 pxa2xx_spi_off(drv_data); 624 625 dev_err(drv_data->ssp->dev, "%s\n", msg); 626 627 drv_data->controller->cur_msg->status = err; 628 spi_finalize_current_transfer(drv_data->controller); 629} 630 631static void int_transfer_complete(struct driver_data *drv_data) 632{ 633 int_stop_and_reset(drv_data); 634 635 spi_finalize_current_transfer(drv_data->controller); 636} 637 638static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 639{ 640 u32 irq_status; 641 642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); 643 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE)) 644 irq_status &= ~SSSR_TFS; 645 646 if (irq_status & SSSR_ROR) { 647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); 648 return IRQ_HANDLED; 649 } 650 651 if (irq_status & SSSR_TUR) { 652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); 653 return IRQ_HANDLED; 654 } 655 656 if (irq_status & SSSR_TINT) { 657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 658 if (drv_data->read(drv_data)) { 659 int_transfer_complete(drv_data); 660 return IRQ_HANDLED; 661 } 662 } 663 664 /* Drain Rx FIFO, Fill Tx FIFO and prevent overruns */ 665 do { 666 if (drv_data->read(drv_data)) { 667 int_transfer_complete(drv_data); 668 return IRQ_HANDLED; 669 } 670 } while (drv_data->write(drv_data)); 671 672 if (drv_data->read(drv_data)) { 673 int_transfer_complete(drv_data); 674 return IRQ_HANDLED; 675 } 676 677 if (drv_data->tx == drv_data->tx_end) { 678 u32 bytes_left; 679 u32 sccr1_reg; 680 681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 682 sccr1_reg &= ~SSCR1_TIE; 683 684 /* 685 * PXA25x_SSP has no timeout, set up Rx threshold for 686 * the remaining Rx bytes. 687 */ 688 if (pxa25x_ssp_comp(drv_data)) { 689 u32 rx_thre; 690 691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 692 693 bytes_left = drv_data->rx_end - drv_data->rx; 694 switch (drv_data->n_bytes) { 695 case 4: 696 bytes_left >>= 2; 697 break; 698 case 2: 699 bytes_left >>= 1; 700 break; 701 } 702 703 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 704 if (rx_thre > bytes_left) 705 rx_thre = bytes_left; 706 707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 708 } 709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 710 } 711 712 /* We did something */ 713 return IRQ_HANDLED; 714} 715 716static void handle_bad_msg(struct driver_data *drv_data) 717{ 718 int_stop_and_reset(drv_data); 719 pxa2xx_spi_off(drv_data); 720 721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); 722} 723 724static irqreturn_t ssp_int(int irq, void *dev_id) 725{ 726 struct driver_data *drv_data = dev_id; 727 u32 sccr1_reg; 728 u32 mask = drv_data->mask_sr; 729 u32 status; 730 731 /* 732 * The IRQ might be shared with other peripherals so we must first 733 * check that are we RPM suspended or not. If we are we assume that 734 * the IRQ was not for us (we shouldn't be RPM suspended when the 735 * interrupt is enabled). 736 */ 737 if (pm_runtime_suspended(drv_data->ssp->dev)) 738 return IRQ_NONE; 739 740 /* 741 * If the device is not yet in RPM suspended state and we get an 742 * interrupt that is meant for another device, check if status bits 743 * are all set to one. That means that the device is already 744 * powered off. 745 */ 746 status = pxa2xx_spi_read(drv_data, SSSR); 747 if (status == ~0) 748 return IRQ_NONE; 749 750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 751 752 /* Ignore possible writes if we don't need to write */ 753 if (!(sccr1_reg & SSCR1_TIE)) 754 mask &= ~SSSR_TFS; 755 756 /* Ignore RX timeout interrupt if it is disabled */ 757 if (!(sccr1_reg & SSCR1_TINTE)) 758 mask &= ~SSSR_TINT; 759 760 if (!(status & mask)) 761 return IRQ_NONE; 762 763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 765 766 if (!drv_data->controller->cur_msg) { 767 handle_bad_msg(drv_data); 768 /* Never fail */ 769 return IRQ_HANDLED; 770 } 771 772 return drv_data->transfer_handler(drv_data); 773} 774 775/* 776 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 777 * input frequency by fractions of 2^24. It also has a divider by 5. 778 * 779 * There are formulas to get baud rate value for given input frequency and 780 * divider parameters, such as DDS_CLK_RATE and SCR: 781 * 782 * Fsys = 200MHz 783 * 784 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 785 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 786 * 787 * DDS_CLK_RATE either 2^n or 2^n / 5. 788 * SCR is in range 0 .. 255 789 * 790 * Divisor = 5^i * 2^j * 2 * k 791 * i = [0, 1] i = 1 iff j = 0 or j > 3 792 * j = [0, 23] j = 0 iff i = 1 793 * k = [1, 256] 794 * Special case: j = 0, i = 1: Divisor = 2 / 5 795 * 796 * Accordingly to the specification the recommended values for DDS_CLK_RATE 797 * are: 798 * Case 1: 2^n, n = [0, 23] 799 * Case 2: 2^24 * 2 / 5 (0x666666) 800 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 801 * 802 * In all cases the lowest possible value is better. 803 * 804 * The function calculates parameters for all cases and chooses the one closest 805 * to the asked baud rate. 806 */ 807static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 808{ 809 unsigned long xtal = 200000000; 810 unsigned long fref = xtal / 2; /* mandatory division by 2, 811 see (2) */ 812 /* case 3 */ 813 unsigned long fref1 = fref / 2; /* case 1 */ 814 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 815 unsigned long scale; 816 unsigned long q, q1, q2; 817 long r, r1, r2; 818 u32 mul; 819 820 /* Case 1 */ 821 822 /* Set initial value for DDS_CLK_RATE */ 823 mul = (1 << 24) >> 1; 824 825 /* Calculate initial quot */ 826 q1 = DIV_ROUND_UP(fref1, rate); 827 828 /* Scale q1 if it's too big */ 829 if (q1 > 256) { 830 /* Scale q1 to range [1, 512] */ 831 scale = fls_long(q1 - 1); 832 if (scale > 9) { 833 q1 >>= scale - 9; 834 mul >>= scale - 9; 835 } 836 837 /* Round the result if we have a remainder */ 838 q1 += q1 & 1; 839 } 840 841 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 842 scale = __ffs(q1); 843 q1 >>= scale; 844 mul >>= scale; 845 846 /* Get the remainder */ 847 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 848 849 /* Case 2 */ 850 851 q2 = DIV_ROUND_UP(fref2, rate); 852 r2 = abs(fref2 / q2 - rate); 853 854 /* 855 * Choose the best between two: less remainder we have the better. We 856 * can't go case 2 if q2 is greater than 256 since SCR register can 857 * hold only values 0 .. 255. 858 */ 859 if (r2 >= r1 || q2 > 256) { 860 /* case 1 is better */ 861 r = r1; 862 q = q1; 863 } else { 864 /* case 2 is better */ 865 r = r2; 866 q = q2; 867 mul = (1 << 24) * 2 / 5; 868 } 869 870 /* Check case 3 only if the divisor is big enough */ 871 if (fref / rate >= 80) { 872 u64 fssp; 873 u32 m; 874 875 /* Calculate initial quot */ 876 q1 = DIV_ROUND_UP(fref, rate); 877 m = (1 << 24) / q1; 878 879 /* Get the remainder */ 880 fssp = (u64)fref * m; 881 do_div(fssp, 1 << 24); 882 r1 = abs(fssp - rate); 883 884 /* Choose this one if it suits better */ 885 if (r1 < r) { 886 /* case 3 is better */ 887 q = 1; 888 mul = m; 889 } 890 } 891 892 *dds = mul; 893 return q - 1; 894} 895 896static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 897{ 898 unsigned long ssp_clk = drv_data->controller->max_speed_hz; 899 const struct ssp_device *ssp = drv_data->ssp; 900 901 rate = min_t(int, ssp_clk, rate); 902 903 /* 904 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding 905 * that the SSP transmission rate can be greater than the device rate. 906 */ 907 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 908 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; 909 else 910 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; 911} 912 913static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 914 int rate) 915{ 916 struct chip_data *chip = 917 spi_get_ctldata(drv_data->controller->cur_msg->spi); 918 unsigned int clk_div; 919 920 switch (drv_data->ssp_type) { 921 case QUARK_X1000_SSP: 922 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 923 break; 924 default: 925 clk_div = ssp_get_clk_div(drv_data, rate); 926 break; 927 } 928 return clk_div << 8; 929} 930 931static bool pxa2xx_spi_can_dma(struct spi_controller *controller, 932 struct spi_device *spi, 933 struct spi_transfer *xfer) 934{ 935 struct chip_data *chip = spi_get_ctldata(spi); 936 937 return chip->enable_dma && 938 xfer->len <= MAX_DMA_LEN && 939 xfer->len >= chip->dma_burst_size; 940} 941 942static int pxa2xx_spi_transfer_one(struct spi_controller *controller, 943 struct spi_device *spi, 944 struct spi_transfer *transfer) 945{ 946 struct driver_data *drv_data = spi_controller_get_devdata(controller); 947 struct spi_message *message = controller->cur_msg; 948 struct chip_data *chip = spi_get_ctldata(spi); 949 u32 dma_thresh = chip->dma_threshold; 950 u32 dma_burst = chip->dma_burst_size; 951 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 952 u32 clk_div; 953 u8 bits; 954 u32 speed; 955 u32 cr0; 956 u32 cr1; 957 int err; 958 int dma_mapped; 959 960 /* Check if we can DMA this transfer */ 961 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 962 963 /* Reject already-mapped transfers; PIO won't always work */ 964 if (message->is_dma_mapped 965 || transfer->rx_dma || transfer->tx_dma) { 966 dev_err(&spi->dev, 967 "Mapped transfer length of %u is greater than %d\n", 968 transfer->len, MAX_DMA_LEN); 969 return -EINVAL; 970 } 971 972 /* Warn ... we force this to PIO mode */ 973 dev_warn_ratelimited(&spi->dev, 974 "DMA disabled for transfer length %u greater than %d\n", 975 transfer->len, MAX_DMA_LEN); 976 } 977 978 /* Setup the transfer state based on the type of transfer */ 979 if (pxa2xx_spi_flush(drv_data) == 0) { 980 dev_err(&spi->dev, "Flush failed\n"); 981 return -EIO; 982 } 983 drv_data->tx = (void *)transfer->tx_buf; 984 drv_data->tx_end = drv_data->tx + transfer->len; 985 drv_data->rx = transfer->rx_buf; 986 drv_data->rx_end = drv_data->rx + transfer->len; 987 988 /* Change speed and bit per word on a per transfer */ 989 bits = transfer->bits_per_word; 990 speed = transfer->speed_hz; 991 992 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 993 994 if (bits <= 8) { 995 drv_data->n_bytes = 1; 996 drv_data->read = drv_data->rx ? u8_reader : null_reader; 997 drv_data->write = drv_data->tx ? u8_writer : null_writer; 998 } else if (bits <= 16) { 999 drv_data->n_bytes = 2; 1000 drv_data->read = drv_data->rx ? u16_reader : null_reader; 1001 drv_data->write = drv_data->tx ? u16_writer : null_writer; 1002 } else if (bits <= 32) { 1003 drv_data->n_bytes = 4; 1004 drv_data->read = drv_data->rx ? u32_reader : null_reader; 1005 drv_data->write = drv_data->tx ? u32_writer : null_writer; 1006 } 1007 /* 1008 * If bits per word is changed in DMA mode, then must check 1009 * the thresholds and burst also. 1010 */ 1011 if (chip->enable_dma) { 1012 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 1013 spi, 1014 bits, &dma_burst, 1015 &dma_thresh)) 1016 dev_warn_ratelimited(&spi->dev, 1017 "DMA burst size reduced to match bits_per_word\n"); 1018 } 1019 1020 dma_mapped = controller->can_dma && 1021 controller->can_dma(controller, spi, transfer) && 1022 controller->cur_msg_mapped; 1023 if (dma_mapped) { 1024 1025 /* Ensure we have the correct interrupt handler */ 1026 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1027 1028 err = pxa2xx_spi_dma_prepare(drv_data, transfer); 1029 if (err) 1030 return err; 1031 1032 /* Clear status and start DMA engine */ 1033 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1034 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1035 1036 pxa2xx_spi_dma_start(drv_data); 1037 } else { 1038 /* Ensure we have the correct interrupt handler */ 1039 drv_data->transfer_handler = interrupt_transfer; 1040 1041 /* Clear status */ 1042 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1043 write_SSSR_CS(drv_data, drv_data->clear_sr); 1044 } 1045 1046 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1047 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1048 if (!pxa25x_ssp_comp(drv_data)) 1049 dev_dbg(&spi->dev, "%u Hz actual, %s\n", 1050 controller->max_speed_hz 1051 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1052 dma_mapped ? "DMA" : "PIO"); 1053 else 1054 dev_dbg(&spi->dev, "%u Hz actual, %s\n", 1055 controller->max_speed_hz / 2 1056 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1057 dma_mapped ? "DMA" : "PIO"); 1058 1059 if (is_lpss_ssp(drv_data)) { 1060 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); 1061 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); 1062 } 1063 1064 if (is_mrfld_ssp(drv_data)) { 1065 u32 mask = SFIFOTT_RFT | SFIFOTT_TFT; 1066 u32 thresh = 0; 1067 1068 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); 1069 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); 1070 1071 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh); 1072 } 1073 1074 if (is_quark_x1000_ssp(drv_data)) 1075 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); 1076 1077 /* Stop the SSP */ 1078 if (!is_mmp2_ssp(drv_data)) 1079 pxa_ssp_disable(drv_data->ssp); 1080 1081 if (!pxa25x_ssp_comp(drv_data)) 1082 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1083 1084 /* First set CR1 without interrupt and service enables */ 1085 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1); 1086 1087 /* See if we need to reload the configuration registers */ 1088 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0); 1089 1090 /* Restart the SSP */ 1091 pxa_ssp_enable(drv_data->ssp); 1092 1093 if (is_mmp2_ssp(drv_data)) { 1094 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8; 1095 1096 if (tx_level) { 1097 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ 1098 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); 1099 if (tx_level > transfer->len) 1100 tx_level = transfer->len; 1101 drv_data->tx += tx_level; 1102 } 1103 } 1104 1105 if (spi_controller_is_target(controller)) { 1106 while (drv_data->write(drv_data)) 1107 ; 1108 if (drv_data->gpiod_ready) { 1109 gpiod_set_value(drv_data->gpiod_ready, 1); 1110 udelay(1); 1111 gpiod_set_value(drv_data->gpiod_ready, 0); 1112 } 1113 } 1114 1115 /* 1116 * Release the data by enabling service requests and interrupts, 1117 * without changing any mode bits. 1118 */ 1119 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1120 1121 return 1; 1122} 1123 1124static int pxa2xx_spi_target_abort(struct spi_controller *controller) 1125{ 1126 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1127 1128 int_error_stop(drv_data, "transfer aborted", -EINTR); 1129 1130 return 0; 1131} 1132 1133static void pxa2xx_spi_handle_err(struct spi_controller *controller, 1134 struct spi_message *msg) 1135{ 1136 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1137 1138 int_stop_and_reset(drv_data); 1139 1140 /* Disable the SSP */ 1141 pxa2xx_spi_off(drv_data); 1142 1143 /* 1144 * Stop the DMA if running. Note DMA callback handler may have unset 1145 * the dma_running already, which is fine as stopping is not needed 1146 * then but we shouldn't rely this flag for anything else than 1147 * stopping. For instance to differentiate between PIO and DMA 1148 * transfers. 1149 */ 1150 if (atomic_read(&drv_data->dma_running)) 1151 pxa2xx_spi_dma_stop(drv_data); 1152} 1153 1154static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller) 1155{ 1156 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1157 1158 /* Disable the SSP now */ 1159 pxa2xx_spi_off(drv_data); 1160 1161 return 0; 1162} 1163 1164static int setup(struct spi_device *spi) 1165{ 1166 struct pxa2xx_spi_chip *chip_info; 1167 struct chip_data *chip; 1168 const struct lpss_config *config; 1169 struct driver_data *drv_data = 1170 spi_controller_get_devdata(spi->controller); 1171 uint tx_thres, tx_hi_thres, rx_thres; 1172 1173 switch (drv_data->ssp_type) { 1174 case QUARK_X1000_SSP: 1175 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1176 tx_hi_thres = 0; 1177 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1178 break; 1179 case MRFLD_SSP: 1180 tx_thres = TX_THRESH_MRFLD_DFLT; 1181 tx_hi_thres = 0; 1182 rx_thres = RX_THRESH_MRFLD_DFLT; 1183 break; 1184 case CE4100_SSP: 1185 tx_thres = TX_THRESH_CE4100_DFLT; 1186 tx_hi_thres = 0; 1187 rx_thres = RX_THRESH_CE4100_DFLT; 1188 break; 1189 case LPSS_LPT_SSP: 1190 case LPSS_BYT_SSP: 1191 case LPSS_BSW_SSP: 1192 case LPSS_SPT_SSP: 1193 case LPSS_BXT_SSP: 1194 case LPSS_CNL_SSP: 1195 config = lpss_get_config(drv_data); 1196 tx_thres = config->tx_threshold_lo; 1197 tx_hi_thres = config->tx_threshold_hi; 1198 rx_thres = config->rx_threshold; 1199 break; 1200 default: 1201 tx_hi_thres = 0; 1202 if (spi_controller_is_target(drv_data->controller)) { 1203 tx_thres = 1; 1204 rx_thres = 2; 1205 } else { 1206 tx_thres = TX_THRESH_DFLT; 1207 rx_thres = RX_THRESH_DFLT; 1208 } 1209 break; 1210 } 1211 1212 /* Only allocate on the first setup */ 1213 chip = spi_get_ctldata(spi); 1214 if (!chip) { 1215 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1216 if (!chip) 1217 return -ENOMEM; 1218 1219 if (drv_data->ssp_type == CE4100_SSP) { 1220 if (spi_get_chipselect(spi, 0) > 4) { 1221 dev_err(&spi->dev, 1222 "failed setup: cs number must not be > 4.\n"); 1223 kfree(chip); 1224 return -EINVAL; 1225 } 1226 } 1227 chip->enable_dma = drv_data->controller_info->enable_dma; 1228 chip->timeout = TIMOUT_DFLT; 1229 } 1230 1231 /* 1232 * Protocol drivers may change the chip settings, so... 1233 * if chip_info exists, use it. 1234 */ 1235 chip_info = spi->controller_data; 1236 1237 /* chip_info isn't always needed */ 1238 if (chip_info) { 1239 if (chip_info->timeout) 1240 chip->timeout = chip_info->timeout; 1241 if (chip_info->tx_threshold) 1242 tx_thres = chip_info->tx_threshold; 1243 if (chip_info->tx_hi_threshold) 1244 tx_hi_thres = chip_info->tx_hi_threshold; 1245 if (chip_info->rx_threshold) 1246 rx_thres = chip_info->rx_threshold; 1247 chip->dma_threshold = 0; 1248 } 1249 1250 chip->cr1 = 0; 1251 if (spi_controller_is_target(drv_data->controller)) { 1252 chip->cr1 |= SSCR1_SCFR; 1253 chip->cr1 |= SSCR1_SCLKDIR; 1254 chip->cr1 |= SSCR1_SFRMDIR; 1255 chip->cr1 |= SSCR1_SPH; 1256 } 1257 1258 if (is_lpss_ssp(drv_data)) { 1259 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1260 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | 1261 SSITF_TxHiThresh(tx_hi_thres); 1262 } 1263 1264 if (is_mrfld_ssp(drv_data)) { 1265 chip->lpss_rx_threshold = rx_thres; 1266 chip->lpss_tx_threshold = tx_thres; 1267 } 1268 1269 /* 1270 * Set DMA burst and threshold outside of chip_info path so that if 1271 * chip_info goes away after setting chip->enable_dma, the burst and 1272 * threshold can still respond to changes in bits_per_word. 1273 */ 1274 if (chip->enable_dma) { 1275 /* Set up legal burst and threshold for DMA */ 1276 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1277 spi->bits_per_word, 1278 &chip->dma_burst_size, 1279 &chip->dma_threshold)) { 1280 dev_warn(&spi->dev, 1281 "in setup: DMA burst size reduced to match bits_per_word\n"); 1282 } 1283 dev_dbg(&spi->dev, 1284 "in setup: DMA burst size set to %u\n", 1285 chip->dma_burst_size); 1286 } 1287 1288 switch (drv_data->ssp_type) { 1289 case QUARK_X1000_SSP: 1290 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1291 & QUARK_X1000_SSCR1_RFT) 1292 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1293 & QUARK_X1000_SSCR1_TFT); 1294 break; 1295 case CE4100_SSP: 1296 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1297 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1298 break; 1299 default: 1300 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1301 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1302 break; 1303 } 1304 1305 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1306 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | 1307 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); 1308 1309 if (spi->mode & SPI_LOOP) 1310 chip->cr1 |= SSCR1_LBM; 1311 1312 spi_set_ctldata(spi, chip); 1313 1314 return 0; 1315} 1316 1317static void cleanup(struct spi_device *spi) 1318{ 1319 struct chip_data *chip = spi_get_ctldata(spi); 1320 1321 kfree(chip); 1322} 1323 1324static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1325{ 1326 return param == chan->device->dev; 1327} 1328 1329static struct pxa2xx_spi_controller * 1330pxa2xx_spi_init_pdata(struct platform_device *pdev) 1331{ 1332 struct pxa2xx_spi_controller *pdata; 1333 struct device *dev = &pdev->dev; 1334 struct device *parent = dev->parent; 1335 struct ssp_device *ssp; 1336 struct resource *res; 1337 enum pxa_ssp_type type = SSP_UNDEFINED; 1338 const void *match; 1339 bool is_lpss_priv; 1340 int status; 1341 u64 uid; 1342 1343 is_lpss_priv = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpss_priv"); 1344 1345 match = device_get_match_data(dev); 1346 if (match) 1347 type = (uintptr_t)match; 1348 else if (is_lpss_priv) { 1349 u32 value; 1350 1351 status = device_property_read_u32(dev, "intel,spi-pxa2xx-type", &value); 1352 if (status) 1353 return ERR_PTR(status); 1354 1355 type = (enum pxa_ssp_type)value; 1356 } 1357 1358 /* Validate the SSP type correctness */ 1359 if (!(type > SSP_UNDEFINED && type < SSP_MAX)) 1360 return ERR_PTR(-EINVAL); 1361 1362 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1363 if (!pdata) 1364 return ERR_PTR(-ENOMEM); 1365 1366 ssp = &pdata->ssp; 1367 1368 ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1369 if (IS_ERR(ssp->mmio_base)) 1370 return ERR_CAST(ssp->mmio_base); 1371 1372 ssp->phys_base = res->start; 1373 1374 /* Platforms with iDMA 64-bit */ 1375 if (is_lpss_priv) { 1376 pdata->tx_param = parent; 1377 pdata->rx_param = parent; 1378 pdata->dma_filter = pxa2xx_spi_idma_filter; 1379 } 1380 1381 ssp->clk = devm_clk_get(dev, NULL); 1382 if (IS_ERR(ssp->clk)) 1383 return ERR_CAST(ssp->clk); 1384 1385 ssp->irq = platform_get_irq(pdev, 0); 1386 if (ssp->irq < 0) 1387 return ERR_PTR(ssp->irq); 1388 1389 ssp->type = type; 1390 ssp->dev = dev; 1391 1392 status = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &uid); 1393 if (status) 1394 ssp->port_id = -1; 1395 else 1396 ssp->port_id = uid; 1397 1398 pdata->is_target = device_property_read_bool(dev, "spi-slave"); 1399 pdata->num_chipselect = 1; 1400 pdata->enable_dma = true; 1401 pdata->dma_burst_size = 1; 1402 1403 return pdata; 1404} 1405 1406static int pxa2xx_spi_fw_translate_cs(struct spi_controller *controller, 1407 unsigned int cs) 1408{ 1409 struct driver_data *drv_data = spi_controller_get_devdata(controller); 1410 1411 if (has_acpi_companion(drv_data->ssp->dev)) { 1412 switch (drv_data->ssp_type) { 1413 /* 1414 * For Atoms the ACPI DeviceSelection used by the Windows 1415 * driver starts from 1 instead of 0 so translate it here 1416 * to match what Linux expects. 1417 */ 1418 case LPSS_BYT_SSP: 1419 case LPSS_BSW_SSP: 1420 return cs - 1; 1421 1422 default: 1423 break; 1424 } 1425 } 1426 1427 return cs; 1428} 1429 1430static size_t pxa2xx_spi_max_dma_transfer_size(struct spi_device *spi) 1431{ 1432 return MAX_DMA_LEN; 1433} 1434 1435static int pxa2xx_spi_probe(struct platform_device *pdev) 1436{ 1437 struct device *dev = &pdev->dev; 1438 struct pxa2xx_spi_controller *platform_info; 1439 struct spi_controller *controller; 1440 struct driver_data *drv_data; 1441 struct ssp_device *ssp; 1442 const struct lpss_config *config; 1443 int status; 1444 u32 tmp; 1445 1446 platform_info = dev_get_platdata(dev); 1447 if (!platform_info) { 1448 platform_info = pxa2xx_spi_init_pdata(pdev); 1449 if (IS_ERR(platform_info)) { 1450 dev_err(&pdev->dev, "missing platform data\n"); 1451 return PTR_ERR(platform_info); 1452 } 1453 } 1454 1455 ssp = pxa_ssp_request(pdev->id, pdev->name); 1456 if (!ssp) 1457 ssp = &platform_info->ssp; 1458 1459 if (!ssp->mmio_base) { 1460 dev_err(&pdev->dev, "failed to get SSP\n"); 1461 return -ENODEV; 1462 } 1463 1464 if (platform_info->is_target) 1465 controller = devm_spi_alloc_target(dev, sizeof(*drv_data)); 1466 else 1467 controller = devm_spi_alloc_host(dev, sizeof(*drv_data)); 1468 1469 if (!controller) { 1470 dev_err(&pdev->dev, "cannot alloc spi_controller\n"); 1471 status = -ENOMEM; 1472 goto out_error_controller_alloc; 1473 } 1474 drv_data = spi_controller_get_devdata(controller); 1475 drv_data->controller = controller; 1476 drv_data->controller_info = platform_info; 1477 drv_data->ssp = ssp; 1478 1479 device_set_node(&controller->dev, dev_fwnode(dev)); 1480 1481 /* The spi->mode bits understood by this driver: */ 1482 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1483 1484 controller->bus_num = ssp->port_id; 1485 controller->dma_alignment = DMA_ALIGNMENT; 1486 controller->cleanup = cleanup; 1487 controller->setup = setup; 1488 controller->set_cs = pxa2xx_spi_set_cs; 1489 controller->transfer_one = pxa2xx_spi_transfer_one; 1490 controller->target_abort = pxa2xx_spi_target_abort; 1491 controller->handle_err = pxa2xx_spi_handle_err; 1492 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1493 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1494 controller->auto_runtime_pm = true; 1495 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 1496 1497 drv_data->ssp_type = ssp->type; 1498 1499 if (pxa25x_ssp_comp(drv_data)) { 1500 switch (drv_data->ssp_type) { 1501 case QUARK_X1000_SSP: 1502 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1503 break; 1504 default: 1505 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1506 break; 1507 } 1508 1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1510 drv_data->dma_cr1 = 0; 1511 drv_data->clear_sr = SSSR_ROR; 1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1513 } else { 1514 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1516 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS 1519 | SSSR_ROR | SSSR_TUR; 1520 } 1521 1522 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1523 drv_data); 1524 if (status < 0) { 1525 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1526 goto out_error_controller_alloc; 1527 } 1528 1529 /* Setup DMA if requested */ 1530 if (platform_info->enable_dma) { 1531 status = pxa2xx_spi_dma_setup(drv_data); 1532 if (status) { 1533 dev_warn(dev, "no DMA channels available, using PIO\n"); 1534 platform_info->enable_dma = false; 1535 } else { 1536 controller->can_dma = pxa2xx_spi_can_dma; 1537 controller->max_dma_len = MAX_DMA_LEN; 1538 controller->max_transfer_size = 1539 pxa2xx_spi_max_dma_transfer_size; 1540 } 1541 } 1542 1543 /* Enable SOC clock */ 1544 status = clk_prepare_enable(ssp->clk); 1545 if (status) 1546 goto out_error_dma_irq_alloc; 1547 1548 controller->max_speed_hz = clk_get_rate(ssp->clk); 1549 /* 1550 * Set minimum speed for all other platforms than Intel Quark which is 1551 * able do under 1 Hz transfers. 1552 */ 1553 if (!pxa25x_ssp_comp(drv_data)) 1554 controller->min_speed_hz = 1555 DIV_ROUND_UP(controller->max_speed_hz, 4096); 1556 else if (!is_quark_x1000_ssp(drv_data)) 1557 controller->min_speed_hz = 1558 DIV_ROUND_UP(controller->max_speed_hz, 512); 1559 1560 pxa_ssp_disable(ssp); 1561 1562 /* Load default SSP configuration */ 1563 switch (drv_data->ssp_type) { 1564 case QUARK_X1000_SSP: 1565 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1566 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1567 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1568 1569 /* Using the Motorola SPI protocol and use 8 bit frame */ 1570 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1571 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1572 break; 1573 case CE4100_SSP: 1574 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1575 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1576 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1577 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1578 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1579 break; 1580 default: 1581 1582 if (spi_controller_is_target(controller)) { 1583 tmp = SSCR1_SCFR | 1584 SSCR1_SCLKDIR | 1585 SSCR1_SFRMDIR | 1586 SSCR1_RxTresh(2) | 1587 SSCR1_TxTresh(1) | 1588 SSCR1_SPH; 1589 } else { 1590 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1591 SSCR1_TxTresh(TX_THRESH_DFLT); 1592 } 1593 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1594 tmp = SSCR0_Motorola | SSCR0_DataSize(8); 1595 if (!spi_controller_is_target(controller)) 1596 tmp |= SSCR0_SCR(2); 1597 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1598 break; 1599 } 1600 1601 if (!pxa25x_ssp_comp(drv_data)) 1602 pxa2xx_spi_write(drv_data, SSTO, 0); 1603 1604 if (!is_quark_x1000_ssp(drv_data)) 1605 pxa2xx_spi_write(drv_data, SSPSP, 0); 1606 1607 if (is_lpss_ssp(drv_data)) { 1608 lpss_ssp_setup(drv_data); 1609 config = lpss_get_config(drv_data); 1610 if (config->reg_capabilities >= 0) { 1611 tmp = __lpss_ssp_read_priv(drv_data, 1612 config->reg_capabilities); 1613 tmp &= LPSS_CAPS_CS_EN_MASK; 1614 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1615 platform_info->num_chipselect = ffz(tmp); 1616 } else if (config->cs_num) { 1617 platform_info->num_chipselect = config->cs_num; 1618 } 1619 } 1620 controller->num_chipselect = platform_info->num_chipselect; 1621 controller->use_gpio_descriptors = true; 1622 1623 if (platform_info->is_target) { 1624 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, 1625 "ready", GPIOD_OUT_LOW); 1626 if (IS_ERR(drv_data->gpiod_ready)) { 1627 status = PTR_ERR(drv_data->gpiod_ready); 1628 goto out_error_clock_enabled; 1629 } 1630 } 1631 1632 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1633 pm_runtime_use_autosuspend(&pdev->dev); 1634 pm_runtime_set_active(&pdev->dev); 1635 pm_runtime_enable(&pdev->dev); 1636 1637 /* Register with the SPI framework */ 1638 platform_set_drvdata(pdev, drv_data); 1639 status = spi_register_controller(controller); 1640 if (status) { 1641 dev_err(&pdev->dev, "problem registering SPI controller\n"); 1642 goto out_error_pm_runtime_enabled; 1643 } 1644 1645 return status; 1646 1647out_error_pm_runtime_enabled: 1648 pm_runtime_disable(&pdev->dev); 1649 1650out_error_clock_enabled: 1651 clk_disable_unprepare(ssp->clk); 1652 1653out_error_dma_irq_alloc: 1654 pxa2xx_spi_dma_release(drv_data); 1655 free_irq(ssp->irq, drv_data); 1656 1657out_error_controller_alloc: 1658 pxa_ssp_free(ssp); 1659 return status; 1660} 1661 1662static void pxa2xx_spi_remove(struct platform_device *pdev) 1663{ 1664 struct driver_data *drv_data = platform_get_drvdata(pdev); 1665 struct ssp_device *ssp = drv_data->ssp; 1666 1667 pm_runtime_get_sync(&pdev->dev); 1668 1669 spi_unregister_controller(drv_data->controller); 1670 1671 /* Disable the SSP at the peripheral and SOC level */ 1672 pxa_ssp_disable(ssp); 1673 clk_disable_unprepare(ssp->clk); 1674 1675 /* Release DMA */ 1676 if (drv_data->controller_info->enable_dma) 1677 pxa2xx_spi_dma_release(drv_data); 1678 1679 pm_runtime_put_noidle(&pdev->dev); 1680 pm_runtime_disable(&pdev->dev); 1681 1682 /* Release IRQ */ 1683 free_irq(ssp->irq, drv_data); 1684 1685 /* Release SSP */ 1686 pxa_ssp_free(ssp); 1687} 1688 1689static int pxa2xx_spi_suspend(struct device *dev) 1690{ 1691 struct driver_data *drv_data = dev_get_drvdata(dev); 1692 struct ssp_device *ssp = drv_data->ssp; 1693 int status; 1694 1695 status = spi_controller_suspend(drv_data->controller); 1696 if (status) 1697 return status; 1698 1699 pxa_ssp_disable(ssp); 1700 1701 if (!pm_runtime_suspended(dev)) 1702 clk_disable_unprepare(ssp->clk); 1703 1704 return 0; 1705} 1706 1707static int pxa2xx_spi_resume(struct device *dev) 1708{ 1709 struct driver_data *drv_data = dev_get_drvdata(dev); 1710 struct ssp_device *ssp = drv_data->ssp; 1711 int status; 1712 1713 /* Enable the SSP clock */ 1714 if (!pm_runtime_suspended(dev)) { 1715 status = clk_prepare_enable(ssp->clk); 1716 if (status) 1717 return status; 1718 } 1719 1720 /* Start the queue running */ 1721 return spi_controller_resume(drv_data->controller); 1722} 1723 1724static int pxa2xx_spi_runtime_suspend(struct device *dev) 1725{ 1726 struct driver_data *drv_data = dev_get_drvdata(dev); 1727 1728 clk_disable_unprepare(drv_data->ssp->clk); 1729 return 0; 1730} 1731 1732static int pxa2xx_spi_runtime_resume(struct device *dev) 1733{ 1734 struct driver_data *drv_data = dev_get_drvdata(dev); 1735 1736 return clk_prepare_enable(drv_data->ssp->clk); 1737} 1738 1739static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1740 SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1741 RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, pxa2xx_spi_runtime_resume, NULL) 1742}; 1743 1744#ifdef CONFIG_ACPI 1745static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1746 { "80860F0E", LPSS_BYT_SSP }, 1747 { "8086228E", LPSS_BSW_SSP }, 1748 { "INT33C0", LPSS_LPT_SSP }, 1749 { "INT33C1", LPSS_LPT_SSP }, 1750 { "INT3430", LPSS_LPT_SSP }, 1751 { "INT3431", LPSS_LPT_SSP }, 1752 {} 1753}; 1754MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1755#endif 1756 1757static const struct of_device_id pxa2xx_spi_of_match[] __maybe_unused = { 1758 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP }, 1759 {} 1760}; 1761MODULE_DEVICE_TABLE(of, pxa2xx_spi_of_match); 1762 1763static struct platform_driver driver = { 1764 .driver = { 1765 .name = "pxa2xx-spi", 1766 .pm = pm_ptr(&pxa2xx_spi_pm_ops), 1767 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1768 .of_match_table = of_match_ptr(pxa2xx_spi_of_match), 1769 }, 1770 .probe = pxa2xx_spi_probe, 1771 .remove_new = pxa2xx_spi_remove, 1772}; 1773 1774static int __init pxa2xx_spi_init(void) 1775{ 1776 return platform_driver_register(&driver); 1777} 1778subsys_initcall(pxa2xx_spi_init); 1779 1780static void __exit pxa2xx_spi_exit(void) 1781{ 1782 platform_driver_unregister(&driver); 1783} 1784module_exit(pxa2xx_spi_exit); 1785 1786MODULE_SOFTDEP("pre: dw_dmac"); 1787