Searched refs:channels_mask (Results 1 - 25 of 47) sorted by last modified time

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/linux-master/include/linux/
H A Dfirewire.h537 u64 channels_mask, int *channel, int *bandwidth,
/linux-master/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7757.c88 .channels_mask = 3,
H A Dsetup-sh7786.c170 .channels_mask = 7,
191 .channels_mask = 7,
212 .channels_mask = 7,
233 .channels_mask = 7,
H A Dsetup-sh7724.c635 .channels_mask = 0x20,
654 .channels_mask = 7,
675 .channels_mask = 7,
H A Dsetup-sh7723.c234 .channels_mask = 0x20,
253 .channels_mask = 7,
274 .channels_mask = 7,
H A Dsetup-shx3.c98 .channels_mask = 7,
119 .channels_mask = 7,
/linux-master/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_kms.c319 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
H A Drzg2l_du_drv.c29 .channels_mask = BIT(0),
H A Drzg2l_du_drv.h45 * @channels_mask: bit mask of available DU channels
49 unsigned int channels_mask; member in struct:rzg2l_du_device_info
/linux-master/drivers/dma/ti/
H A Dedma.c259 unsigned long *channels_mask; member in struct:edma_cc
674 if (!test_bit(echan->ch_num, ecc->channels_mask)) {
2363 ecc->channels_mask = devm_kcalloc(dev,
2366 if (!ecc->slave_chans || !ecc->slot_inuse || !ecc->channels_mask) {
2372 bitmap_fill(ecc->channels_mask, ecc->num_channels);
2389 bitmap_clear(ecc->channels_mask, reserved[i][0],
2482 (u32 *)ecc->channels_mask,
2507 if (!test_bit(i, ecc->channels_mask))
/linux-master/drivers/iio/adc/
H A Dat91_adc.c217 unsigned long channels_mask; member in struct:at91_adc_state
498 st->channels_mask &= ~rsvd_mask;
500 idev->num_channels = bitmap_weight(&st->channels_mask,
511 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
1019 st->channels_mask = prop;
/linux-master/drivers/dma/sh/
H A Drcar-dmac.c196 * @channels_mask: bitfield of which DMA channels are managed by this driver
207 u32 channels_mask; member in struct:rcar_dmac
216 if (!((dmac)->channels_mask & BIT(i))) continue; else
362 rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
1838 dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);
1839 of_property_read_u32(np, "dma-channel-mask", &dmac->channels_mask);
1842 dmac->channels_mask &= GENMASK(dmac->n_channels - 1, 0);
1892 dmac->channels_mask &= ~BIT(0);
/linux-master/drivers/dma/lgm/
H A Dlgm-dma.c257 u32 channels_mask; member in struct:ldma_dev
894 unsigned long ch_mask = (unsigned long)d->channels_mask;
1636 ret = device_property_read_u32(dev, "dma-channel-mask", &d->channels_mask);
1638 d->channels_mask = GENMASK(d->chan_nrs - 1, 0);
1666 ch_mask = (unsigned long)d->channels_mask;
/linux-master/drivers/net/can/rcar/
H A Drcar_canfd.c549 unsigned long channels_mask; /* Enabled channels mask */ member in struct:rcar_canfd_global
696 for_each_set_bit(ch, &gpriv->channels_mask,
745 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
786 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1166 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1198 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1212 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1308 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1857 unsigned long channels_mask = 0; local
1873 channels_mask |
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/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_kms.c881 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
907 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
909 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
946 if (!(rcdu->info->channels_mask & BIT(hwindex)))
H A Drcar_du_drv.c41 .channels_mask = BIT(1) | BIT(0),
65 .channels_mask = BIT(1) | BIT(0),
88 .channels_mask = BIT(1) | BIT(0),
117 .channels_mask = BIT(2) | BIT(1) | BIT(0),
148 .channels_mask = BIT(3) | BIT(1) | BIT(0),
177 .channels_mask = BIT(1) | BIT(0),
207 .channels_mask = BIT(3) | BIT(1) | BIT(0),
235 .channels_mask = BIT(1) | BIT(0),
259 .channels_mask = BIT(2) | BIT(1) | BIT(0),
290 .channels_mask
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H A Drcar_du_group.c47 if (rgrp->channels_mask & BIT(0))
50 if (rgrp->channels_mask & BIT(1))
239 if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) {
H A Drcar_du_group.h24 * @channels_mask: bitmask of populated DU channels in this group
40 unsigned int channels_mask; member in struct:rcar_du_group
H A Drcar_du_drv.h70 * @channels_mask: bit mask of available DU channels
82 unsigned int channels_mask; member in struct:rcar_du_device_info
/linux-master/drivers/clocksource/
H A Dsh_cmt.c74 unsigned int channels_mask; member in struct:sh_cmt_info
202 .channels_mask = 0x3f,
213 .channels_mask = 0x60,
224 .channels_mask = 0xff,
1022 cmt->hw_channels = cmt->info->channels_mask;
1028 cmt->hw_channels = cfg->channels_mask;
H A Dsh_tmu.c532 tmu->num_channels = hweight8(cfg->channels_mask);
/linux-master/sound/firewire/fireface/
H A Dff-protocol-latter.c230 ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
238 ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
H A Dff-protocol-former.c468 ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
476 ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
/linux-master/sound/firewire/dice/
H A Ddice-stream.c506 resources->channels_mask = 0x00000000ffffffffuLL;
/linux-master/drivers/firewire/
H A Dcore-iso.c243 u32 channels_mask, u64 offset, bool allocate)
252 if (!(channels_mask & 1 << channel))
311 * @channels_mask: bitmask for channel allocation
316 * In parameters: card, generation, channels_mask, bandwidth, allocate
321 * Allocates or deallocates at most one channel out of channels_mask.
322 * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0.
339 u64 channels_mask, int *channel, int *bandwidth,
342 u32 channels_hi = channels_mask; /* channels 31...0 */
343 u32 channels_lo = channels_mask >> 32; /* channels 63...32 */
363 if (allocate && channels_mask !
242 manage_channel(struct fw_card *card, int irm_id, int generation, u32 channels_mask, u64 offset, bool allocate) argument
338 fw_iso_resource_manage(struct fw_card *card, int generation, u64 channels_mask, int *channel, int *bandwidth, bool allocate) argument
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