1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SH7786 Setup 4 * 5 * Copyright (C) 2009 - 2011 Renesas Solutions Corp. 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * Paul Mundt <paul.mundt@renesas.com> 8 * 9 * Based on SH7785 Setup 10 * 11 * Copyright (C) 2007 Paul Mundt 12 */ 13#include <linux/platform_device.h> 14#include <linux/init.h> 15#include <linux/serial.h> 16#include <linux/serial_sci.h> 17#include <linux/io.h> 18#include <linux/mm.h> 19#include <linux/dma-mapping.h> 20#include <linux/sh_timer.h> 21#include <linux/sh_dma.h> 22#include <linux/sh_intc.h> 23#include <linux/usb/ohci_pdriver.h> 24#include <cpu/dma-register.h> 25#include <asm/mmzone.h> 26#include <asm/platform_early.h> 27 28static struct plat_sci_port scif0_platform_data = { 29 .scscr = SCSCR_REIE | SCSCR_CKE1, 30 .type = PORT_SCIF, 31 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 32}; 33 34static struct resource scif0_resources[] = { 35 DEFINE_RES_MEM(0xffea0000, 0x100), 36 DEFINE_RES_IRQ(evt2irq(0x700)), 37 DEFINE_RES_IRQ(evt2irq(0x720)), 38 DEFINE_RES_IRQ(evt2irq(0x760)), 39 DEFINE_RES_IRQ(evt2irq(0x740)), 40}; 41 42static struct platform_device scif0_device = { 43 .name = "sh-sci", 44 .id = 0, 45 .resource = scif0_resources, 46 .num_resources = ARRAY_SIZE(scif0_resources), 47 .dev = { 48 .platform_data = &scif0_platform_data, 49 }, 50}; 51 52/* 53 * The rest of these all have multiplexed IRQs 54 */ 55static struct plat_sci_port scif1_platform_data = { 56 .scscr = SCSCR_REIE | SCSCR_CKE1, 57 .type = PORT_SCIF, 58 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 59}; 60 61static struct resource scif1_resources[] = { 62 DEFINE_RES_MEM(0xffeb0000, 0x100), 63 DEFINE_RES_IRQ(evt2irq(0x780)), 64}; 65 66static struct resource scif1_demux_resources[] = { 67 DEFINE_RES_MEM(0xffeb0000, 0x100), 68 /* Placeholders, see sh7786_devices_setup() */ 69 DEFINE_RES_IRQ(0), 70 DEFINE_RES_IRQ(0), 71 DEFINE_RES_IRQ(0), 72 DEFINE_RES_IRQ(0), 73}; 74 75static struct platform_device scif1_device = { 76 .name = "sh-sci", 77 .id = 1, 78 .resource = scif1_resources, 79 .num_resources = ARRAY_SIZE(scif1_resources), 80 .dev = { 81 .platform_data = &scif1_platform_data, 82 }, 83}; 84 85static struct plat_sci_port scif2_platform_data = { 86 .scscr = SCSCR_REIE | SCSCR_CKE1, 87 .type = PORT_SCIF, 88 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 89}; 90 91static struct resource scif2_resources[] = { 92 DEFINE_RES_MEM(0xffec0000, 0x100), 93 DEFINE_RES_IRQ(evt2irq(0x840)), 94}; 95 96static struct platform_device scif2_device = { 97 .name = "sh-sci", 98 .id = 2, 99 .resource = scif2_resources, 100 .num_resources = ARRAY_SIZE(scif2_resources), 101 .dev = { 102 .platform_data = &scif2_platform_data, 103 }, 104}; 105 106static struct plat_sci_port scif3_platform_data = { 107 .scscr = SCSCR_REIE | SCSCR_CKE1, 108 .type = PORT_SCIF, 109 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 110}; 111 112static struct resource scif3_resources[] = { 113 DEFINE_RES_MEM(0xffed0000, 0x100), 114 DEFINE_RES_IRQ(evt2irq(0x860)), 115}; 116 117static struct platform_device scif3_device = { 118 .name = "sh-sci", 119 .id = 3, 120 .resource = scif3_resources, 121 .num_resources = ARRAY_SIZE(scif3_resources), 122 .dev = { 123 .platform_data = &scif3_platform_data, 124 }, 125}; 126 127static struct plat_sci_port scif4_platform_data = { 128 .scscr = SCSCR_REIE | SCSCR_CKE1, 129 .type = PORT_SCIF, 130 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 131}; 132 133static struct resource scif4_resources[] = { 134 DEFINE_RES_MEM(0xffee0000, 0x100), 135 DEFINE_RES_IRQ(evt2irq(0x880)), 136}; 137 138static struct platform_device scif4_device = { 139 .name = "sh-sci", 140 .id = 4, 141 .resource = scif4_resources, 142 .num_resources = ARRAY_SIZE(scif4_resources), 143 .dev = { 144 .platform_data = &scif4_platform_data, 145 }, 146}; 147 148static struct plat_sci_port scif5_platform_data = { 149 .scscr = SCSCR_REIE | SCSCR_CKE1, 150 .type = PORT_SCIF, 151 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 152}; 153 154static struct resource scif5_resources[] = { 155 DEFINE_RES_MEM(0xffef0000, 0x100), 156 DEFINE_RES_IRQ(evt2irq(0x8a0)), 157}; 158 159static struct platform_device scif5_device = { 160 .name = "sh-sci", 161 .id = 5, 162 .resource = scif5_resources, 163 .num_resources = ARRAY_SIZE(scif5_resources), 164 .dev = { 165 .platform_data = &scif5_platform_data, 166 }, 167}; 168 169static struct sh_timer_config tmu0_platform_data = { 170 .channels_mask = 7, 171}; 172 173static struct resource tmu0_resources[] = { 174 DEFINE_RES_MEM(0xffd80000, 0x30), 175 DEFINE_RES_IRQ(evt2irq(0x400)), 176 DEFINE_RES_IRQ(evt2irq(0x420)), 177 DEFINE_RES_IRQ(evt2irq(0x440)), 178}; 179 180static struct platform_device tmu0_device = { 181 .name = "sh-tmu", 182 .id = 0, 183 .dev = { 184 .platform_data = &tmu0_platform_data, 185 }, 186 .resource = tmu0_resources, 187 .num_resources = ARRAY_SIZE(tmu0_resources), 188}; 189 190static struct sh_timer_config tmu1_platform_data = { 191 .channels_mask = 7, 192}; 193 194static struct resource tmu1_resources[] = { 195 DEFINE_RES_MEM(0xffda0000, 0x2c), 196 DEFINE_RES_IRQ(evt2irq(0x480)), 197 DEFINE_RES_IRQ(evt2irq(0x4a0)), 198 DEFINE_RES_IRQ(evt2irq(0x4c0)), 199}; 200 201static struct platform_device tmu1_device = { 202 .name = "sh-tmu", 203 .id = 1, 204 .dev = { 205 .platform_data = &tmu1_platform_data, 206 }, 207 .resource = tmu1_resources, 208 .num_resources = ARRAY_SIZE(tmu1_resources), 209}; 210 211static struct sh_timer_config tmu2_platform_data = { 212 .channels_mask = 7, 213}; 214 215static struct resource tmu2_resources[] = { 216 DEFINE_RES_MEM(0xffdc0000, 0x2c), 217 DEFINE_RES_IRQ(evt2irq(0x7a0)), 218 DEFINE_RES_IRQ(evt2irq(0x7a0)), 219 DEFINE_RES_IRQ(evt2irq(0x7a0)), 220}; 221 222static struct platform_device tmu2_device = { 223 .name = "sh-tmu", 224 .id = 2, 225 .dev = { 226 .platform_data = &tmu2_platform_data, 227 }, 228 .resource = tmu2_resources, 229 .num_resources = ARRAY_SIZE(tmu2_resources), 230}; 231 232static struct sh_timer_config tmu3_platform_data = { 233 .channels_mask = 7, 234}; 235 236static struct resource tmu3_resources[] = { 237 DEFINE_RES_MEM(0xffde0000, 0x2c), 238 DEFINE_RES_IRQ(evt2irq(0x7c0)), 239 DEFINE_RES_IRQ(evt2irq(0x7c0)), 240 DEFINE_RES_IRQ(evt2irq(0x7c0)), 241}; 242 243static struct platform_device tmu3_device = { 244 .name = "sh-tmu", 245 .id = 3, 246 .dev = { 247 .platform_data = &tmu3_platform_data, 248 }, 249 .resource = tmu3_resources, 250 .num_resources = ARRAY_SIZE(tmu3_resources), 251}; 252 253static const struct sh_dmae_channel dmac0_channels[] = { 254 { 255 .offset = 0, 256 .dmars = 0, 257 .dmars_bit = 0, 258 }, { 259 .offset = 0x10, 260 .dmars = 0, 261 .dmars_bit = 8, 262 }, { 263 .offset = 0x20, 264 .dmars = 4, 265 .dmars_bit = 0, 266 }, { 267 .offset = 0x30, 268 .dmars = 4, 269 .dmars_bit = 8, 270 }, { 271 .offset = 0x50, 272 .dmars = 8, 273 .dmars_bit = 0, 274 }, { 275 .offset = 0x60, 276 .dmars = 8, 277 .dmars_bit = 8, 278 } 279}; 280 281static const unsigned int ts_shift[] = TS_SHIFT; 282 283static struct sh_dmae_pdata dma0_platform_data = { 284 .channel = dmac0_channels, 285 .channel_num = ARRAY_SIZE(dmac0_channels), 286 .ts_low_shift = CHCR_TS_LOW_SHIFT, 287 .ts_low_mask = CHCR_TS_LOW_MASK, 288 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 289 .ts_high_mask = CHCR_TS_HIGH_MASK, 290 .ts_shift = ts_shift, 291 .ts_shift_num = ARRAY_SIZE(ts_shift), 292 .dmaor_init = DMAOR_INIT, 293}; 294 295/* Resource order important! */ 296static struct resource dmac0_resources[] = { 297 { 298 /* Channel registers and DMAOR */ 299 .start = 0xfe008020, 300 .end = 0xfe00808f, 301 .flags = IORESOURCE_MEM, 302 }, { 303 /* DMARSx */ 304 .start = 0xfe009000, 305 .end = 0xfe00900b, 306 .flags = IORESOURCE_MEM, 307 }, { 308 .name = "error_irq", 309 .start = evt2irq(0x5c0), 310 .end = evt2irq(0x5c0), 311 .flags = IORESOURCE_IRQ, 312 }, { 313 /* IRQ for channels 0-5 */ 314 .start = evt2irq(0x500), 315 .end = evt2irq(0x5a0), 316 .flags = IORESOURCE_IRQ, 317 }, 318}; 319 320static struct platform_device dma0_device = { 321 .name = "sh-dma-engine", 322 .id = 0, 323 .resource = dmac0_resources, 324 .num_resources = ARRAY_SIZE(dmac0_resources), 325 .dev = { 326 .platform_data = &dma0_platform_data, 327 }, 328}; 329 330#define USB_EHCI_START 0xffe70000 331#define USB_OHCI_START 0xffe70400 332 333static struct resource usb_ehci_resources[] = { 334 [0] = { 335 .start = USB_EHCI_START, 336 .end = USB_EHCI_START + 0x3ff, 337 .flags = IORESOURCE_MEM, 338 }, 339 [1] = { 340 .start = evt2irq(0xba0), 341 .end = evt2irq(0xba0), 342 .flags = IORESOURCE_IRQ, 343 }, 344}; 345 346static struct platform_device usb_ehci_device = { 347 .name = "sh_ehci", 348 .id = -1, 349 .dev = { 350 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask, 351 .coherent_dma_mask = DMA_BIT_MASK(32), 352 }, 353 .num_resources = ARRAY_SIZE(usb_ehci_resources), 354 .resource = usb_ehci_resources, 355}; 356 357static struct resource usb_ohci_resources[] = { 358 [0] = { 359 .start = USB_OHCI_START, 360 .end = USB_OHCI_START + 0x3ff, 361 .flags = IORESOURCE_MEM, 362 }, 363 [1] = { 364 .start = evt2irq(0xba0), 365 .end = evt2irq(0xba0), 366 .flags = IORESOURCE_IRQ, 367 }, 368}; 369 370static struct usb_ohci_pdata usb_ohci_pdata; 371 372static struct platform_device usb_ohci_device = { 373 .name = "ohci-platform", 374 .id = -1, 375 .dev = { 376 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask, 377 .coherent_dma_mask = DMA_BIT_MASK(32), 378 .platform_data = &usb_ohci_pdata, 379 }, 380 .num_resources = ARRAY_SIZE(usb_ohci_resources), 381 .resource = usb_ohci_resources, 382}; 383 384static struct platform_device *sh7786_early_devices[] __initdata = { 385 &scif0_device, 386 &scif1_device, 387 &scif2_device, 388 &scif3_device, 389 &scif4_device, 390 &scif5_device, 391 &tmu0_device, 392 &tmu1_device, 393 &tmu2_device, 394 &tmu3_device, 395}; 396 397static struct platform_device *sh7786_devices[] __initdata = { 398 &dma0_device, 399 &usb_ehci_device, 400 &usb_ohci_device, 401}; 402 403/* 404 * Please call this function if your platform board 405 * use external clock for USB 406 * */ 407#define USBCTL0 0xffe70858 408#define CLOCK_MODE_MASK 0xffffff7f 409#define EXT_CLOCK_MODE 0x00000080 410 411void __init sh7786_usb_use_exclock(void) 412{ 413 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; 414 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0); 415} 416 417#define USBINITREG1 0xffe70094 418#define USBINITREG2 0xffe7009c 419#define USBINITVAL1 0x00ff0040 420#define USBINITVAL2 0x00000001 421 422#define USBPCTL1 0xffe70804 423#define USBST 0xffe70808 424#define PHY_ENB 0x00000001 425#define PLL_ENB 0x00000002 426#define PHY_RST 0x00000004 427#define ACT_PLL_STATUS 0xc0000000 428 429static void __init sh7786_usb_setup(void) 430{ 431 int i = 1000000; 432 433 /* 434 * USB initial settings 435 * 436 * The following settings are necessary 437 * for using the USB modules. 438 * 439 * see "USB Initial Settings" for detail 440 */ 441 __raw_writel(USBINITVAL1, USBINITREG1); 442 __raw_writel(USBINITVAL2, USBINITREG2); 443 444 /* 445 * Set the PHY and PLL enable bit 446 */ 447 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1); 448 while (i--) { 449 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) { 450 /* Set the PHY RST bit */ 451 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1); 452 printk(KERN_INFO "sh7786 usb setup done\n"); 453 break; 454 } 455 cpu_relax(); 456 } 457} 458 459enum { 460 UNUSED = 0, 461 462 /* interrupt sources */ 463 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 464 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 465 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 466 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 467 468 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 469 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 470 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 471 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 472 473 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 474 WDT, 475 TMU0_0, TMU0_1, TMU0_2, TMU0_3, 476 TMU1_0, TMU1_1, TMU1_2, 477 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, 478 HUDI1, HUDI0, 479 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3, 480 HPB_0, HPB_1, HPB_2, 481 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, 482 SCIF1, 483 TMU2, TMU3, 484 SCIF2, SCIF3, SCIF4, SCIF5, 485 Eth_0, Eth_1, 486 PCIeC0_0, PCIeC0_1, PCIeC0_2, 487 PCIeC1_0, PCIeC1_1, PCIeC1_2, 488 USB, 489 I2C0, I2C1, 490 DU, 491 SSI0, SSI1, SSI2, SSI3, 492 PCIeC2_0, PCIeC2_1, PCIeC2_2, 493 HAC0, HAC1, 494 FLCTL, 495 HSPI, 496 GPIO0, GPIO1, 497 Thermal, 498 INTICI0, INTICI1, INTICI2, INTICI3, 499 INTICI4, INTICI5, INTICI6, INTICI7, 500 501 /* Muxed sub-events */ 502 TXI1, BRI1, RXI1, ERI1, 503}; 504 505static struct intc_vect sh7786_vectors[] __initdata = { 506 INTC_VECT(WDT, 0x3e0), 507 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420), 508 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460), 509 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0), 510 INTC_VECT(TMU1_2, 0x4c0), 511 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520), 512 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560), 513 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0), 514 INTC_VECT(DMAC0_6, 0x5c0), 515 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600), 516 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640), 517 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680), 518 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0), 519 INTC_VECT(HPB_2, 0x6e0), 520 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720), 521 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760), 522 INTC_VECT(SCIF1, 0x780), 523 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0), 524 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860), 525 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0), 526 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0), 527 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00), 528 INTC_VECT(PCIeC0_2, 0xb20), 529 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60), 530 INTC_VECT(PCIeC1_2, 0xb80), 531 INTC_VECT(USB, 0xba0), 532 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0), 533 INTC_VECT(DU, 0xd00), 534 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40), 535 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80), 536 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0), 537 INTC_VECT(PCIeC2_2, 0xde0), 538 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20), 539 INTC_VECT(FLCTL, 0xe40), 540 INTC_VECT(HSPI, 0xe80), 541 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0), 542 INTC_VECT(Thermal, 0xee0), 543 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20), 544 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60), 545 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0), 546 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), 547}; 548 549#define CnINTMSK0 0xfe410030 550#define CnINTMSK1 0xfe410040 551#define CnINTMSKCLR0 0xfe410050 552#define CnINTMSKCLR1 0xfe410060 553#define CnINT2MSKR0 0xfe410a20 554#define CnINT2MSKR1 0xfe410a24 555#define CnINT2MSKR2 0xfe410a28 556#define CnINT2MSKR3 0xfe410a2c 557#define CnINT2MSKCR0 0xfe410a30 558#define CnINT2MSKCR1 0xfe410a34 559#define CnINT2MSKCR2 0xfe410a38 560#define CnINT2MSKCR3 0xfe410a3c 561#define INTMSK2 0xfe410068 562#define INTMSKCLR2 0xfe41006c 563 564#define INTDISTCR0 0xfe4100b0 565#define INTDISTCR1 0xfe4100b4 566#define INT2DISTCR0 0xfe410900 567#define INT2DISTCR1 0xfe410904 568#define INT2DISTCR2 0xfe410908 569#define INT2DISTCR3 0xfe41090c 570 571static struct intc_mask_reg sh7786_mask_registers[] __initdata = { 572 { CnINTMSK0, CnINTMSKCLR0, 32, 573 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 }, 574 INTC_SMP_BALANCING(INTDISTCR0) }, 575 { INTMSK2, INTMSKCLR2, 32, 576 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 577 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 578 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH, 579 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0, 580 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH, 581 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH, 582 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH, 583 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 584 { CnINT2MSKR0, CnINT2MSKCR0 , 32, 585 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT }, 587 INTC_SMP_BALANCING(INT2DISTCR0) }, 588 { CnINT2MSKR1, CnINT2MSKCR1, 32, 589 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, 590 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, 591 HUDI1, HUDI0, 592 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3, 593 HPB_0, HPB_1, HPB_2, 594 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, 595 SCIF1, 596 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) }, 597 { CnINT2MSKR2, CnINT2MSKCR2, 32, 598 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, 599 Eth_0, Eth_1, 600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 601 PCIeC0_0, PCIeC0_1, PCIeC0_2, 602 PCIeC1_0, PCIeC1_1, PCIeC1_2, 603 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) }, 604 { CnINT2MSKR3, CnINT2MSKCR3, 32, 605 { 0, 0, 0, 0, 0, 0, 606 I2C0, I2C1, 607 DU, SSI0, SSI1, SSI2, SSI3, 608 PCIeC2_0, PCIeC2_1, PCIeC2_2, 609 HAC0, HAC1, 610 FLCTL, 0, 611 HSPI, GPIO0, GPIO1, Thermal, 612 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) }, 613}; 614 615static struct intc_prio_reg sh7786_prio_registers[] __initdata = { 616 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, 617 IRQ4, IRQ5, IRQ6, IRQ7 } }, 618 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } }, 619 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1, 620 TMU0_2, TMU0_3 } }, 621 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1, 622 TMU1_2, 0 } }, 623 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1, 624 DMAC0_2, DMAC0_3 } }, 625 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5, 626 DMAC0_6, HUDI1 } }, 627 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0, 628 DMAC1_1, DMAC1_2 } }, 629 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0, 630 HPB_1, HPB_2 } }, 631 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1, 632 SCIF0_2, SCIF0_3 } }, 633 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } }, 634 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } }, 635 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5, 636 Eth_0, Eth_1 } }, 637 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } }, 638 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } }, 639 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } }, 640 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } }, 641 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2, 642 PCIeC1_0, PCIeC1_1 } }, 643 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } }, 644 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } }, 645 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } }, 646 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } }, 647 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0, 648 PCIeC2_1, PCIeC2_2 } }, 649 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } }, 650 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0, 651 GPIO1, Thermal } }, 652 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } }, 653 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } }, 654 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */ 655 { INTICI7, INTICI6, INTICI5, INTICI4, 656 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) }, 657}; 658 659static struct intc_subgroup sh7786_subgroups[] __initdata = { 660 { 0xfe410c20, 32, SCIF1, 661 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 662 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } }, 663}; 664 665static struct intc_desc sh7786_intc_desc __initdata = { 666 .name = "sh7786", 667 .hw = { 668 .vectors = sh7786_vectors, 669 .nr_vectors = ARRAY_SIZE(sh7786_vectors), 670 .mask_regs = sh7786_mask_registers, 671 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers), 672 .subgroups = sh7786_subgroups, 673 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups), 674 .prio_regs = sh7786_prio_registers, 675 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers), 676 }, 677}; 678 679/* Support for external interrupt pins in IRQ mode */ 680static struct intc_vect vectors_irq0123[] __initdata = { 681 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240), 682 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0), 683}; 684 685static struct intc_vect vectors_irq4567[] __initdata = { 686 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340), 687 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0), 688}; 689 690static struct intc_sense_reg sh7786_sense_registers[] __initdata = { 691 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, 692 IRQ4, IRQ5, IRQ6, IRQ7 } }, 693}; 694 695static struct intc_mask_reg sh7786_ack_registers[] __initdata = { 696 { 0xfe410024, 0, 32, /* INTREQ */ 697 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 698}; 699 700static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123", 701 vectors_irq0123, NULL, sh7786_mask_registers, 702 sh7786_prio_registers, sh7786_sense_registers, 703 sh7786_ack_registers); 704 705static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567", 706 vectors_irq4567, NULL, sh7786_mask_registers, 707 sh7786_prio_registers, sh7786_sense_registers, 708 sh7786_ack_registers); 709 710/* External interrupt pins in IRL mode */ 711 712static struct intc_vect vectors_irl0123[] __initdata = { 713 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), 714 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), 715 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), 716 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0), 717 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320), 718 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360), 719 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0), 720 INTC_VECT(IRL0_HHHL, 0x3c0), 721}; 722 723static struct intc_vect vectors_irl4567[] __initdata = { 724 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920), 725 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960), 726 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0), 727 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0), 728 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20), 729 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60), 730 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0), 731 INTC_VECT(IRL4_HHHL, 0xac0), 732}; 733 734static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123, 735 NULL, sh7786_mask_registers, NULL, NULL); 736 737static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567, 738 NULL, sh7786_mask_registers, NULL, NULL); 739 740#define INTC_ICR0 0xfe410000 741#define INTC_INTMSK0 CnINTMSK0 742#define INTC_INTMSK1 CnINTMSK1 743#define INTC_INTMSK2 INTMSK2 744#define INTC_INTMSKCLR1 CnINTMSKCLR1 745#define INTC_INTMSKCLR2 INTMSKCLR2 746 747void __init plat_irq_setup(void) 748{ 749 /* disable IRQ3-0 + IRQ7-4 */ 750 __raw_writel(0xff000000, INTC_INTMSK0); 751 752 /* disable IRL3-0 + IRL7-4 */ 753 __raw_writel(0xc0000000, INTC_INTMSK1); 754 __raw_writel(0xfffefffe, INTC_INTMSK2); 755 756 /* select IRL mode for IRL3-0 + IRL7-4 */ 757 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 758 759 register_intc_controller(&sh7786_intc_desc); 760} 761 762void __init plat_irq_setup_pins(int mode) 763{ 764 switch (mode) { 765 case IRQ_MODE_IRQ7654: 766 /* select IRQ mode for IRL7-4 */ 767 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); 768 register_intc_controller(&intc_desc_irq4567); 769 break; 770 case IRQ_MODE_IRQ3210: 771 /* select IRQ mode for IRL3-0 */ 772 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); 773 register_intc_controller(&intc_desc_irq0123); 774 break; 775 case IRQ_MODE_IRL7654: 776 /* enable IRL7-4 but don't provide any masking */ 777 __raw_writel(0x40000000, INTC_INTMSKCLR1); 778 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); 779 break; 780 case IRQ_MODE_IRL3210: 781 /* enable IRL0-3 but don't provide any masking */ 782 __raw_writel(0x80000000, INTC_INTMSKCLR1); 783 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); 784 break; 785 case IRQ_MODE_IRL7654_MASK: 786 /* enable IRL7-4 and mask using cpu intc controller */ 787 __raw_writel(0x40000000, INTC_INTMSKCLR1); 788 register_intc_controller(&intc_desc_irl4567); 789 break; 790 case IRQ_MODE_IRL3210_MASK: 791 /* enable IRL0-3 and mask using cpu intc controller */ 792 __raw_writel(0x80000000, INTC_INTMSKCLR1); 793 register_intc_controller(&intc_desc_irl0123); 794 break; 795 default: 796 BUG(); 797 } 798} 799 800void __init plat_mem_setup(void) 801{ 802} 803 804static int __init sh7786_devices_setup(void) 805{ 806 int ret, irq; 807 808 sh7786_usb_setup(); 809 810 /* 811 * De-mux SCIF1 IRQs if possible 812 */ 813 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); 814 if (irq > 0) { 815 scif1_demux_resources[1].start = 816 intc_irq_lookup(sh7786_intc_desc.name, ERI1); 817 scif1_demux_resources[2].start = 818 intc_irq_lookup(sh7786_intc_desc.name, RXI1); 819 scif1_demux_resources[3].start = irq; 820 scif1_demux_resources[4].start = 821 intc_irq_lookup(sh7786_intc_desc.name, BRI1); 822 823 scif1_device.resource = scif1_demux_resources; 824 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources); 825 } 826 827 ret = platform_add_devices(sh7786_early_devices, 828 ARRAY_SIZE(sh7786_early_devices)); 829 if (unlikely(ret != 0)) 830 return ret; 831 832 return platform_add_devices(sh7786_devices, 833 ARRAY_SIZE(sh7786_devices)); 834} 835arch_initcall(sh7786_devices_setup); 836 837void __init plat_early_device_setup(void) 838{ 839 sh_early_platform_add_devices(sh7786_early_devices, 840 ARRAY_SIZE(sh7786_early_devices)); 841} 842