1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * R-Car Display Unit Channels Pair 4 * 5 * Copyright (C) 2013-2015 Renesas Electronics Corporation 6 * 7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8 */ 9 10/* 11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending 12 * unit, timings generator, ...) and device-global resources (start/stop 13 * control, planes, ...) shared between the two CRTCs. 14 * 15 * The R8A7790 introduced a third CRTC with its own set of global resources. 16 * This would be modeled as two separate DU device instances if it wasn't for 17 * a handful or resources that are shared between the three CRTCs (mostly 18 * related to input and output routing). For this reason the R8A7790 DU must be 19 * modeled as a single device with three CRTCs, two sets of "semi-global" 20 * resources, and a few device-global resources. 21 * 22 * The rcar_du_group object is a driver specific object, without any real 23 * counterpart in the DU documentation, that models those semi-global resources. 24 */ 25 26#include <linux/clk.h> 27#include <linux/io.h> 28 29#include "rcar_du_drv.h" 30#include "rcar_du_group.h" 31#include "rcar_du_regs.h" 32 33u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg) 34{ 35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); 36} 37 38void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data) 39{ 40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); 41} 42 43static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp) 44{ 45 u32 defr6 = DEFR6_CODE; 46 47 if (rgrp->channels_mask & BIT(0)) 48 defr6 |= DEFR6_ODPM02_DISP; 49 50 if (rgrp->channels_mask & BIT(1)) 51 defr6 |= DEFR6_ODPM12_DISP; 52 53 rcar_du_group_write(rgrp, DEFR6, defr6); 54} 55 56static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp) 57{ 58 struct rcar_du_device *rcdu = rgrp->dev; 59 u32 defr8 = DEFR8_CODE; 60 61 if (rcdu->info->gen < 3) { 62 defr8 |= DEFR8_DEFE8; 63 64 /* 65 * On Gen2 the DEFR8 register for the first group also controls 66 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for 67 * DU instances that support it. 68 */ 69 if (rgrp->index == 0) { 70 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source); 71 if (rgrp->dev->vspd1_sink == 2) 72 defr8 |= DEFR8_VSCS; 73 } 74 } else { 75 /* 76 * On Gen3 VSPD routing can't be configured, and DPAD routing 77 * is set in the group corresponding to the DPAD output (no Gen3 78 * SoC has multiple DPAD sources belonging to separate groups). 79 */ 80 if (rgrp->index == rcdu->dpad0_source / 2) 81 defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source); 82 } 83 84 rcar_du_group_write(rgrp, DEFR8, defr8); 85} 86 87static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp) 88{ 89 struct rcar_du_device *rcdu = rgrp->dev; 90 struct rcar_du_crtc *rcrtc; 91 unsigned int num_crtcs = 0; 92 unsigned int i; 93 u32 didsr; 94 95 /* 96 * Configure input dot clock routing with a hardcoded configuration. If 97 * the DU channel can use the LVDS encoder output clock as the dot 98 * clock, do so. Otherwise route DU_DOTCLKINn signal to DUn. 99 * 100 * Each channel can then select between the dot clock configured here 101 * and the clock provided by the CPG through the ESCR register. 102 */ 103 if (rcdu->info->gen < 3 && rgrp->index == 0) { 104 /* 105 * On Gen2 a single register in the first group controls dot 106 * clock selection for all channels. 107 */ 108 rcrtc = rcdu->crtcs; 109 num_crtcs = rcdu->num_crtcs; 110 } else if (rcdu->info->gen >= 3 && rgrp->num_crtcs > 1) { 111 /* 112 * On Gen3 dot clocks are setup through per-group registers, 113 * only available when the group has two channels. 114 */ 115 rcrtc = &rcdu->crtcs[rgrp->index * 2]; 116 num_crtcs = rgrp->num_crtcs; 117 } 118 119 if (!num_crtcs) 120 return; 121 122 didsr = DIDSR_CODE; 123 for (i = 0; i < num_crtcs; ++i, ++rcrtc) { 124 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) 125 didsr |= DIDSR_LDCS_LVDS0(i) 126 | DIDSR_PDCS_CLK(i, 0); 127 else if (rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) 128 didsr |= DIDSR_LDCS_DSI(i); 129 else 130 didsr |= DIDSR_LDCS_DCLKIN(i) 131 | DIDSR_PDCS_CLK(i, 0); 132 } 133 134 rcar_du_group_write(rgrp, DIDSR, didsr); 135} 136 137static void rcar_du_group_setup(struct rcar_du_group *rgrp) 138{ 139 struct rcar_du_device *rcdu = rgrp->dev; 140 u32 defr7 = DEFR7_CODE; 141 u32 dorcr; 142 143 /* Enable extended features */ 144 rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE); 145 if (rcdu->info->gen < 3) { 146 rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G); 147 rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3); 148 rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); 149 } 150 rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); 151 152 if (rcdu->info->gen < 4) 153 rcar_du_group_setup_pins(rgrp); 154 155 if (rcdu->info->gen < 4) { 156 /* 157 * TODO: Handle routing of the DU output to CMM dynamically, as 158 * we should bypass CMM completely when no color management 159 * feature is used. 160 */ 161 defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) | 162 (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0); 163 rcar_du_group_write(rgrp, DEFR7, defr7); 164 } 165 166 if (rcdu->info->gen >= 2) { 167 if (rcdu->info->gen < 4) 168 rcar_du_group_setup_defr8(rgrp); 169 rcar_du_group_setup_didsr(rgrp); 170 } 171 172 if (rcdu->info->gen >= 3) 173 rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); 174 175 /* 176 * Use DS1PR and DS2PR to configure planes priorities and connects the 177 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. 178 * 179 * Groups that have a single channel have a hardcoded configuration. On 180 * Gen3 and newer, the documentation requires PG1T, DK1S and PG1D_DS1 to 181 * always be set in this case. 182 */ 183 dorcr = DORCR_PG0D_DS0 | DORCR_DPRS; 184 if (rcdu->info->gen >= 3 && rgrp->num_crtcs == 1) 185 dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1; 186 rcar_du_group_write(rgrp, DORCR, dorcr); 187 188 /* Apply planes to CRTCs association. */ 189 mutex_lock(&rgrp->lock); 190 rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | 191 rgrp->dptsr_planes); 192 mutex_unlock(&rgrp->lock); 193} 194 195/* 196 * rcar_du_group_get - Acquire a reference to the DU channels group 197 * 198 * Acquiring the first reference setups core registers. A reference must be held 199 * before accessing any hardware registers. 200 * 201 * This function must be called with the DRM mode_config lock held. 202 * 203 * Return 0 in case of success or a negative error code otherwise. 204 */ 205int rcar_du_group_get(struct rcar_du_group *rgrp) 206{ 207 if (rgrp->use_count) 208 goto done; 209 210 rcar_du_group_setup(rgrp); 211 212done: 213 rgrp->use_count++; 214 return 0; 215} 216 217/* 218 * rcar_du_group_put - Release a reference to the DU 219 * 220 * This function must be called with the DRM mode_config lock held. 221 */ 222void rcar_du_group_put(struct rcar_du_group *rgrp) 223{ 224 --rgrp->use_count; 225} 226 227static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) 228{ 229 struct rcar_du_device *rcdu = rgrp->dev; 230 231 /* 232 * Group start/stop is controlled by the DRES and DEN bits of DSYSR0 233 * for the first group and DSYSR2 for the second group. On most DU 234 * instances, this maps to the first CRTC of the group, and we can just 235 * use rcar_du_crtc_dsysr_clr_set() to access the correct DSYSR. On 236 * M3-N, however, DU2 doesn't exist, but DSYSR2 does. We thus need to 237 * access the register directly using group read/write. 238 */ 239 if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) { 240 struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; 241 242 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, 243 start ? DSYSR_DEN : DSYSR_DRES); 244 } else { 245 rcar_du_group_write(rgrp, DSYSR, 246 start ? DSYSR_DEN : DSYSR_DRES); 247 } 248} 249 250void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) 251{ 252 /* 253 * Many of the configuration bits are only updated when the display 254 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some 255 * of those bits could be pre-configured, but others (especially the 256 * bits related to plane assignment to display timing controllers) need 257 * to be modified at runtime. 258 * 259 * Restart the display controller if a start is requested. Sorry for the 260 * flicker. It should be possible to move most of the "DRES-update" bits 261 * setup to driver initialization time and minimize the number of cases 262 * when the display controller will have to be restarted. 263 */ 264 if (start) { 265 if (rgrp->used_crtcs++ != 0) 266 __rcar_du_group_start_stop(rgrp, false); 267 __rcar_du_group_start_stop(rgrp, true); 268 } else { 269 if (--rgrp->used_crtcs == 0) 270 __rcar_du_group_start_stop(rgrp, false); 271 } 272} 273 274void rcar_du_group_restart(struct rcar_du_group *rgrp) 275{ 276 rgrp->need_restart = false; 277 278 __rcar_du_group_start_stop(rgrp, false); 279 __rcar_du_group_start_stop(rgrp, true); 280} 281 282int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu) 283{ 284 struct rcar_du_group *rgrp; 285 struct rcar_du_crtc *crtc; 286 unsigned int index; 287 int ret; 288 289 if (rcdu->info->gen < 2) 290 return 0; 291 292 /* 293 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are 294 * configured in the DEFR8 register of the first group on Gen2 and the 295 * last group on Gen3. As this function can be called with the DU 296 * channels of the corresponding CRTCs disabled, we need to enable the 297 * group clock before accessing the register. 298 */ 299 index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1; 300 rgrp = &rcdu->groups[index]; 301 crtc = &rcdu->crtcs[index * 2]; 302 303 ret = clk_prepare_enable(crtc->clock); 304 if (ret < 0) 305 return ret; 306 307 rcar_du_group_setup_defr8(rgrp); 308 309 clk_disable_unprepare(crtc->clock); 310 311 return 0; 312} 313 314static void rcar_du_group_set_dpad_levels(struct rcar_du_group *rgrp) 315{ 316 static const u32 doflr_values[2] = { 317 DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 | 318 DOFLR_DISPFL0 | DOFLR_CDEFL0 | DOFLR_RGBFL0, 319 DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 | 320 DOFLR_DISPFL1 | DOFLR_CDEFL1 | DOFLR_RGBFL1, 321 }; 322 static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1) 323 | BIT(RCAR_DU_OUTPUT_DPAD0); 324 struct rcar_du_device *rcdu = rgrp->dev; 325 u32 doflr = DOFLR_CODE; 326 unsigned int i; 327 328 if (rcdu->info->gen < 2) 329 return; 330 331 /* 332 * The DPAD outputs can't be controlled directly. However, the parallel 333 * output of the DU channels routed to DPAD can be set to fixed levels 334 * through the DOFLR group register. Use this to turn the DPAD on or off 335 * by driving fixed low-level signals at the output of any DU channel 336 * not routed to a DPAD output. This doesn't affect the DU output 337 * signals going to other outputs, such as the internal LVDS and HDMI 338 * encoders. 339 */ 340 341 for (i = 0; i < rgrp->num_crtcs; ++i) { 342 struct rcar_du_crtc_state *rstate; 343 struct rcar_du_crtc *rcrtc; 344 345 rcrtc = &rcdu->crtcs[rgrp->index * 2 + i]; 346 rstate = to_rcar_crtc_state(rcrtc->crtc.state); 347 348 if (!(rstate->outputs & dpad_mask)) 349 doflr |= doflr_values[i]; 350 } 351 352 rcar_du_group_write(rgrp, DOFLR, doflr); 353} 354 355int rcar_du_group_set_routing(struct rcar_du_group *rgrp) 356{ 357 struct rcar_du_device *rcdu = rgrp->dev; 358 u32 dorcr = rcar_du_group_read(rgrp, DORCR); 359 360 dorcr &= ~(DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_MASK); 361 362 /* 363 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and 364 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1 365 * by default. 366 */ 367 if (rcdu->dpad1_source == rgrp->index * 2) 368 dorcr |= DORCR_PG1D_DS0; 369 else 370 dorcr |= DORCR_PG1T | DORCR_DK1S | DORCR_PG1D_DS1; 371 372 rcar_du_group_write(rgrp, DORCR, dorcr); 373 374 rcar_du_group_set_dpad_levels(rgrp); 375 376 return rcar_du_set_dpad0_vsp1_routing(rgrp->dev); 377} 378