1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * RZ/G2L Display Unit Mode Setting
4 *
5 * Copyright (C) 2023 Renesas Electronics Corporation
6 *
7 * Based on rcar_du_kms.c
8 */
9
10#include <drm/drm_atomic.h>
11#include <drm/drm_atomic_helper.h>
12#include <drm/drm_crtc.h>
13#include <drm/drm_device.h>
14#include <drm/drm_framebuffer.h>
15#include <drm/drm_gem_dma_helper.h>
16#include <drm/drm_gem_framebuffer_helper.h>
17#include <drm/drm_managed.h>
18#include <drm/drm_probe_helper.h>
19#include <drm/drm_vblank.h>
20
21#include <linux/device.h>
22#include <linux/of.h>
23#include <linux/of_graph.h>
24#include <linux/of_platform.h>
25#include <linux/platform_device.h>
26
27#include "rzg2l_du_crtc.h"
28#include "rzg2l_du_drv.h"
29#include "rzg2l_du_encoder.h"
30#include "rzg2l_du_kms.h"
31#include "rzg2l_du_vsp.h"
32
33/* -----------------------------------------------------------------------------
34 * Format helpers
35 */
36
37static const struct rzg2l_du_format_info rzg2l_du_format_infos[] = {
38	{
39		.fourcc = DRM_FORMAT_XRGB8888,
40		.v4l2 = V4L2_PIX_FMT_XBGR32,
41		.bpp = 32,
42		.planes = 1,
43		.hsub = 1,
44	}, {
45		.fourcc = DRM_FORMAT_ARGB8888,
46		.v4l2 = V4L2_PIX_FMT_ABGR32,
47		.bpp = 32,
48		.planes = 1,
49		.hsub = 1,
50	}, {
51		.fourcc = DRM_FORMAT_RGB888,
52		.v4l2 = V4L2_PIX_FMT_BGR24,
53		.bpp = 24,
54		.planes = 1,
55		.hsub = 1,
56	}
57};
58
59const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc)
60{
61	unsigned int i;
62
63	for (i = 0; i < ARRAY_SIZE(rzg2l_du_format_infos); ++i) {
64		if (rzg2l_du_format_infos[i].fourcc == fourcc)
65			return &rzg2l_du_format_infos[i];
66	}
67
68	return NULL;
69}
70
71/* -----------------------------------------------------------------------------
72 * Frame buffer
73 */
74
75int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev,
76			 struct drm_mode_create_dumb *args)
77{
78	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
79	unsigned int align = 16 * args->bpp / 8;
80
81	args->pitch = roundup(min_pitch, align);
82
83	return drm_gem_dma_dumb_create_internal(file, dev, args);
84}
85
86static struct drm_framebuffer *
87rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
88		   const struct drm_mode_fb_cmd2 *mode_cmd)
89{
90	const struct rzg2l_du_format_info *format;
91	unsigned int max_pitch;
92
93	format = rzg2l_du_format_info(mode_cmd->pixel_format);
94	if (!format) {
95		dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
96			&mode_cmd->pixel_format);
97		return ERR_PTR(-EINVAL);
98	}
99
100	/*
101	 * On RZ/G2L the memory interface is handled by the VSP that limits the
102	 * pitch to 65535 bytes.
103	 */
104	max_pitch = 65535;
105	if (mode_cmd->pitches[0] > max_pitch) {
106		dev_dbg(dev->dev, "invalid pitch value %u\n",
107			mode_cmd->pitches[0]);
108		return ERR_PTR(-EINVAL);
109	}
110
111	return drm_gem_fb_create(dev, file_priv, mode_cmd);
112}
113
114/* -----------------------------------------------------------------------------
115 * Initialization
116 */
117
118static const struct drm_mode_config_helper_funcs rzg2l_du_mode_config_helper = {
119	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
120};
121
122static const struct drm_mode_config_funcs rzg2l_du_mode_config_funcs = {
123	.fb_create = rzg2l_du_fb_create,
124	.atomic_check = drm_atomic_helper_check,
125	.atomic_commit = drm_atomic_helper_commit,
126};
127
128static int rzg2l_du_encoders_init_one(struct rzg2l_du_device *rcdu,
129				      enum rzg2l_du_output output,
130				      struct of_endpoint *ep)
131{
132	struct device_node *entity;
133	int ret;
134
135	/* Locate the connected entity and initialize the encoder. */
136	entity = of_graph_get_remote_port_parent(ep->local_node);
137	if (!entity) {
138		dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
139			ep->local_node);
140		return -ENODEV;
141	}
142
143	if (!of_device_is_available(entity)) {
144		dev_dbg(rcdu->dev,
145			"connected entity %pOF is disabled, skipping\n",
146			entity);
147		of_node_put(entity);
148		return -ENODEV;
149	}
150
151	ret = rzg2l_du_encoder_init(rcdu, output, entity);
152	if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
153		dev_warn(rcdu->dev,
154			 "failed to initialize encoder %pOF on output %s (%d), skipping\n",
155			 entity, rzg2l_du_output_name(output), ret);
156
157	of_node_put(entity);
158
159	return ret;
160}
161
162static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu)
163{
164	struct device_node *np = rcdu->dev->of_node;
165	struct device_node *ep_node;
166	unsigned int num_encoders = 0;
167
168	/*
169	 * Iterate over the endpoints and create one encoder for each output
170	 * pipeline.
171	 */
172	for_each_endpoint_of_node(np, ep_node) {
173		enum rzg2l_du_output output;
174		struct of_endpoint ep;
175		unsigned int i;
176		int ret;
177
178		ret = of_graph_parse_endpoint(ep_node, &ep);
179		if (ret < 0) {
180			of_node_put(ep_node);
181			return ret;
182		}
183
184		/* Find the output route corresponding to the port number. */
185		for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {
186			if (rcdu->info->routes[i].port == ep.port) {
187				output = i;
188				break;
189			}
190		}
191
192		if (i == RZG2L_DU_OUTPUT_MAX) {
193			dev_warn(rcdu->dev,
194				 "port %u references unexisting output, skipping\n",
195				 ep.port);
196			continue;
197		}
198
199		/* Process the output pipeline. */
200		ret = rzg2l_du_encoders_init_one(rcdu, output, &ep);
201		if (ret < 0) {
202			if (ret == -EPROBE_DEFER) {
203				of_node_put(ep_node);
204				return ret;
205			}
206
207			continue;
208		}
209
210		num_encoders++;
211	}
212
213	return num_encoders;
214}
215
216static int rzg2l_du_vsps_init(struct rzg2l_du_device *rcdu)
217{
218	const struct device_node *np = rcdu->dev->of_node;
219	const char *vsps_prop_name = "renesas,vsps";
220	struct of_phandle_args args;
221	struct {
222		struct device_node *np;
223		unsigned int crtcs_mask;
224	} vsps[RZG2L_DU_MAX_VSPS] = { { NULL, }, };
225	unsigned int vsps_count = 0;
226	unsigned int cells;
227	unsigned int i;
228	int ret;
229
230	/*
231	 * First parse the DT vsps property to populate the list of VSPs. Each
232	 * entry contains a pointer to the VSP DT node and a bitmask of the
233	 * connected DU CRTCs.
234	 */
235	ret = of_property_count_u32_elems(np, vsps_prop_name);
236	cells = ret / rcdu->num_crtcs - 1;
237	if (cells != 1)
238		return -EINVAL;
239
240	for (i = 0; i < rcdu->num_crtcs; ++i) {
241		unsigned int j;
242
243		ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
244						       cells, i, &args);
245		if (ret < 0)
246			goto done;
247
248		/*
249		 * Add the VSP to the list or update the corresponding existing
250		 * entry if the VSP has already been added.
251		 */
252		for (j = 0; j < vsps_count; ++j) {
253			if (vsps[j].np == args.np)
254				break;
255		}
256
257		if (j < vsps_count)
258			of_node_put(args.np);
259		else
260			vsps[vsps_count++].np = args.np;
261
262		vsps[j].crtcs_mask |= BIT(i);
263
264		/*
265		 * Store the VSP pointer and pipe index in the CRTC. If the
266		 * second cell of the 'renesas,vsps' specifier isn't present,
267		 * default to 0.
268		 */
269		rcdu->crtcs[i].vsp = &rcdu->vsps[j];
270		rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
271	}
272
273	/*
274	 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
275	 * computed previously.
276	 */
277	for (i = 0; i < vsps_count; ++i) {
278		struct rzg2l_du_vsp *vsp = &rcdu->vsps[i];
279
280		vsp->index = i;
281		vsp->dev = rcdu;
282
283		ret = rzg2l_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
284		if (ret)
285			goto done;
286	}
287
288done:
289	for (i = 0; i < ARRAY_SIZE(vsps); ++i)
290		of_node_put(vsps[i].np);
291
292	return ret;
293}
294
295int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)
296{
297	struct drm_device *dev = &rcdu->ddev;
298	struct drm_encoder *encoder;
299	unsigned int num_encoders;
300	int ret;
301
302	ret = drmm_mode_config_init(dev);
303	if (ret)
304		return ret;
305
306	dev->mode_config.min_width = 0;
307	dev->mode_config.min_height = 0;
308	dev->mode_config.normalize_zpos = true;
309	dev->mode_config.funcs = &rzg2l_du_mode_config_funcs;
310	dev->mode_config.helper_private = &rzg2l_du_mode_config_helper;
311
312	/*
313	 * The RZ DU uses the VSP1 for memory access, and is limited
314	 * to frame sizes of 1920x1080.
315	 */
316	dev->mode_config.max_width = 1920;
317	dev->mode_config.max_height = 1080;
318
319	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
320
321	/*
322	 * Initialize vertical blanking interrupts handling. Start with vblank
323	 * disabled for all CRTCs.
324	 */
325	ret = drm_vblank_init(dev, rcdu->num_crtcs);
326	if (ret < 0)
327		return ret;
328
329	/* Initialize the compositors. */
330	ret = rzg2l_du_vsps_init(rcdu);
331	if (ret < 0)
332		return ret;
333
334	/* Create the CRTCs. */
335	ret = rzg2l_du_crtc_create(rcdu);
336	if (ret < 0)
337		return ret;
338
339	/* Initialize the encoders. */
340	ret = rzg2l_du_encoders_init(rcdu);
341	if (ret < 0)
342		return dev_err_probe(rcdu->dev, ret,
343				     "failed to initialize encoders\n");
344
345	if (ret == 0) {
346		dev_err(rcdu->dev, "error: no encoder could be initialized\n");
347		return -EINVAL;
348	}
349
350	num_encoders = ret;
351
352	/*
353	 * Set the possible CRTCs and possible clones. There's always at least
354	 * one way for all encoders to clone each other, set all bits in the
355	 * possible clones field.
356	 */
357	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
358		struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
359		const struct rzg2l_du_output_routing *route =
360			&rcdu->info->routes[renc->output];
361
362		encoder->possible_crtcs = route->possible_outputs;
363		encoder->possible_clones = (1 << num_encoders) - 1;
364	}
365
366	drm_mode_config_reset(dev);
367
368	drm_kms_helper_poll_init(dev);
369
370	return 0;
371}
372