Searched refs:bank (Results 1 - 25 of 367) sorted by last modified time

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/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_debugfs.c1451 int bank, max_bank; local
1463 for (bank = 0; bank < max_bank; bank++) {
1464 seq_printf(s, "BANK:%d\n", bank);
1467 NDC_AF_BANKX_HIT_PC(bank)));
1470 NDC_AF_BANKX_MISS_PC(bank)));
H A Drvu_npc.c174 int bank = index / mcam->banksize; local
178 return bank ? 2 : 0;
180 return bank;
186 int bank = npc_get_bank(mcam, index); local
190 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
197 int bank = npc_get_bank(mcam, index); local
198 int actbank = bank;
201 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
203 NPC_AF_MCAMEX_BANKX_CFG(index, bank),
211 int bank = npc_get_bank(mcam, index); local
367 int bank, nixlf, index; local
433 int bank = npc_get_bank(mcam, index); local
509 int bank, kw = 0; local
546 int bank, i; local
583 int bank = npc_get_bank(mcam, index); local
593 int bank = npc_get_bank(mcam, index); local
950 int actindex, index, bank, entry; local
997 int bank, op_rss; local
1023 int blkaddr, index, bank; local
2098 int blkaddr, entry, bank, err; local
2266 u32 bank = npc_get_bank(mcam, entry); local
2283 u32 bank = npc_get_bank(mcam, entry); local
3440 u32 bank; local
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/linux-master/drivers/soundwire/
H A Damd_manager.c430 unsigned int bank)
457 enum sdw_reg_bank bank)
517 unsigned int bank)
429 amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params, unsigned int bank) argument
455 amd_sdw_transport_params(struct sdw_bus *bus, struct sdw_transport_params *params, enum sdw_reg_bank bank) argument
515 amd_sdw_port_enable(struct sdw_bus *bus, struct sdw_enable_ch *enable_ch, unsigned int bank) argument
/linux-master/drivers/net/ethernet/mellanox/mlxsw/
H A Dcore_env.c495 mlxsw_reg_mcia_bank_number_set(mcia_pl, page->bank);
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c2630 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
2916 /* if valid mca bank count is 0, the driver can return 0 directly */
3104 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3111 enum aca_error_type type, int idx, struct aca_bank *bank)
3115 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3117 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3110 aca_smu_get_valid_aca_bank(struct amdgpu_device *adev, enum aca_error_type type, int idx, struct aca_bank *bank) argument
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4_2.c2184 struct aca_bank *bank, enum aca_error_type type,
2190 status = bank->regs[ACA_REG_IDX_STATUS];
2196 ret = aca_bank_info_decode(bank, &report->info);
2200 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2210 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, argument
2215 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2221 if (aca_bank_check_error_codes(handle->adev, bank,
2183 sdma_v4_4_2_aca_bank_generate_report(struct aca_handle *handle, struct aca_bank *bank, enum aca_error_type type, struct aca_bank_report *report, void *data) argument
/linux-master/drivers/gpio/
H A Dgpio-tegra186.c72 unsigned int bank; member in struct:tegra_gpio_port
139 offset = port->bank * 0x1000 + port->port * 0x200;
154 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
642 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
644 /* skip ports that are not associated with this bank */
646 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
759 base = gpio->secure + port->bank * 0x1000 + 0x800;
838 if (gpio->soc->ports[i].bank > gpio->num_banks)
839 gpio->num_banks = gpio->soc->ports[i].bank;
943 * To simplify things, use a single interrupt per bank fo
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H A Dgpio-lpc32xx.c494 /* Is this the correct bank? */
495 u32 bank = gpiospec->args[0]; local
496 if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
497 (gc != &lpc32xx_gpiochip[bank].chip)))
/linux-master/arch/x86/kvm/
H A Dx86.c3457 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3521 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
5233 unsigned bank_num = mcg_cap & 0xff, bank; local
5246 for (bank = 0; bank < bank_num; bank++) {
5247 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5249 vcpu->arch.mci_ctl2_banks[bank] = 0;
5286 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5302 if (mce->bank >
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/linux-master/tools/arch/x86/include/uapi/asm/
H A Dkvm.h538 __u8 bank; member in struct:kvm_x86_mce
/linux-master/sound/core/seq/
H A Dseq_ump_convert.c272 ev->data.control.param = (val->rpn.bank << 7) | val->rpn.index;
757 data->rpn.bank = cc->cc_rpn_msb;
763 data->rpn.bank = cc->cc_nrpn_msb;
784 /* process special CC's (bank/rpn/nrpn) */
890 /* process special CC's (bank/rpn/nrpn) */
947 data->rpn.bank = (event->data.control.param >> 7) & 0x7f;
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/
H A Den_ethtool.c1842 query.bank = page_data->bank;
/linux-master/drivers/iommu/
H A Dmtk_iommu.c230 * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
231 * Here list how many banks this SoC supports/enables and which ports are in which bank.
249 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */
264 struct mtk_iommu_bank_data *bank; member in struct:mtk_iommu_data
284 struct mtk_iommu_bank_data *bank; member in struct:mtk_iommu_domain
378 struct mtk_iommu_bank_data *bank = &data->bank[0]; local
379 void __iomem *base = bank->base;
382 spin_lock_irqsave(&bank->tlb_lock, flags);
386 spin_unlock_irqrestore(&bank
389 mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, struct mtk_iommu_bank_data *bank) argument
457 struct mtk_iommu_bank_data *bank = dev_id; local
715 struct mtk_iommu_bank_data *bank; local
1258 struct mtk_iommu_bank_data *bank; local
1415 struct mtk_iommu_bank_data *bank; local
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/linux-master/drivers/iommu/amd/
H A Dinit.c3751 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, argument
3765 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3789 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) argument
3794 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3797 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) argument
3802 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
/linux-master/arch/x86/kernel/cpu/mce/
H A Dcore.c76 /* One object for each MCE bank, shared by all CPUs */
80 u8 bank; /* bank number */ member in struct:mce_bank_dev
167 m->mcgstatus, m->bank, m->status);
333 unsigned bank = __this_cpu_read(injectm.bank); local
337 if (msr == mca_msr_reg(bank, MCA_STATUS))
339 if (msr == mca_msr_reg(bank, MCA_ADDR))
341 if (msr == mca_msr_reg(bank, MCA_MISC))
434 * the severity of the problem as we read per-bank specifi
804 quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) argument
887 quirk_zen_ifu(int bank, struct mce *m, struct pt_regs *regs) argument
2269 int bank = *((int *)arg); local
2274 mce_disable_bank(int bank) argument
2475 u8 bank = attr_to_bank(attr)->bank; local
2492 u8 bank = attr_to_bank(attr)->bank; local
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/linux-master/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.c99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
3181 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3183 * @bank: pointer to the variable that returns the active bank
3186 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3188 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) argument
3210 /* set bank to 0 in case flash read fails */
3211 *bank = 0;
3213 /* Check bank 0 */
3221 *bank
3302 u32 bank = 0; local
3395 u32 bank = 0; local
3822 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; local
3983 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; local
4485 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) argument
5703 u32 bank = 0; local
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/linux-master/drivers/net/dsa/sja1105/
H A Dsja1105_mdio.c57 int offset, bank; local
72 bank = addr >> 8;
75 /* This addressing scheme reserves register 0xff for the bank address
81 tmp = bank;
103 int offset, bank; local
113 bank = addr >> 8;
116 /* This addressing scheme reserves register 0xff for the bank address
122 tmp = bank;
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgf100.c2292 u8 bank[GPC_MAX] = {}, gpc, i, j; local
2297 data |= bank[gr->tile[i + j]] << (j * 4);
2298 bank[gr->tile[i + j]]++;
/linux-master/arch/x86/include/uapi/asm/
H A Dkvm.h538 __u8 bank; member in struct:kvm_x86_mce
/linux-master/drivers/pinctrl/
H A Dpinctrl-amd.c193 unsigned int bank, i, pin_num; local
214 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
218 switch (bank) {
236 /* Illegal bank number, ignore */
239 seq_printf(s, "GPIO bank%d\n", bank);
/linux-master/drivers/usb/host/
H A Dsl811-hcd.c68 /* for now, use only one transfer register bank */
138 u8 bank,
146 addr = SL811HS_PACKET_BUF(bank == 0);
152 sl811_write(sl811, bank + SL11H_BUFADDRREG, addr);
158 sl811_write(sl811, bank + SL11H_HOSTCTLREG,
169 u8 bank,
180 sl811_write(sl811, bank + SL11H_BUFADDRREG, 0);
189 sl811_write(sl811, bank + SL11H_HOSTCTLREG, control);
203 u8 bank,
213 addr = SL811HS_PACKET_BUF(bank
134 setup_packet( struct sl811 *sl811, struct sl811h_ep *ep, struct urb *urb, u8 bank, u8 control ) argument
165 status_packet( struct sl811 *sl811, struct sl811h_ep *ep, struct urb *urb, u8 bank, u8 control ) argument
199 in_packet( struct sl811 *sl811, struct sl811h_ep *ep, struct urb *urb, u8 bank, u8 control ) argument
235 out_packet( struct sl811 *sl811, struct sl811h_ep *ep, struct urb *urb, u8 bank, u8 control ) argument
302 start(struct sl811 *sl811, u8 bank) argument
475 done(struct sl811 *sl811, struct sl811h_ep *ep, u8 bank) argument
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/linux-master/drivers/staging/rtl8723bs/hal/
H A Drtl8723b_hal_init.c451 struct adapter *padapter, u8 bank, bool bPseudoTest
464 pEfuseHal->fakeEfuseBank = bank;
466 fakeEfuseBank = bank;
472 switch (bank) {
750 /* switch bank back to bank 0 for later BT and wifi use. */
829 u8 bank; local
852 for (bank = 1; bank < 3; bank
450 hal_EfuseSwitchToBank( struct adapter *padapter, u8 bank, bool bPseudoTest ) argument
1046 u8 bank, startBank; local
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/linux-master/drivers/hwspinlock/
H A Domap_hwspinlock.c77 struct hwspinlock_device *bank; local
114 bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
116 if (!bank)
120 bank->lock[i].priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
122 return devm_hwspin_lock_register(&pdev->dev, bank, &omap_hwspinlock_ops,
/linux-master/drivers/thermal/mediatek/
H A Dauxadc_thermal.c109 /* The number of sensing points per bank */
198 /* The number of sensing points per bank */
219 /* The number of sensing points per bank */
258 /* The number of sensing points per bank */
276 /* The number of sensing points per bank */
472 * The MT8173 thermal controller has four banks. Each bank can read up to
474 * temperature sensors. We use each bank to measure a certain area of the
479 * the bank concept wouldn't be necessary here. However, the SVS (Smart
480 * Voltage Scaling) unit makes its decisions based on the same bank
515 * The MT2701 thermal controller has one bank, whic
780 mtk_thermal_get_bank(struct mtk_thermal_bank *bank) argument
801 mtk_thermal_put_bank(struct mtk_thermal_bank *bank) argument
816 mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) argument
855 struct mtk_thermal_bank *bank = &mt->banks[i]; local
877 struct mtk_thermal_bank *bank = &mt->banks[num]; local
[all...]
/linux-master/drivers/reset/
H A Dreset-simple.c35 int bank = id / (reg_width * BITS_PER_BYTE); local
42 reg = readl(data->membase + (bank * reg_width));
47 writel(reg, data->membase + (bank * reg_width));
89 int bank = id / (reg_width * BITS_PER_BYTE); local
93 reg = readl(data->membase + (bank * reg_width));

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