Searched refs:M2 (Results 1 - 25 of 30) sorted by path

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/linux-master/arch/xtensa/variants/csp/include/variant/
H A Dtie-asm.h111 rsr.M2 \at1 // MAC16 option
178 wsr.M2 \at1 // MAC16 option
/linux-master/arch/xtensa/variants/dc232b/include/variant/
H A Dtie-asm.h53 rsr \at1, M2
96 wsr \at1, M2
/linux-master/arch/xtensa/variants/dc233c/include/variant/
H A Dtie-asm.h108 rsr \at1, M2 // MAC16 option
173 wsr \at1, M2 // MAC16 option
/linux-master/arch/xtensa/variants/de212/include/variant/
H A Dtie-asm.h99 rsr.M2 \at1 // MAC16 option
154 wsr.M2 \at1 // MAC16 option
/linux-master/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dtie-asm.h111 rsr.M2 \at1 // MAC16 option
178 wsr.M2 \at1 // MAC16 option
/linux-master/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dtie-asm.h108 rsr.M2 \at1 // MAC16 option
175 wsr.M2 \at1 // MAC16 option
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dpll.h9 uint8_t N1, M1, N2, M2; member in struct:nvkm_pll_vals::__anon87::__anon88
11 uint8_t M1, N1, M2, N2;
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpll.h9 int *N1, int *M1, int *N2, int *M2, int *P);
H A Dpllnv04.c151 int M1, N1, M2, N2, log2P; local
177 for (M2 = minM2; M2 <= maxM2; M2++) {
178 if (calcclk1/M2 < minU2)
180 if (calcclk1/M2 > maxU2)
184 N2 = (clkP * M2 + calcclk1/2) / calcclk1;
192 if (N2/M2 < 4 || N2/M2 > 10)
195 calcclk2 = calcclk1 * N2 / M2;
227 nv04_pll_calc(struct nvkm_subdev *subdev, struct nvbios_pll *info, u32 freq, int *N1, int *M1, int *N2, int *M2, int *P) argument
[all...]
H A Dnv04.c35 int N1, M1, N2, M2, P; local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P);
42 pv->M2 = M2;
H A Dnv40.c62 int M2 = (coef & 0x00ff0000) >> 16; local
71 if (M2)
72 khz = khz * N2 / M2;
125 int *N1, int *M1, int *N2, int *M2, int *log2P)
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P);
151 int N1, M1, N2, M2, log2P; local
156 &N1, &M1, &N2, &M2, &log2P);
160 if (N2 == M2) {
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, int *N1, int *M1, int *N2, int *M2, int *log2P) argument
H A Dnv50.c166 int N1, N2, M1, M2; local
175 M2 = (coef & 0x00ff0000) >> 16;
181 if (M2)
182 freq = freq * N2 / M2;
/linux-master/arch/arm64/crypto/
H A Dpolyval-ce-core.S40 M2 .req v2 label
223 ld1 {M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
251 karatsuba1 M2 KEY6
278 ld1 {M0.16b, M1.16b, M2.16b, M3.16b}, [MSG], #64
282 karatsuba1 M2 KEY6
/linux-master/arch/sparc/kernel/
H A Dtraps_64.c1096 #define M2 144 macro
1101 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1102 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 1
[all...]
/linux-master/arch/x86/crypto/
H A Dpoly1305-x86_64-cryptogams.pl2208 my ($M0,$M1,$M2,$M3,$M4) = map("%zmm$_",(25..29));
2299 vpmuludq $T1,$R1,$M2
2305 vpaddq $M2,$D2,$D2 # d2 += r1'*r1
2313 vpmuludq $T2,$R0,$M2
2319 vpaddq $M2,$D2,$D2 # d2 += r2'*r0
2325 vpmuludq $T3,$S4,$M2
2330 vpaddq $M2,$D2,$D2 # d2 += r3'*5*r4
2336 vpmuludq $T4,$S3,$M2
2341 vpaddq $M2,$D2,$D2 # d2 += r2'*5*r3
2371 vpsrlq \$26,$D2,$M2
[all...]
/linux-master/drivers/bus/mhi/
H A Dcommon.h305 mhi_state(M2, "M2") \
/linux-master/drivers/bus/mhi/host/
H A Ddebugfs.c28 seq_printf(m, "M0: %u M2: %u M3: %u", mhi_cntrl->M0, mhi_cntrl->M2,
H A Dinternal.h123 mhi_pm_state(M2, "M2") \
H A Dpm.c34 * POR -> M0 -> M2 --> M0
158 /* NOP for backward compatibility, host allowed to ring DB in M2 state */
334 * transition to M1 state, the host can transition the device to M2 state
350 mhi_cntrl->M2++;
353 /* If there are any pending resources, exit M2 immediately */
357 "Exiting M2, pending_pkts: %d dev_wake: %d\n",
863 /* Take MHI out of M2 state */
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dcrtc.c166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
H A Dhw.c141 pllvals->N2 = pllvals->M2 = 1;
155 pllvals->M2 = (pll1 >> 4) & 0x7;
208 if (!pv->M1 || !pv->M2)
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c210 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
217 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
296 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
363 int N1, M1, N2, M2, P; local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
378 pv.M2 = M2;
H A Dnv50.c41 int N1, M1, N2, M2, P; local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
62 (M2 << 16) | N2);
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgk104.c134 int N2, M2, P2; member in struct:gk104_ram
160 const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
990 int *N2, int *M2, int *P2)
997 *M2 = 1;
1067 &ram->N2, &ram->M2, &ram->P2);
988 gk104_pll_calc_hiclk(int target_khz, int crystal, int *N1, int *fN1, int *M1, int *P1, int *N2, int *M2, int *P2) argument
H A Dramnv40.c40 int N1, M1, N2, M2; local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P);
55 if (N2 == M2) {
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;

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