1/*
2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
3 *
4 *  NOTE:  This header file is not meant to be included directly.
5 */
6
7/* This header file contains assembly-language definitions (assembly
8   macros, etc.) for this specific Xtensa processor's TIE extensions
9   and options.  It is customized to this Xtensa processor configuration.
10
11   Copyright (c) 1999-2015 Cadence Design Systems Inc.
12
13   Permission is hereby granted, free of charge, to any person obtaining
14   a copy of this software and associated documentation files (the
15   "Software"), to deal in the Software without restriction, including
16   without limitation the rights to use, copy, modify, merge, publish,
17   distribute, sublicense, and/or sell copies of the Software, and to
18   permit persons to whom the Software is furnished to do so, subject to
19   the following conditions:
20
21   The above copyright notice and this permission notice shall be included
22   in all copies or substantial portions of the Software.
23
24   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
27   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
28   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
30   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
31
32#ifndef _XTENSA_CORE_TIE_ASM_H
33#define _XTENSA_CORE_TIE_ASM_H
34
35/*  Selection parameter values for save-area save/restore macros:  */
36/*  Option vs. TIE:  */
37#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
38#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
39#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
40/*  Whether used automatically by compiler:  */
41#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
42#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
43#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
44/*  ABI handling across function calls:  */
45#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
46#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
47#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
48#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
49/*  Misc  */
50#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
51#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
52					| ((ccuse) & XTHAL_SAS_ANYCC)  \
53					| ((abi)   & XTHAL_SAS_ANYABI) )
54
55
56    /*
57      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
58      *  (not including zero-overhead loop registers).
59      *  Required parameters:
60      *      ptr         Save area pointer address register (clobbered)
61      *                  (register must contain a 4 byte aligned address).
62      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
63      *                  registers are clobbered, the remaining are unused).
64      *  Optional parameters:
65      *      continue    If macro invoked as part of a larger store sequence, set to 1
66      *                  if this is not the first in the sequence.  Defaults to 0.
67      *      ofs         Offset from start of larger sequence (from value of first ptr
68      *                  in sequence) at which to store.  Defaults to next available space
69      *                  (or 0 if <continue> is 0).
70      *      select      Select what category(ies) of registers to store, as a bitmask
71      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
72      *      alloc       Select what category(ies) of registers to allocate; if any
73      *                  category is selected here that is not in <select>, space for
74      *                  the corresponding registers is skipped without doing any store.
75      */
76    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
77	xchal_sa_start	\continue, \ofs
78	// Optional global registers used by default by the compiler:
79	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
80	xchal_sa_align	\ptr, 0, 1020, 4, 4
81	rur.THREADPTR	\at1		// threadptr option
82	s32i	\at1, \ptr, .Lxchal_ofs_+0
83	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
84	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
85	xchal_sa_align	\ptr, 0, 1020, 4, 4
86	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
87	.endif
88	// Optional caller-saved registers used by default by the compiler:
89	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
90	xchal_sa_align	\ptr, 0, 1016, 4, 4
91	rsr.ACCLO	\at1		// MAC16 option
92	s32i	\at1, \ptr, .Lxchal_ofs_+0
93	rsr.ACCHI	\at1		// MAC16 option
94	s32i	\at1, \ptr, .Lxchal_ofs_+4
95	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
96	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
97	xchal_sa_align	\ptr, 0, 1016, 4, 4
98	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
99	.endif
100	// Optional caller-saved registers not used by default by the compiler:
101	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
102	xchal_sa_align	\ptr, 0, 1000, 4, 4
103	rsr.BR	\at1		// boolean option
104	s32i	\at1, \ptr, .Lxchal_ofs_+0
105	rsr.SCOMPARE1	\at1		// conditional store option
106	s32i	\at1, \ptr, .Lxchal_ofs_+4
107	rsr.M0	\at1		// MAC16 option
108	s32i	\at1, \ptr, .Lxchal_ofs_+8
109	rsr.M1	\at1		// MAC16 option
110	s32i	\at1, \ptr, .Lxchal_ofs_+12
111	rsr.M2	\at1		// MAC16 option
112	s32i	\at1, \ptr, .Lxchal_ofs_+16
113	rsr.M3	\at1		// MAC16 option
114	s32i	\at1, \ptr, .Lxchal_ofs_+20
115	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
116	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
117	xchal_sa_align	\ptr, 0, 1000, 4, 4
118	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
119	.endif
120    .endm	// xchal_ncp_store
121
122    /*
123      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
124      *  (not including zero-overhead loop registers).
125      *  Required parameters:
126      *      ptr         Save area pointer address register (clobbered)
127      *                  (register must contain a 4 byte aligned address).
128      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
129      *                  registers are clobbered, the remaining are unused).
130      *  Optional parameters:
131      *      continue    If macro invoked as part of a larger load sequence, set to 1
132      *                  if this is not the first in the sequence.  Defaults to 0.
133      *      ofs         Offset from start of larger sequence (from value of first ptr
134      *                  in sequence) at which to load.  Defaults to next available space
135      *                  (or 0 if <continue> is 0).
136      *      select      Select what category(ies) of registers to load, as a bitmask
137      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
138      *      alloc       Select what category(ies) of registers to allocate; if any
139      *                  category is selected here that is not in <select>, space for
140      *                  the corresponding registers is skipped without doing any load.
141      */
142    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
143	xchal_sa_start	\continue, \ofs
144	// Optional global registers used by default by the compiler:
145	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
146	xchal_sa_align	\ptr, 0, 1020, 4, 4
147	l32i	\at1, \ptr, .Lxchal_ofs_+0
148	wur.THREADPTR	\at1		// threadptr option
149	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
150	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
151	xchal_sa_align	\ptr, 0, 1020, 4, 4
152	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
153	.endif
154	// Optional caller-saved registers used by default by the compiler:
155	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
156	xchal_sa_align	\ptr, 0, 1016, 4, 4
157	l32i	\at1, \ptr, .Lxchal_ofs_+0
158	wsr.ACCLO	\at1		// MAC16 option
159	l32i	\at1, \ptr, .Lxchal_ofs_+4
160	wsr.ACCHI	\at1		// MAC16 option
161	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
162	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
163	xchal_sa_align	\ptr, 0, 1016, 4, 4
164	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
165	.endif
166	// Optional caller-saved registers not used by default by the compiler:
167	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
168	xchal_sa_align	\ptr, 0, 1000, 4, 4
169	l32i	\at1, \ptr, .Lxchal_ofs_+0
170	wsr.BR	\at1		// boolean option
171	l32i	\at1, \ptr, .Lxchal_ofs_+4
172	wsr.SCOMPARE1	\at1		// conditional store option
173	l32i	\at1, \ptr, .Lxchal_ofs_+8
174	wsr.M0	\at1		// MAC16 option
175	l32i	\at1, \ptr, .Lxchal_ofs_+12
176	wsr.M1	\at1		// MAC16 option
177	l32i	\at1, \ptr, .Lxchal_ofs_+16
178	wsr.M2	\at1		// MAC16 option
179	l32i	\at1, \ptr, .Lxchal_ofs_+20
180	wsr.M3	\at1		// MAC16 option
181	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
182	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
183	xchal_sa_align	\ptr, 0, 1000, 4, 4
184	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
185	.endif
186    .endm	// xchal_ncp_load
187
188
189#define XCHAL_NCP_NUM_ATMPS	1
190
191    /*
192     *  Macro to store the state of TIE coprocessor AudioEngineLX.
193     *  Required parameters:
194     *      ptr         Save area pointer address register (clobbered)
195     *                  (register must contain a 8 byte aligned address).
196     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
197     *                  registers are clobbered, the remaining are unused).
198     *  Optional parameters are the same as for xchal_ncp_store.
199     */
200#define xchal_cp_AudioEngineLX_store	xchal_cp1_store
201    .macro	xchal_cp1_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
202	xchal_sa_start \continue, \ofs
203	// Custom caller-saved registers not used by default by the compiler:
204	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
205	xchal_sa_align	\ptr, 0, 0, 8, 8
206	rur.AE_OVF_SAR	\at1		// ureg 240
207	s32i	\at1, \ptr, .Lxchal_ofs_+0
208	rur.AE_BITHEAD	\at1		// ureg 241
209	s32i	\at1, \ptr, .Lxchal_ofs_+4
210	rur.AE_TS_FTS_BU_BP	\at1		// ureg 242
211	s32i	\at1, \ptr, .Lxchal_ofs_+8
212	rur.AE_SD_NO	\at1		// ureg 243
213	s32i	\at1, \ptr, .Lxchal_ofs_+12
214	rur.AE_CBEGIN0	\at1		// ureg 246
215	s32i	\at1, \ptr, .Lxchal_ofs_+16
216	rur.AE_CEND0	\at1		// ureg 247
217	s32i	\at1, \ptr, .Lxchal_ofs_+20
218	ae_sp24x2s.i	aep0, \ptr, .Lxchal_ofs_+24
219	ae_sp24x2s.i	aep1, \ptr, .Lxchal_ofs_+32
220	ae_sp24x2s.i	aep2, \ptr, .Lxchal_ofs_+40
221	ae_sp24x2s.i	aep3, \ptr, .Lxchal_ofs_+48
222	ae_sp24x2s.i	aep4, \ptr, .Lxchal_ofs_+56
223	addi	\ptr, \ptr, 64
224	ae_sp24x2s.i	aep5, \ptr, .Lxchal_ofs_+0
225	ae_sp24x2s.i	aep6, \ptr, .Lxchal_ofs_+8
226	ae_sp24x2s.i	aep7, \ptr, .Lxchal_ofs_+16
227	ae_sq56s.i	aeq0, \ptr, .Lxchal_ofs_+24
228	ae_sq56s.i	aeq1, \ptr, .Lxchal_ofs_+32
229	ae_sq56s.i	aeq2, \ptr, .Lxchal_ofs_+40
230	ae_sq56s.i	aeq3, \ptr, .Lxchal_ofs_+48
231	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 64
232	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 56
233	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
234	xchal_sa_align	\ptr, 0, 0, 8, 8
235	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 120
236	.endif
237    .endm	// xchal_cp1_store
238
239    /*
240     *  Macro to load the state of TIE coprocessor AudioEngineLX.
241     *  Required parameters:
242     *      ptr         Save area pointer address register (clobbered)
243     *                  (register must contain a 8 byte aligned address).
244     *      at1..at4    Four temporary address registers (first XCHAL_CP1_NUM_ATMPS
245     *                  registers are clobbered, the remaining are unused).
246     *  Optional parameters are the same as for xchal_ncp_load.
247     */
248#define xchal_cp_AudioEngineLX_load	xchal_cp1_load
249    .macro	xchal_cp1_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
250	xchal_sa_start \continue, \ofs
251	// Custom caller-saved registers not used by default by the compiler:
252	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
253	xchal_sa_align	\ptr, 0, 0, 8, 8
254	l32i	\at1, \ptr, .Lxchal_ofs_+0
255	wur.AE_OVF_SAR	\at1		// ureg 240
256	l32i	\at1, \ptr, .Lxchal_ofs_+4
257	wur.AE_BITHEAD	\at1		// ureg 241
258	l32i	\at1, \ptr, .Lxchal_ofs_+8
259	wur.AE_TS_FTS_BU_BP	\at1		// ureg 242
260	l32i	\at1, \ptr, .Lxchal_ofs_+12
261	wur.AE_SD_NO	\at1		// ureg 243
262	l32i	\at1, \ptr, .Lxchal_ofs_+16
263	wur.AE_CBEGIN0	\at1		// ureg 246
264	l32i	\at1, \ptr, .Lxchal_ofs_+20
265	wur.AE_CEND0	\at1		// ureg 247
266	ae_lp24x2.i	aep0, \ptr, .Lxchal_ofs_+24
267	ae_lp24x2.i	aep1, \ptr, .Lxchal_ofs_+32
268	ae_lp24x2.i	aep2, \ptr, .Lxchal_ofs_+40
269	ae_lp24x2.i	aep3, \ptr, .Lxchal_ofs_+48
270	ae_lp24x2.i	aep4, \ptr, .Lxchal_ofs_+56
271	addi	\ptr, \ptr, 64
272	ae_lp24x2.i	aep5, \ptr, .Lxchal_ofs_+0
273	ae_lp24x2.i	aep6, \ptr, .Lxchal_ofs_+8
274	ae_lp24x2.i	aep7, \ptr, .Lxchal_ofs_+16
275	addi	\ptr, \ptr, 24
276	ae_lq56.i	aeq0, \ptr, .Lxchal_ofs_+0
277	ae_lq56.i	aeq1, \ptr, .Lxchal_ofs_+8
278	ae_lq56.i	aeq2, \ptr, .Lxchal_ofs_+16
279	ae_lq56.i	aeq3, \ptr, .Lxchal_ofs_+24
280	.set	.Lxchal_pofs_, .Lxchal_pofs_ + 88
281	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 32
282	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
283	xchal_sa_align	\ptr, 0, 0, 8, 8
284	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 120
285	.endif
286    .endm	// xchal_cp1_load
287
288#define XCHAL_CP1_NUM_ATMPS	1
289#define XCHAL_SA_NUM_ATMPS	1
290
291	/*  Empty macros for unconfigured coprocessors:  */
292	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
293	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
294	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
295	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
296	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
297	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
298	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
299	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
300	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
301	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
302	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
303	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
304	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
305	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
306
307#endif /*_XTENSA_CORE_TIE_ASM_H*/
308
309