1/* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "nouveau_drv.h" 26#include "hw.h" 27 28#include <subdev/bios/pll.h> 29#include <nvif/timer.h> 30 31#define CHIPSET_NFORCE 0x01a0 32#define CHIPSET_NFORCE2 0x01f0 33 34/* 35 * misc hw access wrappers/control functions 36 */ 37 38void 39NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) 40{ 41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); 43} 44 45uint8_t 46NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) 47{ 48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); 49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); 50} 51 52void 53NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) 54{ 55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); 57} 58 59uint8_t 60NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) 61{ 62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); 63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); 64} 65 66/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) 67 * it affects only the 8 bit vga io regs, which we access using mmio at 68 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* 69 * in general, the set value of cr44 does not matter: reg access works as 70 * expected and values can be set for the appropriate head by using a 0x2000 71 * offset as required 72 * however: 73 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and 74 * cr44 must be set to 0 or 3 for accessing values on the correct head 75 * through the common 0xc03c* addresses 76 * b) in tied mode (4) head B is programmed to the values set on head A, and 77 * access using the head B addresses can have strange results, ergo we leave 78 * tied mode in init once we know to what cr44 should be restored on exit 79 * 80 * the owner parameter is slightly abused: 81 * 0 and 1 are treated as head values and so the set value is (owner * 3) 82 * other values are treated as literal values to set 83 */ 84void 85NVSetOwner(struct drm_device *dev, int owner) 86{ 87 struct nouveau_drm *drm = nouveau_drm(dev); 88 89 if (owner == 1) 90 owner *= 3; 91 92 if (drm->client.device.info.chipset == 0x11) { 93 /* This might seem stupid, but the blob does it and 94 * omitting it often locks the system up. 95 */ 96 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 97 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); 98 } 99 100 /* CR44 is always changed on CRTC0 */ 101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 102 103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ 104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 106 } 107} 108 109void 110NVBlankScreen(struct drm_device *dev, int head, bool blank) 111{ 112 unsigned char seq1; 113 114 if (nv_two_heads(dev)) 115 NVSetOwner(dev, head); 116 117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); 118 119 NVVgaSeqReset(dev, head, true); 120 if (blank) 121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); 122 else 123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); 124 NVVgaSeqReset(dev, head, false); 125} 126 127/* 128 * PLL getting 129 */ 130 131static void 132nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 133 uint32_t pll2, struct nvkm_pll_vals *pllvals) 134{ 135 struct nouveau_drm *drm = nouveau_drm(dev); 136 137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 138 139 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ 140 pllvals->log2P = (pll1 >> 16) & 0x7; 141 pllvals->N2 = pllvals->M2 = 1; 142 143 if (reg1 <= 0x405c) { 144 pllvals->NM1 = pll2 & 0xffff; 145 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ 146 if (!(pll1 & 0x1100)) 147 pllvals->NM2 = pll2 >> 16; 148 } else { 149 pllvals->NM1 = pll1 & 0xffff; 150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 151 pllvals->NM2 = pll2 & 0xffff; 152 else if (drm->client.device.info.chipset == 0x30 || drm->client.device.info.chipset == 0x35) { 153 pllvals->M1 &= 0xf; /* only 4 bits */ 154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 155 pllvals->M2 = (pll1 >> 4) & 0x7; 156 pllvals->N2 = ((pll1 >> 21) & 0x18) | 157 ((pll1 >> 19) & 0x7); 158 } 159 } 160 } 161} 162 163int 164nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 165 struct nvkm_pll_vals *pllvals) 166{ 167 struct nouveau_drm *drm = nouveau_drm(dev); 168 struct nvif_object *device = &drm->client.device.object; 169 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 170 uint32_t reg1, pll1, pll2 = 0; 171 struct nvbios_pll pll_lim; 172 int ret; 173 174 ret = nvbios_pll_parse(bios, plltype, &pll_lim); 175 if (ret || !(reg1 = pll_lim.reg)) 176 return -ENOENT; 177 178 pll1 = nvif_rd32(device, reg1); 179 if (reg1 <= 0x405c) 180 pll2 = nvif_rd32(device, reg1 + 4); 181 else if (nv_two_reg_pll(dev)) { 182 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 183 184 pll2 = nvif_rd32(device, reg2); 185 } 186 187 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 188 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 189 190 /* check whether vpll has been forced into single stage mode */ 191 if (reg1 == NV_PRAMDAC_VPLL_COEFF) { 192 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) 193 pll2 = 0; 194 } else 195 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) 196 pll2 = 0; 197 } 198 199 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 200 pllvals->refclk = pll_lim.refclk; 201 return 0; 202} 203 204int 205nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) 206{ 207 /* Avoid divide by zero if called at an inappropriate time */ 208 if (!pv->M1 || !pv->M2) 209 return 0; 210 211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; 212} 213 214int 215nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) 216{ 217 struct pci_dev *pdev = to_pci_dev(dev->dev); 218 struct nvkm_pll_vals pllvals; 219 int ret; 220 int domain; 221 222 domain = pci_domain_nr(pdev->bus); 223 224 if (plltype == PLL_MEMORY && 225 (pdev->device & 0x0ff0) == CHIPSET_NFORCE) { 226 uint32_t mpllP; 227 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3), 228 0x6c, &mpllP); 229 mpllP = (mpllP >> 8) & 0xf; 230 if (!mpllP) 231 mpllP = 4; 232 233 return 400000 / mpllP; 234 } else 235 if (plltype == PLL_MEMORY && 236 (pdev->device & 0xff0) == CHIPSET_NFORCE2) { 237 uint32_t clock; 238 239 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5), 240 0x4c, &clock); 241 return clock / 1000; 242 } 243 244 ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); 245 if (ret) 246 return ret; 247 248 return nouveau_hw_pllvals_to_clk(&pllvals); 249} 250 251static void 252nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) 253{ 254 /* the vpll on an unused head can come up with a random value, way 255 * beyond the pll limits. for some reason this causes the chip to 256 * lock up when reading the dac palette regs, so set a valid pll here 257 * when such a condition detected. only seen on nv11 to date 258 */ 259 260 struct nouveau_drm *drm = nouveau_drm(dev); 261 struct nvif_device *device = &drm->client.device; 262 struct nvkm_clk *clk = nvxx_clk(device); 263 struct nvkm_bios *bios = nvxx_bios(device); 264 struct nvbios_pll pll_lim; 265 struct nvkm_pll_vals pv; 266 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 267 268 if (nvbios_pll_parse(bios, pll, &pll_lim)) 269 return; 270 nouveau_hw_get_pllvals(dev, pll, &pv); 271 272 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && 273 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && 274 pv.log2P <= pll_lim.max_p) 275 return; 276 277 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); 278 279 /* set lowest clock within static limits */ 280 pv.M1 = pll_lim.vco1.max_m; 281 pv.N1 = pll_lim.vco1.min_n; 282 pv.log2P = pll_lim.max_p_usable; 283 clk->pll_prog(clk, pll_lim.reg, &pv); 284} 285 286/* 287 * vga font save/restore 288 */ 289 290static void nouveau_vga_font_io(struct drm_device *dev, 291 void __iomem *iovram, 292 bool save, unsigned plane) 293{ 294 unsigned i; 295 296 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); 297 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); 298 for (i = 0; i < 16384; i++) { 299 if (save) { 300 nv04_display(dev)->saved_vga_font[plane][i] = 301 ioread32_native(iovram + i * 4); 302 } else { 303 iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], 304 iovram + i * 4); 305 } 306 } 307} 308 309void 310nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 311{ 312 struct nouveau_drm *drm = nouveau_drm(dev); 313 struct pci_dev *pdev = to_pci_dev(dev->dev); 314 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 315 bool graphicsmode; 316 unsigned plane; 317 void __iomem *iovram; 318 319 if (nv_two_heads(dev)) 320 NVSetOwner(dev, 0); 321 322 NVSetEnablePalette(dev, 0, true); 323 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; 324 NVSetEnablePalette(dev, 0, false); 325 326 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 327 return; 328 329 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 330 331 /* map first 64KiB of VRAM, holds VGA fonts etc */ 332 iovram = ioremap(pci_resource_start(pdev, 1), 65536); 333 if (!iovram) { 334 NV_ERROR(drm, "Failed to map VRAM, " 335 "cannot save/restore VGA fonts.\n"); 336 return; 337 } 338 339 if (nv_two_heads(dev)) 340 NVBlankScreen(dev, 1, true); 341 NVBlankScreen(dev, 0, true); 342 343 /* save control regs */ 344 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); 345 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); 346 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); 347 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); 348 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); 349 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); 350 351 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); 352 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); 353 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); 354 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); 355 356 /* store font in planes 0..3 */ 357 for (plane = 0; plane < 4; plane++) 358 nouveau_vga_font_io(dev, iovram, save, plane); 359 360 /* restore control regs */ 361 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); 362 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); 363 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); 364 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); 365 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); 366 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); 367 368 if (nv_two_heads(dev)) 369 NVBlankScreen(dev, 1, false); 370 NVBlankScreen(dev, 0, false); 371 372 iounmap(iovram); 373} 374 375/* 376 * mode state save/load 377 */ 378 379static void 380rd_cio_state(struct drm_device *dev, int head, 381 struct nv04_crtc_reg *crtcstate, int index) 382{ 383 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); 384} 385 386static void 387wr_cio_state(struct drm_device *dev, int head, 388 struct nv04_crtc_reg *crtcstate, int index) 389{ 390 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); 391} 392 393static void 394nv_save_state_ramdac(struct drm_device *dev, int head, 395 struct nv04_mode_state *state) 396{ 397 struct nouveau_drm *drm = nouveau_drm(dev); 398 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 399 int i; 400 401 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 402 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 403 404 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); 405 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 406 if (nv_two_heads(dev)) 407 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 408 if (drm->client.device.info.chipset == 0x11) 409 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 410 411 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 412 413 if (nv_gf4_disp_arch(dev)) 414 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 415 if (drm->client.device.info.chipset >= 0x30) 416 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 417 418 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 419 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); 420 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); 421 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); 422 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); 423 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); 424 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); 425 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); 426 427 for (i = 0; i < 7; i++) { 428 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 429 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); 430 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); 431 } 432 433 if (nv_gf4_disp_arch(dev)) { 434 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); 435 for (i = 0; i < 3; i++) { 436 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); 437 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); 438 } 439 } 440 441 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 442 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); 443 if (!nv_gf4_disp_arch(dev) && head == 0) { 444 /* early chips don't allow access to PRAMDAC_TMDS_* without 445 * the head A FPCLK on (nv11 even locks up) */ 446 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & 447 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); 448 } 449 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); 450 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); 451 452 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); 453 454 if (nv_gf4_disp_arch(dev)) 455 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 456 457 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 458 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 459 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 460 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 461 462 for (i = 0; i < 38; i++) 463 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, 464 NV_PRAMDAC_CTV + 4*i); 465 } 466} 467 468static void 469nv_load_state_ramdac(struct drm_device *dev, int head, 470 struct nv04_mode_state *state) 471{ 472 struct nouveau_drm *drm = nouveau_drm(dev); 473 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 474 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 475 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 476 int i; 477 478 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 479 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 480 481 clk->pll_prog(clk, pllreg, ®p->pllvals); 482 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 483 if (nv_two_heads(dev)) 484 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 485 if (drm->client.device.info.chipset == 0x11) 486 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 487 488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 489 490 if (nv_gf4_disp_arch(dev)) 491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 492 if (drm->client.device.info.chipset >= 0x30) 493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 494 495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); 497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); 498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); 499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); 500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); 501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); 502 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); 503 504 for (i = 0; i < 7; i++) { 505 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); 506 507 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); 508 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); 509 } 510 511 if (nv_gf4_disp_arch(dev)) { 512 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); 513 for (i = 0; i < 3; i++) { 514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); 515 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); 516 } 517 } 518 519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); 520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); 521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); 522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); 523 524 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); 525 526 if (nv_gf4_disp_arch(dev)) 527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 528 529 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 532 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 533 534 for (i = 0; i < 38; i++) 535 NVWriteRAMDAC(dev, head, 536 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); 537 } 538} 539 540static void 541nv_save_state_vga(struct drm_device *dev, int head, 542 struct nv04_mode_state *state) 543{ 544 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 545 int i; 546 547 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); 548 549 for (i = 0; i < 25; i++) 550 rd_cio_state(dev, head, regp, i); 551 552 NVSetEnablePalette(dev, head, true); 553 for (i = 0; i < 21; i++) 554 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); 555 NVSetEnablePalette(dev, head, false); 556 557 for (i = 0; i < 9; i++) 558 regp->Graphics[i] = NVReadVgaGr(dev, head, i); 559 560 for (i = 0; i < 5; i++) 561 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); 562} 563 564static void 565nv_load_state_vga(struct drm_device *dev, int head, 566 struct nv04_mode_state *state) 567{ 568 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 569 int i; 570 571 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); 572 573 for (i = 0; i < 5; i++) 574 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); 575 576 nv_lock_vga_crtc_base(dev, head, false); 577 for (i = 0; i < 25; i++) 578 wr_cio_state(dev, head, regp, i); 579 nv_lock_vga_crtc_base(dev, head, true); 580 581 for (i = 0; i < 9; i++) 582 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); 583 584 NVSetEnablePalette(dev, head, true); 585 for (i = 0; i < 21; i++) 586 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); 587 NVSetEnablePalette(dev, head, false); 588} 589 590static void 591nv_save_state_ext(struct drm_device *dev, int head, 592 struct nv04_mode_state *state) 593{ 594 struct nouveau_drm *drm = nouveau_drm(dev); 595 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 596 int i; 597 598 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 600 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 601 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 602 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 603 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 604 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 605 606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 607 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 608 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 609 610 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 611 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 612 613 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 614 rd_cio_state(dev, head, regp, 0x9f); 615 616 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 619 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 620 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 621 622 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 623 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 624 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 625 626 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 627 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 628 629 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 630 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 631 632 if (nv_two_heads(dev)) 633 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); 634 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); 635 } 636 637 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); 638 639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 640 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 641 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 642 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 643 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 644 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 645 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 646 } 647 /* NV11 and NV20 don't have this, they stop at 0x52. */ 648 if (nv_gf4_disp_arch(dev)) { 649 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); 650 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); 651 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); 652 653 for (i = 0; i < 0x10; i++) 654 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); 655 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); 656 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); 657 658 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); 659 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); 660 } 661 662 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); 663} 664 665static void 666nv_load_state_ext(struct drm_device *dev, int head, 667 struct nv04_mode_state *state) 668{ 669 struct nouveau_drm *drm = nouveau_drm(dev); 670 struct nvif_object *device = &drm->client.device.object; 671 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 672 uint32_t reg900; 673 int i; 674 675 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 676 if (nv_two_heads(dev)) 677 /* setting ENGINE_CTRL (EC) *must* come before 678 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 679 * EC that should not be overwritten by writing stale EC 680 */ 681 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 682 683 nvif_wr32(device, NV_PVIDEO_STOP, 1); 684 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); 685 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); 686 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); 687 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1); 688 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1); 689 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1); 690 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1); 691 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); 692 693 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 694 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 695 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 696 697 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 698 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 699 700 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 701 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 702 703 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 704 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) 705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); 706 else 707 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); 708 } 709 } 710 711 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); 712 713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); 714 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); 715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); 716 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); 717 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); 718 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); 719 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); 720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 721 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 722 723 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) 724 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 725 726 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 727 wr_cio_state(dev, head, regp, 0x9f); 728 729 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 732 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 733 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 734 nv_fix_nv40_hw_cursor(dev, head); 735 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 736 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 738 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 739 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 740 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 741 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 742 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 743 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 744 } 745 /* NV11 and NV20 stop at 0x52. */ 746 if (nv_gf4_disp_arch(dev)) { 747 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 748 /* Not waiting for vertical retrace before modifying 749 CRE_53/CRE_54 causes lockups. */ 750 nvif_msec(&drm->client.device, 650, 751 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 752 break; 753 ); 754 nvif_msec(&drm->client.device, 650, 755 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) 756 break; 757 ); 758 } 759 760 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 761 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 762 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 763 764 for (i = 0; i < 0x10; i++) 765 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); 766 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); 767 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); 768 769 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); 770 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); 771 } 772 773 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); 774} 775 776static void 777nv_save_state_palette(struct drm_device *dev, int head, 778 struct nv04_mode_state *state) 779{ 780 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 781 int head_offset = head * NV_PRMDIO_SIZE, i; 782 783 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 784 NV_PRMDIO_PIXEL_MASK_MASK); 785 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 786 787 for (i = 0; i < 768; i++) { 788 state->crtc_reg[head].DAC[i] = nvif_rd08(device, 789 NV_PRMDIO_PALETTE_DATA + head_offset); 790 } 791 792 NVSetEnablePalette(dev, head, false); 793} 794 795void 796nouveau_hw_load_state_palette(struct drm_device *dev, int head, 797 struct nv04_mode_state *state) 798{ 799 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 800 int head_offset = head * NV_PRMDIO_SIZE, i; 801 802 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, 803 NV_PRMDIO_PIXEL_MASK_MASK); 804 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 805 806 for (i = 0; i < 768; i++) { 807 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, 808 state->crtc_reg[head].DAC[i]); 809 } 810 811 NVSetEnablePalette(dev, head, false); 812} 813 814void nouveau_hw_save_state(struct drm_device *dev, int head, 815 struct nv04_mode_state *state) 816{ 817 struct nouveau_drm *drm = nouveau_drm(dev); 818 819 if (drm->client.device.info.chipset == 0x11) 820 /* NB: no attempt is made to restore the bad pll later on */ 821 nouveau_hw_fix_bad_vpll(dev, head); 822 nv_save_state_ramdac(dev, head, state); 823 nv_save_state_vga(dev, head, state); 824 nv_save_state_palette(dev, head, state); 825 nv_save_state_ext(dev, head, state); 826} 827 828void nouveau_hw_load_state(struct drm_device *dev, int head, 829 struct nv04_mode_state *state) 830{ 831 NVVgaProtect(dev, head, true); 832 nv_load_state_ramdac(dev, head, state); 833 nv_load_state_ext(dev, head, state); 834 nouveau_hw_load_state_palette(dev, head, state); 835 nv_load_state_vga(dev, head, state); 836 NVVgaProtect(dev, head, false); 837} 838