197403Sobrien/* 297403Sobrien * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3169691Skan * 4169691Skan * NOTE: This header file is not meant to be included directly. 597403Sobrien */ 697403Sobrien 797403Sobrien/* This header file contains assembly-language definitions (assembly 897403Sobrien macros, etc.) for this specific Xtensa processor's TIE extensions 997403Sobrien and options. It is customized to this Xtensa processor configuration. 1097403Sobrien 1197403Sobrien Copyright (c) 1999-2015 Cadence Design Systems Inc. 1297403Sobrien 1397403Sobrien Permission is hereby granted, free of charge, to any person obtaining 1497403Sobrien a copy of this software and associated documentation files (the 1597403Sobrien "Software"), to deal in the Software without restriction, including 1697403Sobrien without limitation the rights to use, copy, modify, merge, publish, 1797403Sobrien distribute, sublicense, and/or sell copies of the Software, and to 1897403Sobrien permit persons to whom the Software is furnished to do so, subject to 19169691Skan the following conditions: 2097403Sobrien 2197403Sobrien The above copyright notice and this permission notice shall be included 2297403Sobrien in all copies or substantial portions of the Software. 2397403Sobrien 2497403Sobrien THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 2597403Sobrien EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 2697403Sobrien MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 2797403Sobrien IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 2897403Sobrien CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 2997403Sobrien TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 3097403Sobrien SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 3197403Sobrien 3297403Sobrien#ifndef _XTENSA_CORE_TIE_ASM_H 3397403Sobrien#define _XTENSA_CORE_TIE_ASM_H 3497403Sobrien 3597403Sobrien/* Selection parameter values for save-area save/restore macros: */ 36117397Skan/* Option vs. TIE: */ 37132720Skan#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 38132720Skan#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 39132720Skan#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 40132720Skan/* Whether used automatically by compiler: */ 41132720Skan#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 42132720Skan#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 43132720Skan#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 44132720Skan/* ABI handling across function calls: */ 45117397Skan#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 46132720Skan#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 4797403Sobrien#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 48132720Skan#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 49132720Skan/* Misc */ 50132720Skan#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 51117397Skan#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 52117397Skan | ((ccuse) & XTHAL_SAS_ANYCC) \ 53117397Skan | ((abi) & XTHAL_SAS_ANYABI) ) 54117397Skan 55132720Skan 56117397Skan /* 57117397Skan * Macro to store all non-coprocessor (extra) custom TIE and optional state 58117397Skan * (not including zero-overhead loop registers). 59132720Skan * Required parameters: 60132720Skan * ptr Save area pointer address register (clobbered) 61117397Skan * (register must contain a 4 byte aligned address). 62117397Skan * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 63132720Skan * registers are clobbered, the remaining are unused). 64117397Skan * Optional parameters: 65132720Skan * continue If macro invoked as part of a larger store sequence, set to 1 66132720Skan * if this is not the first in the sequence. Defaults to 0. 67117397Skan * ofs Offset from start of larger sequence (from value of first ptr 68132720Skan * in sequence) at which to store. Defaults to next available space 69117397Skan * (or 0 if <continue> is 0). 70117397Skan * select Select what category(ies) of registers to store, as a bitmask 71117397Skan * (see XTHAL_SAS_xxx constants). Defaults to all registers. 72169691Skan * alloc Select what category(ies) of registers to allocate; if any 73132720Skan * category is selected here that is not in <select>, space for 74169691Skan * the corresponding registers is skipped without doing any store. 7597403Sobrien */ 76132720Skan .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 77132720Skan xchal_sa_start \continue, \ofs 78132720Skan // Optional caller-saved registers used by default by the compiler: 79132720Skan .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 80132720Skan xchal_sa_align \ptr, 0, 1016, 4, 4 81132720Skan rsr.ACCLO \at1 // MAC16 option 82117397Skan s32i \at1, \ptr, .Lxchal_ofs_+0 83132720Skan rsr.ACCHI \at1 // MAC16 option 84132720Skan s32i \at1, \ptr, .Lxchal_ofs_+4 85132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 86132720Skan .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 87132720Skan xchal_sa_align \ptr, 0, 1016, 4, 4 88132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 89132720Skan .endif 90132720Skan // Optional caller-saved registers not used by default by the compiler: 91117397Skan .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92132720Skan xchal_sa_align \ptr, 0, 1004, 4, 4 93132720Skan rsr.SCOMPARE1 \at1 // conditional store option 94132720Skan s32i \at1, \ptr, .Lxchal_ofs_+0 95132720Skan rsr.M0 \at1 // MAC16 option 96132720Skan s32i \at1, \ptr, .Lxchal_ofs_+4 97132720Skan rsr.M1 \at1 // MAC16 option 98169691Skan s32i \at1, \ptr, .Lxchal_ofs_+8 99169691Skan rsr.M2 \at1 // MAC16 option 100132720Skan s32i \at1, \ptr, .Lxchal_ofs_+12 101132720Skan rsr.M3 \at1 // MAC16 option 102132720Skan s32i \at1, \ptr, .Lxchal_ofs_+16 103132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 104132720Skan .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 105132720Skan xchal_sa_align \ptr, 0, 1004, 4, 4 106132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 107169691Skan .endif 108169691Skan .endm // xchal_ncp_store 109132720Skan 110132720Skan /* 111117397Skan * Macro to load all non-coprocessor (extra) custom TIE and optional state 112132720Skan * (not including zero-overhead loop registers). 113132720Skan * Required parameters: 114132720Skan * ptr Save area pointer address register (clobbered) 115132720Skan * (register must contain a 4 byte aligned address). 116132720Skan * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 117132720Skan * registers are clobbered, the remaining are unused). 118132720Skan * Optional parameters: 119132720Skan * continue If macro invoked as part of a larger load sequence, set to 1 120132720Skan * if this is not the first in the sequence. Defaults to 0. 121117397Skan * ofs Offset from start of larger sequence (from value of first ptr 122132720Skan * in sequence) at which to load. Defaults to next available space 123132720Skan * (or 0 if <continue> is 0). 124132720Skan * select Select what category(ies) of registers to load, as a bitmask 125132720Skan * (see XTHAL_SAS_xxx constants). Defaults to all registers. 126132720Skan * alloc Select what category(ies) of registers to allocate; if any 127132720Skan * category is selected here that is not in <select>, space for 128132720Skan * the corresponding registers is skipped without doing any load. 129132720Skan */ 130132720Skan .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 131132720Skan xchal_sa_start \continue, \ofs 132132720Skan // Optional caller-saved registers used by default by the compiler: 133117397Skan .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 134117397Skan xchal_sa_align \ptr, 0, 1016, 4, 4 135132720Skan l32i \at1, \ptr, .Lxchal_ofs_+0 136132720Skan wsr.ACCLO \at1 // MAC16 option 137132720Skan l32i \at1, \ptr, .Lxchal_ofs_+4 138132720Skan wsr.ACCHI \at1 // MAC16 option 139132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 140132720Skan .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 141132720Skan xchal_sa_align \ptr, 0, 1016, 4, 4 142132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 143132720Skan .endif 144132720Skan // Optional caller-saved registers not used by default by the compiler: 145132720Skan .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 146132720Skan xchal_sa_align \ptr, 0, 1004, 4, 4 147132720Skan l32i \at1, \ptr, .Lxchal_ofs_+0 148132720Skan wsr.SCOMPARE1 \at1 // conditional store option 149132720Skan l32i \at1, \ptr, .Lxchal_ofs_+4 150132720Skan wsr.M0 \at1 // MAC16 option 151132720Skan l32i \at1, \ptr, .Lxchal_ofs_+8 152117397Skan wsr.M1 \at1 // MAC16 option 153132720Skan l32i \at1, \ptr, .Lxchal_ofs_+12 154132720Skan wsr.M2 \at1 // MAC16 option 155132720Skan l32i \at1, \ptr, .Lxchal_ofs_+16 156132720Skan wsr.M3 \at1 // MAC16 option 157132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 158132720Skan .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 159132720Skan xchal_sa_align \ptr, 0, 1004, 4, 4 160132720Skan .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 161132720Skan .endif 162132720Skan .endm // xchal_ncp_load 163132720Skan 164132720Skan 165132720Skan#define XCHAL_NCP_NUM_ATMPS 1 166132720Skan 167132720Skan#define XCHAL_SA_NUM_ATMPS 1 168132720Skan 169132720Skan#endif /*_XTENSA_CORE_TIE_ASM_H*/ 170132720Skan 171132720Skan