1/* 2 * This header file contains assembly-language definitions (assembly 3 * macros, etc.) for this specific Xtensa processor's TIE extensions 4 * and options. It is customized to this Xtensa processor configuration. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 1999-2007 Tensilica Inc. 11 */ 12 13#ifndef _XTENSA_CORE_TIE_ASM_H 14#define _XTENSA_CORE_TIE_ASM_H 15 16/* Selection parameter values for save-area save/restore macros: */ 17/* Option vs. TIE: */ 18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 20/* Whether used automatically by compiler: */ 21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 23/* ABI handling across function calls: */ 24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 27/* Misc */ 28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 29 30 31 32/* Macro to save all non-coprocessor (extra) custom TIE and optional state 33 * (not including zero-overhead loop registers). 34 * Save area ptr (clobbered): ptr (1 byte aligned) 35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 36 */ 37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 38 xchal_sa_start \continue, \ofs 39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 40 xchal_sa_align \ptr, 0, 1024-8, 4, 4 41 rsr \at1, ACCLO // MAC16 accumulator 42 rsr \at2, ACCHI 43 s32i \at1, \ptr, .Lxchal_ofs_ + 0 44 s32i \at2, \ptr, .Lxchal_ofs_ + 4 45 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 46 .endif 47 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 48 xchal_sa_align \ptr, 0, 1024-16, 4, 4 49 rsr \at1, M0 // MAC16 registers 50 rsr \at2, M1 51 s32i \at1, \ptr, .Lxchal_ofs_ + 0 52 s32i \at2, \ptr, .Lxchal_ofs_ + 4 53 rsr \at1, M2 54 rsr \at2, M3 55 s32i \at1, \ptr, .Lxchal_ofs_ + 8 56 s32i \at2, \ptr, .Lxchal_ofs_ + 12 57 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 58 .endif 59 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 60 xchal_sa_align \ptr, 0, 1024-4, 4, 4 61 rsr \at1, SCOMPARE1 // conditional store option 62 s32i \at1, \ptr, .Lxchal_ofs_ + 0 63 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 64 .endif 65 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 66 xchal_sa_align \ptr, 0, 1024-4, 4, 4 67 rur \at1, THREADPTR // threadptr option 68 s32i \at1, \ptr, .Lxchal_ofs_ + 0 69 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 70 .endif 71 .endm // xchal_ncp_store 72 73/* Macro to save all non-coprocessor (extra) custom TIE and optional state 74 * (not including zero-overhead loop registers). 75 * Save area ptr (clobbered): ptr (1 byte aligned) 76 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 77 */ 78 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 79 xchal_sa_start \continue, \ofs 80 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 81 xchal_sa_align \ptr, 0, 1024-8, 4, 4 82 l32i \at1, \ptr, .Lxchal_ofs_ + 0 83 l32i \at2, \ptr, .Lxchal_ofs_ + 4 84 wsr \at1, ACCLO // MAC16 accumulator 85 wsr \at2, ACCHI 86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 87 .endif 88 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 89 xchal_sa_align \ptr, 0, 1024-16, 4, 4 90 l32i \at1, \ptr, .Lxchal_ofs_ + 0 91 l32i \at2, \ptr, .Lxchal_ofs_ + 4 92 wsr \at1, M0 // MAC16 registers 93 wsr \at2, M1 94 l32i \at1, \ptr, .Lxchal_ofs_ + 8 95 l32i \at2, \ptr, .Lxchal_ofs_ + 12 96 wsr \at1, M2 97 wsr \at2, M3 98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 99 .endif 100 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 101 xchal_sa_align \ptr, 0, 1024-4, 4, 4 102 l32i \at1, \ptr, .Lxchal_ofs_ + 0 103 wsr \at1, SCOMPARE1 // conditional store option 104 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 105 .endif 106 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 107 xchal_sa_align \ptr, 0, 1024-4, 4, 4 108 l32i \at1, \ptr, .Lxchal_ofs_ + 0 109 wur \at1, THREADPTR // threadptr option 110 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 111 .endif 112 .endm // xchal_ncp_load 113 114 115 116#define XCHAL_NCP_NUM_ATMPS 2 117 118 119#define XCHAL_SA_NUM_ATMPS 2 120 121#endif /*_XTENSA_CORE_TIE_ASM_H*/ 122 123