Searched refs:BASE (Results 1 - 25 of 87) sorted by last modified time

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/linux-master/fs/xfs/libxfs/
H A Dxfs_da_btree.h165 #define XFS_DA_LOGOFF(BASE, ADDR) ((char *)(ADDR) - (char *)(BASE))
166 #define XFS_DA_LOGRANGE(BASE, ADDR, SIZE) \
167 (uint)(XFS_DA_LOGOFF(BASE, ADDR)), \
168 (uint)(XFS_DA_LOGOFF(BASE, ADDR)+(SIZE)-1)
/linux-master/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c926 KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE);
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn32.c38 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
H A Ddmub_dcn35.c38 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
H A Ddmub_dcn31.c37 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c109 #define BASE(seg) BASE_INNER(seg) macro
112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
145 REG_STRUCT[id].reg_name = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c129 #define BASE(seg) BASE_INNER(seg) macro
132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
161 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
165 REG_STRUCT[id].reg_name = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c115 #define BASE(seg) BASE_INNER(seg) macro
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
149 REG_STRUCT[id].reg_name = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c114 #define BASE(seg) BASE_INNER(seg) macro
117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
120 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
126 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
137 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
148 REG_STRUCT[id].reg_name = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c146 #define BASE(seg) BASE_INNER(seg) macro
149 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
153 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
161 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
169 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
180 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
184 .reg_name[id] = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c159 #define BASE(seg) BASE_INNER(seg) macro
162 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
166 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
174 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
193 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
197 .reg_name[id] = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c143 #define BASE(seg) BASE_INNER(seg) macro
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
177 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 .reg_name[id] = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c126 #define BASE(seg) BASE_INNER(seg) macro
129 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
133 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
141 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
160 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
164 .reg_name[id] = BASE(re
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c170 #define BASE(seg) BASE_INNER(seg) macro
173 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
179 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
182 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
185 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
189 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
193 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
197 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
204 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
878 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_ID
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c115 #define BASE(seg) BASE_INNER(seg) macro
118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
126 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
138 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
149 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 .reg_name[id] = BASE(m
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c99 #define BASE(seg) BASE_INNER(seg) macro
102 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
118 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
122 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
1083 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c249 #define BASE(seg) BASE_INNER(seg) macro
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
271 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
275 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
841 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c126 #define BASE(seg) BASE_INNER(seg) macro
129 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
133 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
146 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
986 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c108 #define BASE(seg) \ macro
112 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
116 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
125 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
817 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c133 #define BASE(seg) \ macro
137 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
141 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
774 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c52 #define BASE(seg) BASE_INNER(seg) macro
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.c51 #define BASE(seg) BASE_INNER(seg) macro
53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c93 #define BASE(seg) BASE_INNER(seg) macro
96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c56 #define BASE(seg) BASE_INNER(seg) macro
59 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c47 #define BASE(seg) BASE_INNER(seg) macro
50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \

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