/linux-master/drivers/media/platform/ti/omap3isp/ |
H A D | isp.c | 159 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider) argument 161 switch (xclk->id) { 163 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 168 isp_reg_clr_set(xclk->isp, OMAP3_ISP_IOMEM_MAIN, ISP_TCTRL_CTRL, 177 struct isp_xclk *xclk = to_isp_xclk(hw); local 179 omap3isp_get(xclk->isp); 186 struct isp_xclk *xclk = to_isp_xclk(hw); local 188 omap3isp_put(xclk->isp); 193 struct isp_xclk *xclk = to_isp_xclk(hw); local 196 spin_lock_irqsave(&xclk 206 struct isp_xclk *xclk = to_isp_xclk(hw); local 218 struct isp_xclk *xclk = to_isp_xclk(hw); local 253 struct isp_xclk *xclk = to_isp_xclk(hw); local 305 struct isp_xclk *xclk = &isp->xclks[i]; local 344 struct isp_xclk *xclk = &isp->xclks[i]; local [all...] |
/linux-master/drivers/media/usb/em28xx/ |
H A D | em28xx-camera.c | 323 * need to use a lower xclk frequency. 324 * Yet, it would be possible to adjust xclk depending on the 328 dev->board.xclk = EM28XX_XCLK_FREQUENCY_4_3MHZ; 329 em28xx_write_reg(dev, EM28XX_R0F_XCLK, dev->board.xclk); 355 dev->board.xclk = EM28XX_XCLK_FREQUENCY_48MHZ; 356 em28xx_write_reg(dev, EM28XX_R0F_XCLK, dev->board.xclk); 380 * - adjust bridge xclk 398 dev->board.xclk = EM28XX_XCLK_FREQUENCY_24MHZ; 399 em28xx_write_reg(dev, EM28XX_R0F_XCLK, dev->board.xclk);
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H A D | em28xx-input.c | 389 /* Adjust xclk based on IR table for RC5/NEC tables */ 391 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE; 395 dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE; 404 em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk, 418 /* Adjust xclk and set type based on IR table for RC5/NEC/RC6 tables */ 420 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE; 424 dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE; 429 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE; 440 em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk,
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H A D | em28xx-cards.c | 674 .xclk = EM28XX_XCLK_FREQUENCY_20MHZ, 710 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ, 719 .xclk = EM28XX_XCLK_FREQUENCY_48MHZ, 1042 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ, 1136 .xclk = EM28XX_XCLK_I2S_MSB_TIMING | 1169 .xclk = EM28XX_XCLK_IR_RC5_MODE | 1195 .xclk = EM28XX_XCLK_IR_RC5_MODE | 1470 .xclk = EM28XX_XCLK_FREQUENCY_12MHZ, /* NEC IR */ 1726 .xclk = EM28XX_XCLK_FREQUENCY_10MHZ, 1834 .xclk 2859 u8 xclk = board->xclk, i2c_speed = board->i2c_speed; local [all...] |
H A D | em28xx-core.c | 417 u8 xclk; local 437 xclk = dev->board.xclk & 0x7f; 439 xclk |= EM28XX_XCLK_AUDIO_UNMUTE; 441 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
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H A D | em28xx.h | 497 unsigned char xclk, i2c_speed; member in struct:em28xx_board
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/linux-master/drivers/clk/ |
H A D | clk-max9485.c | 78 struct clk *xclk; member in struct:max9485_driver_data 268 drvdata->xclk = devm_clk_get(dev, "xclk"); 269 if (IS_ERR(drvdata->xclk)) 270 return PTR_ERR(drvdata->xclk); 272 xclk_name = __clk_get_name(drvdata->xclk);
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | sumo_smc.c | 145 u32 xclk = radeon_get_xclk(rdev); local 150 period = 100 * (xclk / 100 / sumo_power_of_4(unit));
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H A D | sumo_dpm.c | 121 u32 xclk = radeon_get_xclk(rdev); local 124 xclk, 16, &p, &u); 132 u32 xclk = radeon_get_xclk(rdev); local 135 r600_calculate_u_and_p(1, xclk, 14, &p, &u); 152 u32 xclk = radeon_get_xclk(rdev); local 171 xclk, 16, &p, &u); 177 xclk, 16, &p, &u); 316 u32 xclk = radeon_get_xclk(rdev); local 322 xclk, 16, &pi->bsp, &pi->bsu); 325 xclk, 1 463 u32 xclk = radeon_get_xclk(rdev); local 925 u32 xclk = radeon_get_xclk(rdev); local 971 u32 xclk = radeon_get_xclk(rdev); local [all...] |
H A D | trinity_dpm.c | 320 u32 xclk = radeon_get_xclk(rdev); local 337 r600_calculate_u_and_p(500, xclk, 16, &p, &u); 839 u32 xclk = radeon_get_xclk(rdev); local 841 r600_calculate_u_and_p(interval, xclk, 16, &p, &u); 982 u32 xclk = radeon_get_xclk(rdev); local 985 r600_calculate_u_and_p(400, xclk, 16, &p, &u);
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H A D | rv770_dpm.c | 820 u32 xclk = radeon_get_xclk(rdev); local 823 xclk, 829 xclk,
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/linux-master/drivers/media/i2c/ |
H A D | st-mipid02.c | 95 struct clk *xclk; member in struct:mipid02_dev 256 ret = clk_prepare_enable(bridge->xclk); 281 clk_disable_unprepare(bridge->xclk); 288 clk_disable_unprepare(bridge->xclk); 824 bridge->xclk = devm_clk_get(dev, "xclk"); 825 if (IS_ERR(bridge->xclk)) { 826 dev_err(dev, "failed to get xclk\n"); 827 return PTR_ERR(bridge->xclk); 830 clk_freq = clk_get_rate(bridge->xclk); [all...] |
H A D | imx219.c | 320 struct clk *xclk; /* system clock to IMX219 */ member in struct:imx219 971 ret = clk_prepare_enable(imx219->xclk); 997 clk_disable_unprepare(imx219->xclk); 1116 /* Get system clock (xclk) */ 1117 imx219->xclk = devm_clk_get(dev, NULL); 1118 if (IS_ERR(imx219->xclk)) { 1119 dev_err(dev, "failed to get xclk\n"); 1120 return PTR_ERR(imx219->xclk); 1123 imx219->xclk_freq = clk_get_rate(imx219->xclk); 1125 dev_err(dev, "xclk frequenc [all...] |
H A D | ov6650.c | 896 const struct ov6650_xclk *xclk = NULL; local 913 xclk = &ov6650_xclk[i]; 918 for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) { 923 xclk = &ov6650_xclk[i]; 925 xclk->rate / 1000); 928 if (!xclk) { 968 ret = ov6650_prog_dflt(client, xclk->clkrc);
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H A D | imx214.c | 57 struct clk *xclk; member in struct:imx214 464 ret = clk_prepare_enable(imx214->xclk); 485 clk_disable_unprepare(imx214->xclk); 1039 imx214->xclk = devm_clk_get(dev, NULL); 1040 if (IS_ERR(imx214->xclk)) { 1041 dev_err(dev, "could not get xclk"); 1042 return PTR_ERR(imx214->xclk); 1045 ret = clk_set_rate(imx214->xclk, IMX214_DEFAULT_CLK_FREQ); 1047 dev_err(dev, "could not set xclk frequency\n");
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H A D | ov7251.c | 133 struct clk *xclk; member in struct:ov7251 918 ret = clk_prepare_enable(ov7251->xclk); 938 clk_disable_unprepare(ov7251->xclk); 952 clk_disable_unprepare(ov7251->xclk); 1641 /* get system clock (xclk) */ 1642 ov7251->xclk = devm_clk_get_optional(dev, NULL); 1643 if (IS_ERR(ov7251->xclk)) 1644 return dev_err_probe(dev, PTR_ERR(ov7251->xclk), 1645 "could not get xclk"); 1654 if (ret && !ov7251->xclk) [all...] |
H A D | ov5647.c | 103 struct clk *xclk; member in struct:ov5647 785 ret = clk_prepare_enable(sensor->xclk); 808 clk_disable_unprepare(sensor->xclk); 838 clk_disable_unprepare(sensor->xclk); 1404 sensor->xclk = devm_clk_get(dev, NULL); 1405 if (IS_ERR(sensor->xclk)) { 1406 dev_err(dev, "could not get xclk"); 1407 return PTR_ERR(sensor->xclk); 1410 xclk_freq = clk_get_rate(sensor->xclk);
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H A D | imx290.c | 230 struct clk *xclk; member in struct:imx290 976 /* Set clock parameters based on mode and xclk */ 1310 ret = clk_prepare_enable(imx290->xclk); 1320 clk_disable_unprepare(imx290->xclk); 1333 clk_disable_unprepare(imx290->xclk); 1389 dev_err(imx290->dev, "Could not get xclk frequency\n"); 1407 ret = clk_set_rate(imx290->xclk, xclk_freq); 1409 dev_err(imx290->dev, "Could not set xclk frequency\n"); 1541 imx290->xclk = devm_clk_get(dev, "xclk"); [all...] |
H A D | ov5645.c | 93 struct clk *xclk; member in struct:ov5645 646 clk_disable_unprepare(ov5645->xclk); 662 ret = clk_prepare_enable(ov5645->xclk); 1083 /* get system clock (xclk) */ 1084 ov5645->xclk = devm_clk_get(dev, NULL); 1085 if (IS_ERR(ov5645->xclk)) { 1086 dev_err(dev, "could not get xclk"); 1087 return PTR_ERR(ov5645->xclk); 1092 dev_err(dev, "could not get xclk frequency\n"); 1103 ret = clk_set_rate(ov5645->xclk, xclk_fre [all...] |
H A D | gc2145.c | 602 struct clk *xclk; member in struct:gc2145 965 ret = clk_prepare_enable(gc2145->xclk); 996 clk_disable_unprepare(gc2145->xclk); 1298 /* Get system clock (xclk) */ 1299 gc2145->xclk = devm_clk_get(dev, NULL); 1300 if (IS_ERR(gc2145->xclk)) 1301 return dev_err_probe(dev, PTR_ERR(gc2145->xclk), 1302 "failed to get xclk\n"); 1304 xclk_freq = clk_get_rate(gc2145->xclk); 1306 dev_err(dev, "xclk frequenc [all...] |
H A D | st-vgxy61.c | 388 struct clk *xclk; member in struct:vgxy61_dev 1646 ret = clk_prepare_enable(sensor->xclk); 1681 clk_disable_unprepare(sensor->xclk); 1695 clk_disable_unprepare(sensor->xclk); 1764 sensor->xclk = devm_clk_get(dev, NULL); 1765 if (IS_ERR(sensor->xclk)) { 1766 dev_err(dev, "failed to get xclk\n"); 1767 return PTR_ERR(sensor->xclk); 1769 sensor->clk_freq = clk_get_rate(sensor->xclk);
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H A D | ov5640.c | 29 /* min/typical/max system clock (xclk) frequencies */ 441 struct clk *xclk; /* system clock to OV5640 */ member in struct:ov5640_dev 2484 ret = clk_prepare_enable(sensor->xclk); 2511 clk_disable_unprepare(sensor->xclk); 2519 clk_disable_unprepare(sensor->xclk); 3899 /* get system clock (xclk) */ 3900 sensor->xclk = devm_clk_get(dev, "xclk"); 3901 if (IS_ERR(sensor->xclk)) { 3902 dev_err(dev, "failed to get xclk\ [all...] |
/linux-master/drivers/video/fbdev/aty/ |
H A D | atyfb_base.c | 330 static int xclk; variable 386 int pll, mclk, xclk, ecp_max; member in struct:__anon1367 475 par->pll_limits.xclk = aty_chips[i].xclk; 503 par->pll_limits.xclk = 67; 511 par->pll_limits.xclk = 67; 521 par->pll_limits.xclk = 67; 529 par->pll_limits.xclk = 67; 541 par->pll_limits.xclk = 67; 549 par->pll_limits.xclk 2296 aty_calc_mem_refresh(struct atyfb_par *par, int xclk) argument [all...] |
H A D | aty128fb.c | 407 u32 xclk; member in struct:aty128_constants 906 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 910 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 912 par->constants.xclk, par->constants.ref_divider, 965 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 986 if (!par->constants.xclk) 987 par->constants.xclk = 0x1d4d; /* same as mclk */ 1428 u32 xclk = par->constants.xclk; local 1437 n = xclk * fifo_widt [all...] |
H A D | atyfb.h | 52 int sclk, mclk, mclk_pm, xclk; member in struct:pll_info
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