/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfxhub_v1_2.c | 45 uint32_t xcc_mask) 50 for_each_inst(i, xcc_mask) { 68 uint32_t xcc_mask; local 70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 71 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); 75 uint32_t xcc_mask) 85 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); 90 for_each_inst(i, xcc_mask) { 125 uint32_t xcc_mask) 42 gfxhub_v1_2_xcc_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base, uint32_t xcc_mask) argument 74 gfxhub_v1_2_xcc_init_gart_aperture_regs(struct amdgpu_device *adev, uint32_t xcc_mask) argument 124 gfxhub_v1_2_xcc_init_system_aperture_regs(struct amdgpu_device *adev, uint32_t xcc_mask) argument 194 gfxhub_v1_2_xcc_init_tlb_regs(struct amdgpu_device *adev, uint32_t xcc_mask) argument 220 gfxhub_v1_2_xcc_init_cache_regs(struct amdgpu_device *adev, uint32_t xcc_mask) argument 269 gfxhub_v1_2_xcc_enable_system_domain(struct amdgpu_device *adev, uint32_t xcc_mask) argument 289 gfxhub_v1_2_xcc_disable_identity_aperture(struct amdgpu_device *adev, uint32_t xcc_mask) argument 316 gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev, uint32_t xcc_mask) argument 390 gfxhub_v1_2_xcc_program_invalidation(struct amdgpu_device *adev, uint32_t xcc_mask) argument 408 gfxhub_v1_2_xcc_gart_enable(struct amdgpu_device *adev, uint32_t xcc_mask) argument 429 uint32_t xcc_mask; local 435 gfxhub_v1_2_xcc_gart_disable(struct amdgpu_device *adev, uint32_t xcc_mask) argument 470 uint32_t xcc_mask; local 476 gfxhub_v1_2_xcc_set_fault_enable_default(struct amdgpu_device *adev, bool value, uint32_t xcc_mask) argument 528 uint32_t xcc_mask; local 534 gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) argument 577 uint32_t xcc_mask; local [all...] |
H A D | ta_ras_if.h | 140 uint16_t xcc_mask; member in struct:ta_ras_init_flags
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H A D | aqua_vanjaram.c | 275 { GC_HWIP, adev->gfx.xcc_mask }, 322 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 415 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 439 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 500 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 556 uint32_t xcc_mask; local 573 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 574 if (r || !xcc_mask) 577 xcc_id = ffs(xcc_mask) - 1;
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H A D | amdgpu_gfx.c | 215 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 929 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 930 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); local 938 for_each_inst(i, xcc_mask) 1249 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1294 switch (NUM_XCC(adev->gfx.xcc_mask)) {
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H A D | gfx_v9_4_3.c | 192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 201 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 467 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 636 NUM_XCC(adev->gfx.xcc_mask) / 641 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 663 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 852 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 945 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1078 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1157 num_xcc = NUM_XCC(adev->gfx.xcc_mask); [all...] |
H A D | gmc_v9_0.c | 1848 uint32_t xcc_mask; local 1850 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1851 xcc_mask = (1U << num_xcc) - 1; 1853 for_each_inst(xcc_id, xcc_mask) { 2057 NUM_XCC(adev->gfx.xcc_mask));
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H A D | amdgpu_gfx.h | 433 uint16_t xcc_mask; member in struct:amdgpu_gfx
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H A D | amdgpu_vm.h | 467 uint32_t xcc_mask);
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H A D | amdgpu_virt.c | 954 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) {
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H A D | nbio_v7_9.c | 432 0xff & ~(adev->gfx.xcc_mask));
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H A D | amdgpu_discovery.c | 668 adev->gfx.xcc_mask &= 952 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1243 adev->gfx.xcc_mask = 0; 1338 adev->gfx.xcc_mask |=
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H A D | amdgpu_vm.c | 1501 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush. 1511 uint32_t xcc_mask) 1531 for_each_inst(xcc, xcc_mask) { 1508 amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint32_t flush_type, uint32_t xcc_mask) argument
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H A D | amdgpu_ras.c | 355 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
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H A D | amdgpu_psp.c | 1721 ras_cmd->ras_in_message.init_flags.xcc_mask = 1722 adev->gfx.xcc_mask;
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H A D | gfx_v6_0.c | 3031 adev->gfx.xcc_mask = 1;
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H A D | gfx_v7_0.c | 4179 adev->gfx.xcc_mask = 1;
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H A D | gfx_v8_0.c | 5264 adev->gfx.xcc_mask = 1;
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/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_mqd_manager_v9.c | 139 NUM_XCC(node->xcc_mask), 539 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 563 uint32_t xcc_mask = mm->dev->xcc_mask; local 568 for_each_inst(xcc_id, xcc_mask) { 587 uint32_t xcc_mask = mm->dev->xcc_mask; local 593 for_each_inst(xcc_id, xcc_mask) { 634 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 661 NUM_XCC(mm->dev->xcc_mask); 724 uint32_t xcc_mask = mm->dev->xcc_mask; local 754 uint32_t xcc_mask = mm->dev->xcc_mask; local [all...] |
H A D | kfd_mqd_manager.c | 80 NUM_XCC(dev->xcc_mask); 109 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); 110 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1;
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H A D | kfd_device.c | 621 uint32_t xcc_mask = node->xcc_mask; local 644 for_each_inst(xcc, xcc_mask) { 801 &node->xcc_mask); 804 node->xcc_mask = 805 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
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H A D | kfd_device_queue_manager.c | 143 uint32_t xcc_mask = dqm->dev->xcc_mask; local 146 for_each_inst(xcc_id, xcc_mask) 436 uint32_t xcc_mask = dqm->dev->xcc_mask; local 440 for_each_inst(xcc_id, xcc_mask) 709 uint32_t xcc_mask = dev->xcc_mask; local 755 for_each_inst(xcc_id, xcc_mask) 1374 uint32_t xcc_mask local 1389 uint32_t xcc_mask = dqm->dev->xcc_mask; local 3189 uint32_t xcc_mask = dqm->dev->xcc_mask; local [all...] |
H A D | kfd_debug.c | 448 uint32_t xcc_mask = pdd->dev->xcc_mask; local 462 for_each_inst(xcc_id, xcc_mask) 1068 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask);
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H A D | kfd_topology.c | 478 NUM_XCC(dev->gpu->xcc_mask)) : 0); 544 NUM_XCC(dev->gpu->xcc_mask)); 1113 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); 1611 int num_xcc = NUM_XCC(knode->xcc_mask); 1616 start = ffs(knode->xcc_mask) - 1; 1725 start = ffs(kdev->xcc_mask) - 1; 1726 end = start + NUM_XCC(kdev->xcc_mask);
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H A D | kfd_priv.h | 270 uint32_t xcc_mask; /* Instance mask of XCCs present */ member in struct:kfd_node 1471 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask);
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H A D | kfd_process_queue_manager.c | 1037 num_xccs = NUM_XCC(q->device->xcc_mask);
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