#
533eefb9 |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add smu 14.0.1 discovery support This patch to add smu 14.0.1 support Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
68a2afbc |
|
06-Mar-2024 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: enable UMSCH 4.0.6 Share same codes with 4.0.5 and enable collaborate mode for VPE. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
155d4683 |
|
13-Feb-2024 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add VPE 6.1.1 discovery support Enable VPE 6.1.1. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
709ef39f |
|
30-Nov-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu/vpe: add multi instance VPE support Add support for multi instance VPE processing. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
79698b14 |
|
08-Mar-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add nbif v6_3_1 ip block Add nbif v6_3_1 ip block. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2bdebcb1 |
|
04-Mar-2024 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add dcn3.5.1 support This patch to add dcn3.5.1 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a24029cc |
|
26-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add vcn 4.0.6 discovery support This patch is to add vcn 4.0.6 support Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d6a76c0a |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: enable MES discovery for GC 11.5.1 This patch to enable MES for GC 11.5.1 Reviewed-by: shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e2442d3e |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add GC 11.5.1 discovery support This patch to add GC 11.5.1 support Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
93c5cc83 |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add GC 11.5.1 to GC 11.5.0 family This patch to add GC 11.5.1 to GC 11.5.0 family. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f1c40b6e |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: enable soc21 discovery support for GC 11.5.1 This patch to enable soc21 support for GC 11.5.1 Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
278318d3 |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: enable gmc11 discovery support for GC 11.5.1 This patch to enable gmc11 for GC 11.5.1 Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a02cfac9 |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add SDMA 6.1.1 discovery support This patch to add SDMA 6.1.1 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aec765a4 |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add psp 14.0.1 discovery support This patch to add psp 14.0.1 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c5ce1f1a |
|
12-Dec-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add smuio 14.0.1 support This patch to add smuio 14.0.1 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bd377b12 |
|
03-Jan-2024 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add nbio 7.11.1 discovery support This patch to add nbio 7.11.1 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
efc11f34 |
|
10-Aug-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: support psp ip block discovery for psp v14 Support PSP ip block discovery for psp v14. Add psp ip block for psp v14_0_2 and v14_0_3. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cff99603 |
|
14-Sep-2023 |
Sonny Jiang <sonny.jiang@amd.com> |
drm/amdgpu: Add jpeg_v5_0_0 ip block support Enable support for jpeg_v5_0_0 ip block. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
470675f6 |
|
15-Aug-2023 |
Sonny Jiang <sonny.jiang@amd.com> |
amdgpu/drm: Add vcn_v5_0_0_ip_block support Enable support for vcn_v5_0_0_ip_block Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ca46c259 |
|
08-Mar-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: Add hdp v7_0 ip block Add hdp v7_0 ip block Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
56018e83 |
|
08-Mar-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: Add ih v7_0 ip block Add ih v7_0 ip block. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
39df603d |
|
08-Mar-2023 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: Add lsdma v7_0 ip block Add lsdma v7_0 ip block. v2: squash in updates (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cdb637d3 |
|
01-Feb-2024 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amdgpu: Fix potential out-of-bounds access in 'amdgpu_discovery_reg_base_init()' The issue arises when the array 'adev->vcn.vcn_config' is accessed before checking if the index 'adev->vcn.num_vcn_inst' is within the bounds of the array. The fix involves moving the bounds check before the array access. This ensures that 'adev->vcn.num_vcn_inst' is within the bounds of the array before it is used as an index. Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1289 amdgpu_discovery_reg_base_init() error: testing array offset 'adev->vcn.num_vcn_inst' after use. Fixes: a0ccc717c4ab ("drm/amdgpu/discovery: validate VCN and SDMA instances") Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c8cb7e09 |
|
28-Dec-2023 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Query boot status if discovery failed Check and report boot status if discovery failed. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
c3d5e297 |
|
09-Jan-2024 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop exp hw support check for GC 9.4.3 No longer needed. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.7.x
|
#
3938eb95 |
|
19-Oct-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add a retry for IP discovery init AMD dGPUs have integrated FW that runs as soon as the device gets power and initializes the board (determines the amount of memory, provides configuration details to the driver, etc.). For direct PCIe attached cards this happens as soon as power is applied and normally completes well before the OS has even started loading. However, with hotpluggable ports like USB4, the driver needs to wait for this to complete before initializing the device. This normally takes 60-100ms, but could take longer on some older boards periodically due to memory training. Retry for up to a second. In the non-hotplug case, there should be no change in behavior and this should complete on the first try. v2: adjust test criteria v3: adjust checks for the masks, only enable on removable devices v4: skip bif_fb_en check Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2925 Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
d539b0ad |
|
26-Oct-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: set XGMI IP version manually for v6_4 The version can't be queried from discovery table. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f7a17b2b |
|
26-Oct-2023 |
Mukul Joshi <mukul.joshi@amd.com> |
drm/amdgpu: Fix typo in IP discovery parsing Fix a typo in parsing of the GC info table header when reading the IP discovery table. Fixes: 0e64c9aad031 ("drm/amdgpu: add type conversion for gc info") Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2cea7bb9 |
|
11-Sep-2023 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: get RAS poison status from DF v4_6_2 Add DF block and RAS poison mode query for DF v4_6_2. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ad3e54ab |
|
28-Apr-2023 |
Li Ma <li.ma@amd.com> |
drm/amdgpu/discovery: add SMU 14 support add smu 14 into the IP discovery list. Signed-off-by: Li Ma <li.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ce862c49 |
|
25-May-2023 |
Aaron Liu <aaron.liu@amd.com> |
drm/amdgpu/discovery: enable DCN 3.5.0 support Enable DCN 3.5.0 support. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ac8e62ab |
|
22-Sep-2023 |
Kees Cook <keescook@chromium.org> |
drm/amdgpu/discovery: Annotate struct ip_hw_instance with __counted_by Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time checking via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct ip_hw_instance. [1] https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230922173216.3823169-2-keescook@chromium.org
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#
ff96ddc3 |
|
11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add more fields to IP version Include subrevision and variant fileds also to IP version. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e8303cf |
|
11-Sep-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use function for IP version check Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0e64c9aa |
|
06-Sep-2023 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add type conversion for gc info gc info usage misses type conversion. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Li Ma <li.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eebb06d1 |
|
03-Jun-2023 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add amdgpu_umsch_mm module parameter Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled). Signed-off-by: Lang Yu <Lang.Yu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
822f7808 |
|
21-Jun-2023 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu/discovery: enable UMSCH 4.0 in IP discovery Enable UMSCH to support VPE and VCN user queues. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
844d8dd5 |
|
13-Jun-2023 |
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> |
drm/amdgpu/discovery: add VCN 4.0.5 Support Enable VCN 4.0.5 on gc 11_5_0. Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3ee8fb70 |
|
12-Jul-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: enable VPE for VPE 6.1.0 Enable Video Processing Engine on SoCs that contain VPE 6.1.0. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0b233357 |
|
16-Jun-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add HWID for VPE Add HWID for Video Processing Engine. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b90975fa |
|
14-Jul-2023 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: enable gmc11 for GC 11.5.0 Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b5549a2d |
|
14-Jul-2023 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: enable gfx11 for GC 11.5.0 Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d3ff0189 |
|
06-Jul-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu/discovery: enable mes block for gc 11.5.0 Add to IP discovery table. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d9d68334 |
|
23-May-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: add nbio 7.11.0 support Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bb7249ee |
|
14-Jul-2023 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: enable soc21 support Add 11.5.0 to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2c8a7ca1 |
|
14-Jul-2023 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu: add new AMDGPU_FAMILY definition add GC 11.5.0 family Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e240020a |
|
14-Aug-2023 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: update gc_info v2_1 from discovery Several new fields are exposed in gc_info v2_1 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f489a419 |
|
14-Aug-2023 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: update mall info v2 from discovery Mall info v2 is introduced in ip discovery Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
46b55e25 |
|
14-Aug-2023 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: update gc_info v2_1 from discovery Several new fields are exposed in gc_info v2_1 Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d4f6425a |
|
14-Aug-2023 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: update mall info v2 from discovery Mall info v2 is introduced in ip discovery Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4c340d00 |
|
23-May-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: add ih 6.1.0 support Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eff7a442 |
|
23-May-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: add smuio 14.0.0 support Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
9b9a5e34 |
|
23-May-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: add hdp 6.1.0 support Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
99af9c95 |
|
14-Jul-2023 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: enable sdma6 for SDMA 6.1.0 Add to IP discovery table. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
82f33504 |
|
18-Jul-2023 |
Li Ma <li.ma@amd.com> |
drm/amdgpu/discovery: enable PSP 14.0.0 support Add it to IP discovery. Signed-off-by: Li Ma <li.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2eb841bd |
|
15-Jun-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: mark GC 9.4.3 experimental for now Mark as experimental for now until we get closer to production to avoid possible undesireable behavior when mixing newer boards with older kernels. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bcd9a5f8 |
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09-Jun-2023 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Update total channel number for umc v8_10 Update total channel number for umc v8_10. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20997c04 |
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22-May-2023 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: set the APU flag based on package type Since currently APU and dGPU share the same pcie class while gmc init needs the flag to set up correctly for upcomming memory allocations v2: call get_pkg_type in smuio 13_0_3 is enough (hawking) Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c796d7e0 |
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16-May-2023 |
Shiwu Zhang <shiwu.zhang@amd.com> |
drm/amdgpu: add the smu_v13_0_6 and gfx_v9_4_3 ip block Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6a944ccb |
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27-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix harvest reporting of VCN Use VCN instance mask to check if an instance is harvested or not. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aaf1090a |
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17-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add instance mask for VCN and JPEG Keep an instance mask formed by physical instance numbers for VCN and JPEG IPs. Populate the mask from discovery table information. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Tested-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f2b8447b |
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09-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Fix discovery sys node harvest info Initalize syfs nodes after harvest information is fetched and fetch the correct harvest info based on each IP instance. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ac772a3c |
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29-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add fallback path for discovery info If SOC doesn't expose dedicated vram, discovery region may be available through system memory. Rename the existing interface to generic read_binary_from_mem and add a fallback path to read from system memory. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
368bb1bc |
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29-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Read discovery info from system memory On certain ASICs, discovery info is available at reserved region in system memory. The location is available through ACPI interface. Add API to read discovery info from there. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
52c293ab |
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09-Jan-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Populate VCN/JPEG harvest information Certain instances of VCN/JPEG IPs may not be usable. Fetch the information from harvest table. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ed1f42f0 |
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17-Dec-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu: enable vcn/jpeg on vcn_v4_0_3 Enable vcn/jpeg on vcn_v4_0_3. Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
73fa2553 |
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27-Nov-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use discovery to get XCC/SDMA mask Get information about active XCC and SDMAs from discovery table. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
44cbc453 |
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01-Dec-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Make VRAM discovery read optional When overridden with module param, directly read discovery info from discovery binary instead of reading from VRAM. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a820d3ca |
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01-Dec-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Remove unnecessary return value check There is no need to check return value, as the function internally used - amdgpu_discovery_read_binary_from_vram() - returns void. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e56c9ef6 |
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23-Sep-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add soc config init for GC9.4.3 ASICs Add function to initialize soc configuration information for GC 9.4.3 ASICs. Use it to map IPs and other SOC related information once IP configuration information is available through discovery. For GC9.4.3 compute partition related callbacks are initialized as part of configuration init. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6b7ec18b |
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23-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init smuio funcs for smuio v13_0_3 Add callbacks for SMUIO 13.0.3 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7d158f52 |
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27-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: parse base address from new ip discovery with 64bit ip base address Truncate the 64bit base address from ip discovery and only store lower 32bit ip base in reg_offset[]. Bits > 32 follows ASIC specific format, thus just discard them and handle it within specific ASIC. By this way reg_offset[] and related helpers can stay unchanged. v2: make comments more generic Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aabb4784 |
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07-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: upgrade amdgpu_discovery struct ip to ip_v4 version 4 supports 64bit ip base address Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cab7d478 |
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29-Jun-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Add IP instance map for aqua vanjaram Add XCC logical to physical instance map for aqua vanjaram v2: Keep look up table only for required IPs, for others return default mapping (Felix). Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0e5f6251 |
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27-Apr-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop unused function amdgpu_discovery_get_ip_version() has not been used since commit c40bdfb2ffa4 ("drm/amdgpu: fix incorrect VCN revision in SRIOV") so drop it. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
29551fd9 |
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27-Apr-2023 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: drop invalid IP revision This was already fixed and dropped in: commit baf3f8f37406 ("drm/amdgpu: handle SRIOV VCN revision parsing") commit c40bdfb2ffa4 ("drm/amdgpu: fix incorrect VCN revision in SRIOV") But seems to have been accidently been left around in a merge. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7abac457 |
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19-Apr-2023 |
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> |
drm/amd/amdgpu: Fix style issues in amdgpu_discovery.c Fix following checkpatch errors in amdgpu_discovery.c ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: code indent should use tabs where possible Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5e5d4b39 |
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03-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add common ip block for GC 9.4.3 Add common IP handling for GC 9.4.3 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
69bacf15 |
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03-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add GMC ip block for GC 9.4.3 Add GMC IP handling for GC 9.4.3 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f3409f76 |
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03-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Set family for GC 9.4.3 Set family for GC 9.4.3 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5d55e1d0 |
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25-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init nbio v7_9 callbacks switch to the new nbio generation for NBIO 7.9.0. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bf35dbc1 |
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08-Jul-2022 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/jpeg: enable jpeg v4_0 for sriov - skip direct jpeg registers read&write since it is not allowed - reset Doorbell range layout for sriov Signed-off-by: Jane Jian <Jane.Jian@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a32d7d6b |
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03-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add PSP ip block for PSP 13.0.6 Add PSP IP handling for PSP 13.0.6 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
051ae8d5 |
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06-Sep-2021 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: set sdma v4_4_2 ip block Use sdma 4.4.2 IP block for chips with sdma 4.4.2 hardware. Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4688940a |
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03-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add HDP ip block for HDP 4.4.2 Add HDP IP handling for HDP 4.4.2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0df2032a |
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03-Oct-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add IH ip block for IH 4.4.2 Add IH IP handling for IH 4.4.2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2b595659 |
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24-Feb-2023 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Support umc node harvest config on umc v8_10 Don't need to query error count and error address on harvest umc nodes. v2: Fix code bug, use active_mask instead of harvsest_config and remove unnecessary argument in LOOP macro. v3: Leave adev->gmc.num_umc unchanged. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b2daaa93 |
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15-Feb-2023 |
Thomas Weißschuh <linux@weissschuh.net> |
drm/amdgpu: make kobj_type structures constant Since commit ee6d3dd4ed48 ("driver core: make kobj_type constant.") the driver core allows the usage of const struct kobj_type. Take advantage of this to constify the structure definitions to prevent modification at runtime. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
06630fb9 |
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24-Feb-2023 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Support umc node harvest config on umc v8_10 Don't need to query error count and error address on harvest umc nodes. v2: Fix code bug, use active_mask instead of harvsest_config and remove unnecessary argument in LOOP macro. v3: Leave adev->gmc.num_umc unchanged. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e4f665de |
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19-Sep-2022 |
Candice Li <candice.li@amd.com> |
drm/amdgpu: Add poison mode query for df v4_3 Add poison mode query support on df v4_3. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7308ceb4 |
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25-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1 this patch is to enable nbio support for NBIO v7.7.1. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
51e7a216 |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add smu 13 support for smu 13.0.11 this patch to add smu 13 support for smu 13.0.11. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dd2d9c7f |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: set the APU flag for GC 11.0.4 Set the APU flag appropriately for GC 11.0.4. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
94ab7068 |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: set GC 11.0.4 family this patch is to set GC 11.0.4 family. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7c1389f1 |
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21-Nov-2022 |
Tim Huang <tim.huang@amd.com> |
drm/amdgpu/discovery: add PSP IP v13.0.11 support Add PSP IP v13.0.11 ip discovery support. Signed-off-by: Tim Huang <tim.huang@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6a6af775 |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: enable mes support for GC v11.0.4 this patch is to enable mes for GC 11.0.4. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b952d6b3 |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: enable gfx v11 for GC 11.0.4 Enable gfx v11 for GC 11.0.4. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d5fd8c89 |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: enable gmc v11 for GC 11.0.4 Enable gmc (graphic memory controller) v11 for GC 11.0.4. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
69dc98bb |
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11-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 Enable soc21 common for GC 11.0.4. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b7a3260c |
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21-Nov-2022 |
Ren Zhijie <renzhijie2@huawei.com> |
drm/amdgpu: fix unused-function error If CONFIG_DRM_AMDGPU=y and CONFIG_DRM_AMD_DC is not set, gcc complained about unused-function : drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1705:13: error: ‘amdgpu_discovery_set_sriov_display’ defined but not used [-Werror=unused-function] static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors To fix this error, use CONFIG_DRM_AMD_DC to wrap the definition of amdgpu_discovery_set_sriov_display(). Fixes: 25263da37693 ("drm/amdgpu: rework SR-IOV virtual display handling") Signed-off-by: Ren Zhijie <renzhijie2@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5e0f4c04 |
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29-Sep-2022 |
Perry Yuan <Perry.Yuan@amd.com> |
drm/amdgpu: add Vangogh APU flag to IP discovery path Add the missing apu flag for Vangogh when using IP discovery code path to initialize IPs Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25263da3 |
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18-Jul-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework SR-IOV virtual display handling virtual display is enabled unconditionally in SR-IOV, but without specifying the virtual_display module, the number of crtcs defaults to 0. Set a single display by default for SR-IOV if the virtual_display parameter is not set. Only enable virtual display by default on SR-IOV on asics which actually have display hardware. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7701d10a |
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25-Oct-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: force read discovery file if set discovery=2 If discovery is set to 2 in module parameters explicitly, the intention is to use the discovery file in FW rather than the one in BIOS, usually because the latter is incorrect. This patch to force read discovery file if set discovery=2. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a79852a3 |
|
06-Sep-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: correct the memcpy size for ip discovery firmware Use fw->size instead of discovery_tmr_size for fallback path. Signed-off-by: Le Ma <le.ma@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
aa44beb5 |
|
22-Aug-2022 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/vcn: Add sriov VCN v4_0 unified queue support Enable unified queue support for sriov, abandon all previous multi-queue settings Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dc5f3829 |
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21-Jul-2022 |
Horace Chen <horace.chen@amd.com> |
drm/amdgpu: sriov remove vcn_4_0 and jpeg_4_0 SRIOV needs to initialize mmsch instead of multimedia engines directly. So currently remove them for SR-IOV until the code and firmwares are ready. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
119dc6c5 |
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20-Jul-2022 |
Horace Chen <horace.chen@amd.com> |
drm/amdgpu: add sriov nbio callback structure [Why] under SR-IOV, the nbio doorbell range will be defined by PF. So VF nbio doorbell range registers will be blocked. It will cause violation if VF access those registers directly. [How] create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to skip the setting for the doorbell range registers. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e7c69a27 |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new ip block for MES 11.0.3 Add ip block support for mes v11_0_3. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a4d002d7 |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new ip block for GFX 11.0 Add ip block support for gfx v11_0_3. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2b569234 |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: Set GC family for GC 11.0.3 Set AMDGPU_FAMILY_GC_11_0_0. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
94ac3233 |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new ip block for GMC 11.0 Add ip block support for gmc v11_0_3. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
de2b2ae3 |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new ip block for LSDMA 6.0 Add ip block support for lsdma v6_0_3. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5bb71735 |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new ip block for sdma 6.0 Add ip block support for sdma v6_0_3. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
77356236 |
|
11-May-2022 |
John Clements <john.clements@amd.com> |
drm/amdgpu: enable smu block for smu 13.0.10 Force to enable smu block for SMU v13.0.10 Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a60d2191 |
|
25-Aug-2022 |
Frank Min <Frank.Min@amd.com> |
drm/amdgpu: add new ip block for PSP 13.0 Add ip block support for psp v13_0_10. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
fc968efd |
|
25-Aug-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add new ip block for SOC21 Add ip block support for soc21_common. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7e8a3ca9 |
|
27-Jul-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/amdgpu: enable support for psp 13.0.4 block This patch will enable support for psp 13.0.4 blcok. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
869b10ac |
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12-Jun-2022 |
Roman Li <Roman.Li@amd.com> |
drm/amdgpu: add dm ip block for dcn 3.1.4 Adding dm ip block to enable display on dcn 3.1.4. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
98a90f1f |
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11-Jul-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use the same HDP flush registers for all nbio 2.3.x Align RDNA2.x with other asics. One HDP bit per SDMA instance, aligned with firmware. This is effectively a revert of commit 369b7d04baf3 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12"). On further discussions with the relevant hardware teams, re-align the bits for SDMA. Fixes: 369b7d04baf3 ("drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12") Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
912db6a5 |
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11-Jul-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: use the same HDP flush registers for all nbio 7.4.x Align aldebaran with all other asics. One HDP bit per SDMA instance, aligned with firmware. This is effectively a revert of commit a0f9f8546668 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12"). On further discussions with the relevant hardware teams, re-align the bits for SDMA. Fixes: a0f9f8546668 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12") Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0081bc07 |
|
20-Jun-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add LSDMA block for LSDMA v6.0.1 This patch adds LSDMA ip block for LSDMA v6.0.1. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
438eac25 |
|
08-Jun-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/discovery: enable vcn/jpeg v4_0_2 Enable vcn/jpeg 4_0_2. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
62f8f5c3 |
|
28-Apr-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0 Enable ASPM support for PCIE 7.4.0 and 7.6.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
031ac4e4 |
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01-Jun-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add comments about VCN instance handling Add comments to clarify code that is safe, but triggers and smatch warning. Link: https://lists.freedesktop.org/archives/amd-gfx/2022-June/079905.html Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Dan Carpenter <dan.carpenter@oracle.com>
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#
85b0cc35 |
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25-Apr-2022 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: add DCN32 to IP discovery table [Why&How] Add DCN32 to IP discovery to enable automatic initialization of AMDGPU Display Manager Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a0ccc717 |
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16-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: validate VCN and SDMA instances Validate the VCN and SDMA instances against the driver structure sizes to make sure we don't get into a situation where the firmware reports more instances than the driver supports. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
caa5eadc |
|
19-May-2022 |
Evan Quan <evan.quan@amd.com> |
drm/amdgpu: suppress some compile warnings Suppress two compile warnings about "no previous prototype". Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0d6ec07a |
|
11-Jan-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/amdgpu/discovery: add SMU v13.0.4 into the IP discovery list This patch will add SMU v13.0.4 into the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
74c9b2e7 |
|
25-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add LSDMA block for LSDMA v6.0.2 Add LSDMA ip block for LSDMA v6.0.2. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
04de4afc |
|
25-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add LSDMA block for LSDMA v6.0.0 Add LSDMA ip block for LSDMA v6.0.0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1b491330 |
|
05-May-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add lsdma block Add Light SDMA (LSDMA) block and related function. LSDMA is a small instance of SDMA mainly for kernel driver use. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f333c9c6 |
|
11-Oct-2021 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/discovery: enable mes support for GC v11.0.1 GC v11.0.1 is using MES v11, so add IP block. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
10eab4e7 |
|
19-Apr-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/discovery: enable gfx v11 for GC 11.0.1 Enable gfx v11 for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
921173e2 |
|
19-Apr-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: set flag for GC 11.0.1 Set the APU flag appropriately for GC 11.0.1. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
23752714 |
|
10-Mar-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: set GC 11.0.1 family Add GC 11.0.1 family support. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
500448dc |
|
19-Apr-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/discovery: enable sdma v6 for SDMA 6.0.1 Enable sdma (system dma) v6 for SDMA 6.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bed95cfd |
|
11-Jan-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/amdgpu/discovery: add PSP v13.0.4 into the IP discovery list This patch will add PSP v13.0.4 into the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
48858a10 |
|
19-Apr-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/discovery: enable ih v6 for OSS 6.0.1 Enable ih (interrupt handler) v6 for OSS 6.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a8f24139 |
|
19-Apr-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/discovery: enable gmc v11 for GC 11.0.1 Enable gmc (graphic memory controller) v11 for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6e4eb7ce |
|
19-Apr-2022 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu/discovery: enable soc21 common for GC 11.0.1 Enable soc21 common for GC 11.0.1. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Aaron Liu <aaron.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6e9e59e2 |
|
10-Jan-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/amdgpu/discovery: add HDP v5.2.1 into the IP discovery list This patch is to add HDP v5.2.1 in the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0c1e5527 |
|
11-Jan-2022 |
Xiaojian Du <Xiaojian.Du@amd.com> |
drm/admgpu/discovery: add NBIO v7.7 into the IP discovery list This patch is to add NBIO v7.7 into the IP discovery list. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
30ca5b2b |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: set family for GC 11.0.2 Set AMDGPU_FAMILY_GC_11_0_0. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
af695849 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add gfx11 support for GC 11.0.2 Enable gfx11 support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
215a65f5 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add mes11 support for GC 11.0.2 Enable Micro Engine Scheduler support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
63b17080 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add sdma6 support for SDMA 6.0.2 Enable sdma6 support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
3a65fbc0 |
|
11-Feb-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/discovery: enable vcn/jpeg v4_0_4 Enable vcn/jpeg 4_0_4. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5681e800 |
|
15-Apr-2022 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amdgpu/discovery: add psp13 support for PSP 13.0.7 Enable psp 13 support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
eee5ed42 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add gmc11 support for GC 11.0.2 Enable gmc11 support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
86140844 |
|
09-Feb-2022 |
Chengming Gui <Jack.Gui@amd.com> |
drm/amdgpu/discovery: add SMUIO_13_0_8 func support Add SMUIO funcs for SMUIO_13_0_8. Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8742f5f1 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add hdp6 support for HDP 6.0.1 Enable Host Data Path support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4dad9d63 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add nbio 4.3 support for NBIO 4.3.1 Enable nbio 4.3 support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1db7b3aa |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add smu13 support for MP1 13.0.7 Enable System Management Unit support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1f926186 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add ih6 support for IH 6.0.2 Enable Interrupt Handler v6 support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0effe4a0 |
|
15-Apr-2022 |
Flora Cui <flora.cui@amd.com> |
drm/amdgpu/discovery: add soc21 support for GC 11.0.2 Enable soc21 common soc support. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d6ffefcc |
|
04-Apr-2022 |
James Zhu <James.Zhu@amd.com> |
drm/amdgpu/discovery: add VCN 4.0 Support Enable VCN 4.0 on asics where it is present. Signed-off-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8143b87c |
|
12-Mar-2021 |
Stanley Yang <Stanley.Yang@amd.com> |
drm/amdgpu/discovery: add SDMA v6_0 ip block Add SDMA v6 ip block for asics which support it. Signed-off-by: Stanley Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e97b0720 |
|
13-Apr-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add MES11 support Enable MES 11 on asics which support it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f6abd4d9 |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add GFX 11.0 Support Enable GFX 11.0 on asics where it is present. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a8bc8923 |
|
13-Apr-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: handle AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO in SMU Handle SMU load ordering when firmware load type is AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO. This works similarly to AMDGPU_FW_LOAD_DIRECT where the SMU load order is different from the standard ordering when front door loading is enabled. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7d336142 |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: Set GC family for GC 11.0 IP Set GC family for GC 11.0 IPs. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
40c48740 |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: Enable SMU for SMU 13.0.0 Enable SMU on SMU IP version 13.0.0 Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0984d384 |
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04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add GMC 11.0 Support Enable GMC 11.0 on asics where it is present. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
55a800da |
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04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: Enable PSP for PSP 13.0.0 Enable PSP on PSP IP version 13.0.0 Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
996ea859 |
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08-Jan-2022 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: init smuio v13_0_6 callbacks initialize smuio callback for soc21 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1761e5ef |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add HDP v6 Enable HDP v6 on asics where it is present. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2929a6bf |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add IH v6 Enable IH v6 on asics where it is present. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2c0e7ddd |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add NBIO 4.3 Support Enable NBIO 4.3 on asics where it is present. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
759693ac |
|
04-Apr-2022 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu/discovery: add soc21 common Support Enable soc21 common support on asics where it is present. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e24d0e91 |
|
29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.c This data has no dependencies, so encapsulate it all within amdgpu_discovery.c. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
622469c8 |
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29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add a function to parse the vcn info table To get the codec disable fuse mask. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f716113a |
|
29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add additional validation Check the table signatures and checksums and verify that the tables exist before accessing them. v2: disable MALL table for now Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
24681cb5 |
|
29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add a function to get the mall_size Add a function to fetch the mall size from the IP discovery table. Properly handle harvest configurations where more or less cache may be available. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
478d338b |
|
29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: handle UMC harvesting in IP discovery Check the harvesting table to determing if any UMC blocks have been harvested. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a2efebf1 |
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31-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: store the number of UMC IPs on the asic For chips with IP discovery get this from the table, hardcode it for older asics. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8eece29c |
|
29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: fix byteswapping in gc info parsing The table is in little endian format. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5cb1cfd5 |
|
29-Mar-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: populate additional GC info From the GC info table to the gfx config structure in the driver. The driver will use this data to configure the card correctly. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
73bce7a4 |
|
07-Apr-2022 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amdgpu: Use flexible array member Use flexible array member in ip discovery struct as recommended[1]. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays v2: squash in struct_size fixes Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f3fa4909 |
|
16-Mar-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop redundant check of harvest info Harvest bit setting in IP data structure promises this, so no need to set it explicitly. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e776a755 |
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22-Feb-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fix typo in amdgpu_discovery.c disocvery -> discovery Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e1dd4bbf |
|
17-Feb-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: read harvest bit per IP data on legacy GPUs Based on firmware team's input, harvest table in VBIOS does not apply well to legacy products like Navi1x, so seperate harvest mask configuration retrieve from different places. On legacy GPUs, scan harvest bit per IP data stuctures, while for newer ones, still read IP harvest info from harvest table. v2: squash in fix to limit it to specific skus (Guchun) Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
181ebed7 |
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10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add dm ip block for dcn 3.1.5 this patch adds dm ip block for dcn 3.1.5. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
068ea8bd |
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21-Jan-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amd/pm: add smu_v13_0_5_ppt implementation this patch adds smu_v13_0_5_ppt implementation. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d7fd297c |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add support for psp 13.0.5 Enabl psp support for psp 13.0.5. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
ec3ca078 |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add smuio support for smuio 13.0.10 this patch adds smuio support for smuio 13.0.10. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
935ad3a7 |
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21-Jan-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add support for nbio 7.3.0 this patch adds support for nbio 7.3.0. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
afc2f276 |
|
28-Oct-2021 |
Boyuan Zhang <boyuan.zhang@amd.com> |
drm/amdgpu/vcn: add vcn support for vcn 3.1.2 Load VCN FW, set caps. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
93afe158 |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add support for sdma 5.2.6 This patch adds support for sdma 5.2.6. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
874bfdfa |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add gc 10.3.6 support this patch adds gc 10.3.6 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a142606d |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add support for gmc10 for gc 10.3.6 this patch adds support for gmc10. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1957f27d |
|
10-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu: add nv common init for gc 10.3.6 This patch adds add nv common init for gc 10.3.6. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6b503383 |
|
17-Feb-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Dynamically initialize IP instance attributes Dynamically initialize IP instance attributes. This eliminates bugs stemming from adding new attributes to an IP instance. Cc: Alex Deucher <Alexander.Deucher@amd.com> Reported-by: Tom StDenis <tom.stdenis@amd.com> Fixes: 4d7ba312dd1f ("drm/amdgpu: Add "harvest" to IP discovery sysfs") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f0d54098 |
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16-Feb-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Fix ARM compilation warning Fix this ARM warning: drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:664:35: warning: format '%ld' expects argument of type 'long int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Wformat=] Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: kbuild-all@lists.01.org Cc: linux-kernel@vger.kernel.org Reported-by: kernel test robot <lkp@intel.com> Fixes: a6c40b178092 ("drm/amdgpu: Show IP discovery in sysfs") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Acked-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f83e1401 |
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25-Oct-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: Add sw DM function for 3.1.6 DCE Add 3.1.6 DCE IP and assign relevant sw DM function for the new DCE. Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a65dbf7c |
|
22-Dec-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/gfx10: Add GC 10.3.7 Support Needed to properly initialize GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
967af863 |
|
08-Nov-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/sdma5.2: add support for SDMA 5.2.7 Initialize SDMA engine firmware loading. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
db090ff8 |
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12-Nov-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amd/pm: Add support for MP1 13.0.8 Set smu sw function and enable swSMU support for MP1. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f99a7eb2 |
|
22-Dec-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/psp: Add support for MP0 13.0.8 Set psp sw funcs callback and firmware loading for MP0. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
97437f47 |
|
26-Oct-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/gmc10: add support for GC 10.3.7 Set gfxhub function and configure VM for GC block. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2fbc5086 |
|
08-Feb-2022 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: set sw common init for GC 10.3.7 Set nv_common_ip_block for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2019bf7c |
|
25-Oct-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: Add 13.0.9 SMUIO block Add SMUIO sw function for the new SMUIO block. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
01cbf049 |
|
22-Dec-2021 |
Prike Liang <Prike.Liang@amd.com> |
drm/amdgpu/discovery: add nbio sw func for 7.5.1 nbio add nbio sw func for the new 7.5.1 nbio block. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
4d7ba312 |
|
14-Feb-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Add "harvest" to IP discovery sysfs Add the "harvest" field to the IP attributes in the IP discovery sysfs visualization, as this field is present in the binary data. At the time of this commit, the harvest data isn't consistently correct in VBIOS, but it is exposed for completeness, in the hopes that VBIOS will be fixed in the future. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
a6c40b17 |
|
03-Feb-2022 |
Luben Tuikov <luben.tuikov@amd.com> |
drm/amdgpu: Show IP discovery in sysfs Add IP discovery data in sysfs. The format is: /sys/class/drm/cardX/device/ip_discovery/die/D/B/I/<attrs> where, X is the card ID, an integer, D is the die ID, an integer, B is the IP HW ID, an integer, aka block type, I is the IP HW ID instance, an integer. <attrs> are the attributes of the block instance. At the moment these include HW ID, instance number, major, minor, revision, number of base addresses, and the base addresses themselves. A symbolic link of the acronym HW ID is also created, under D/, if you prefer to browse by something humanly accessible. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Tom StDenis <tom.stdenis@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
f9ed188d |
|
08-Feb-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: add support for GC 10.1.4 Add basic support for GC 10.1.4, it uses same IP blocks with GC 10.1.3 Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
21202129 |
|
21-Jan-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: set APU flag based on IP discovery table Use the IP versions to set the APU flag when necessary. Reviewed-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6a6c2ab6 |
|
19-Jan-2022 |
Lang Yu <Lang.Yu@amd.com> |
drm/amdgpu: enable amdgpu_dc module parameter It doesn't work under IP discovery mode. Make it work! Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Alex Deucher <aleander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
03f6fb84 |
|
13-Jan-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: apply vcn harvest quirk This is a following patch to apply the workaround only on those boards with a bad harvest table in ip discovery. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e475986f |
|
13-Jan-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop redundant check of ip discovery_bin Early check in amdgpu_discovery_reg_base_init promises this. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
520d9cd2 |
|
13-Jan-2022 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: apply vcn harvest quirk This is a following patch to apply the workaround only on those boards with a bad harvest table in ip discovery. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
6638391b |
|
05-Jan-2022 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amdgpu: Enable second VCN for certain Navy Flounder. Certain Navy Flounder cards have 2 VCNs, enable it. Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
45e3d1db |
|
20-Dec-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop redundant semicolon A minor typo. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
0cd7f378 |
|
15-Dec-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add support for IP discovery gc_info table v2 Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
2cb6577a |
|
22-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: read and authenticate ip discovery binary read and authenticate ip discovery binary getting from vram first, if it is not valid, read and authenticate the one getting from file Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
32f0e1a3 |
|
22-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add helper to verify ip discovery binary signature To be used to check ip discovery binary signature Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f6dcaf0c |
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22-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: rename discovery_read_binary helper add _from_vram in the funciton name to diffrentiate the one used to read from file Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
43a80bd5 |
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23-Nov-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add helper to load ip_discovery binary from file To be used when ip_discovery binary is not carried by vbios Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c40bdfb2 |
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08-Dec-2021 |
Leslie Shi <Yuliang.Shi@amd.com> |
drm/amdgpu: fix incorrect VCN revision in SRIOV Guest OS will setup VCN instance 1 which is disabled as an enabled instance and execute initialization work on it, but this causes VCN ib ring test failure on the disabled VCN instance during modprobe: amdgpu 0000:00:08.0: amdgpu: ring vcn_enc_1.0 uses VM inv eng 5 on hub 1 amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_dec_0 (-110). amdgpu 0000:00:08.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vcn_enc_0.0 (-110). [drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test failed (-110). v2: drop amdgpu_discovery_get_vcn_version and rename sriov_config to vcn_config v3: modify VCN's revision in SR-IOV and bare-metal Fixes: baf3f8f3740625 ("drm/amdgpu: handle SRIOV VCN revision parsing") Signed-off-by: Leslie Shi <Yuliang.Shi@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
baf3f8f3 |
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30-Nov-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: handle SRIOV VCN revision parsing For SR-IOV, the IP discovery revision number encodes additional information. Handle that case here. v2: drop additional IP versions Reviewed-by: Guchun Chen <guchun.chen@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
37001698 |
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25-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: fix the missed handling for SDMA2 and SDMA3 There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Kevin Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
981b3045 |
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23-Nov-2021 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID [WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cc7818d7 |
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23-Nov-2021 |
Yang Wang <KevinYang.Wang@amd.com> |
drm/amdgpu: fix byteorder error in amdgpu discovery fix some byteorder issues about amdgpu discovery. This will result in running errors on the big end system. (e.g:MIPS) Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
73729a7d |
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10-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: add error print when failing to add IP block(v2) Driver initialization is driven by IP version from IP discovery table. So add error print when failing to add ip block during driver initialization, this will be more friendly to user to know which IP version is not correct. [ 40.467361] [drm] host supports REQ_INIT_DATA handshake [ 40.474076] [drm] add ip block number 0 <nv_common> [ 40.474090] [drm] add ip block number 1 <gmc_v10_0> [ 40.474101] [drm] add ip block number 2 <psp> [ 40.474103] [drm] add ip block number 3 <navi10_ih> [ 40.474114] [drm] add ip block number 4 <smu> [ 40.474119] [drm] add ip block number 5 <amdgpu_vkms> [ 40.474134] [drm] add ip block number 6 <gfx_v10_0> [ 40.474143] [drm] add ip block number 7 <sdma_v5_2> [ 40.474147] amdgpu 0000:00:08.0: amdgpu: Fatal error during GPU init [ 40.474545] amdgpu 0000:00:08.0: amdgpu: amdgpu: finishing device. v2: use dev_err to multi-GPU system Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5e713c6a |
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15-Dec-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add support for IP discovery gc_info table v2 Used on gfx9 based systems. Fixes incorrect CU counts reported in the kernel log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1833 Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
7551f70a |
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25-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: fix the missed handling for SDMA2 and SDMA3 There is no base reg offset or ip_version set for SDMA2 and SDMA3 on SIENNA_CICHLID, so add them. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Kevin Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
da3b36a2 |
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23-Nov-2021 |
Jane Jian <Jane.Jian@amd.com> |
drm/amdgpu/sriov/vcn: add new vcn ip revision check case for SIENNA_CICHLID [WHY] for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia bandwidth feature), which will be mismatched with original vcn0 revision [HOW] add new version check for vcn0 disabled revision(3, 0, 192), typically modified under sriov mode Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fd08953b |
|
23-Nov-2021 |
Yang Wang <KevinYang.Wang@amd.com> |
drm/amdgpu: fix byteorder error in amdgpu discovery fix some byteorder issues about amdgpu discovery. This will result in running errors on the big end system. (e.g:MIPS) Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
69650a87 |
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10-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: add error print when failing to add IP block(v2) Driver initialization is driven by IP version from IP discovery table. So add error print when failing to add ip block during driver initialization, this will be more friendly to user to know which IP version is not correct. [ 40.467361] [drm] host supports REQ_INIT_DATA handshake [ 40.474076] [drm] add ip block number 0 <nv_common> [ 40.474090] [drm] add ip block number 1 <gmc_v10_0> [ 40.474101] [drm] add ip block number 2 <psp> [ 40.474103] [drm] add ip block number 3 <navi10_ih> [ 40.474114] [drm] add ip block number 4 <smu> [ 40.474119] [drm] add ip block number 5 <amdgpu_vkms> [ 40.474134] [drm] add ip block number 6 <gfx_v10_0> [ 40.474143] [drm] add ip block number 7 <sdma_v5_2> [ 40.474147] amdgpu 0000:00:08.0: amdgpu: Fatal error during GPU init [ 40.474545] amdgpu 0000:00:08.0: amdgpu: amdgpu: finishing device. v2: use dev_err to multi-GPU system Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4d395f93 |
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09-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: add missed support for UVD IP_VERSION(3, 0, 64) Fixes: 96b8dd4423e74d ("drm/amdgpu/amdgpu_vcn: convert to IP version checking") Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b45a3603 |
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09-Nov-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: drop jpeg IP initialization in SRIOV case Fixes: b05b9c591f9ed6 ("drm/amdgpu: clean up set IP function") Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
58f8c7fa |
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25-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts Add secondary instance version info for soc15 parts. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
074b2092 |
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25-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts Add secondary instance version info for vega20, arcturure, and aldebaran. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
df9feb1a |
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21-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nbio7.4: use original HDP_FLUSH bits The extended bits were not available for use on vega20 and presumably arcturus as well. Fixes: a0f9f854666834 ("drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12") Reviewed-and-tested-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8cbc52c2 |
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21-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: Workaround harvesting info for some navy flounder boards Some navy flounder boards do not properly mark harvested VCN instances. Fix that here. v2: use IP versions Fixes: 1b592d00b4ac83 ("drm/amdgpu/vcn: remove manual instance setting") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1743 Reviewed-and-tested-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dac35c42 |
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18-Oct-2021 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu/discovery: parse hw_id_name for SDMA instance 2 and 3 Otherwise, hw_id_name string is NULL for SDMA 2 and 3 when dumping ip version from VBIOS. Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fe04957e |
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12-Oct-2021 |
Lang Yu <lang.yu@amd.com> |
drm/amdgpu: enable display for cyan skillfish Display support for cyan skillfish is ready now. Enable it! Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
369b7d04 |
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08-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12 It's used internally by firmware. Using it in the driver could conflict with firmware. v2: squash in fix for navi1x (Alex) Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
35bdf463 |
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01-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add missing case for HDP for renoir Missing 4.1.2. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
73bf6671 |
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07-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: add missing case for SMU 11.0.5 Was missed when converting the driver over to IP based initialization. Tested-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8001ba85 |
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01-Oct-2021 |
Guo Zhengkui <guozhengkui@vivo.com> |
drm/amdgpu: remove some repeated includings Remove two repeated includings in line 46 and 47. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
a79d3709 |
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17-Sep-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add an option to override IP discovery table from a file If you set amdgpu.discovery=2 you can force the the driver to fetch the IP discovery table from a file rather than from the table shipped on the device. This is useful for debugging and for device bring up and emulation when the tables may be in flux. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6d46d419 |
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10-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add support for SRIOV in IP discovery path Handle SRIOV requirements when adding IP blocks. v2: add comment about UVD/VCE support on vega20 SR-IOV Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b05b9c59 |
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10-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: clean up set IP function Split into several smaller per IP functions to make it easier to handle ordering issues for things like SR-IOV in a follow up patch. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1d789535 |
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04-Oct-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: convert IP version array to include instances Allow us to query instances versions more cleanly. Instancing support is not consistent unfortunately. SDMA is a good example. Sienna cichlid has 4 total SDMA instances, each enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8 total SDMA instances, but they are enumerated as multiple instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC is another example. On most chips there are multiple instances with the same HWID. This allows us to support both forms. v2: rebase v3: clarify instancing support Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f1741615 |
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09-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: get VCN harvest information from IP discovery table Use the table rather than asic specific harvest registers. v2: remove harvesting register checking Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5c3720be |
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09-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: get VCN and SDMA instances from IP discovery table Rather than hardcoding it. We already have the number of VCN instances from a previous patch, so just update the VCN instances for chips with static tables. v2: squash in checks for SDMA3,4 (Guchun) v3: clarify VCN changes Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d4c6e870 |
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30-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add initial IP discovery support for vega based parts Hardcode the IP versions for asics without IP discovery tables and then enumerate the asics based on the IP versions. TODO: fix SR-IOV support v2: Squash in HDP fix for Renoir Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5f931489 |
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29-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add DCI HWIP So we can track grab the appropriate DCE info out of the IP discovery table. This is a separare IP from DCN. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
795d0839 |
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20-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add initial IP enumeration via IP discovery table Add initial support for all navi based parts. v2: rebase Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1534db55 |
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26-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add XGMI HWIP So we can track grab the appropriate XGMI info out of the IP discovery table. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
54d2b1f4 |
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20-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fill in IP versions from IP discovery table Prerequisite for using IP versions in the driver rather than asic type. v2: Use IP_VERSION() macro instead of new function Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5f52e9a7 |
|
20-Jul-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: store HW IP versions in the driver structure So we can check the IP versions directly rather than using asic type. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f76f795a |
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09-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move headless sku check into harvest function Consolidate harvesting information. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5039f529 |
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26-Sep-2021 |
Ernst Sjöstrand <ernstp@gmail.com> |
drm/amd/amdgpu: Validate ip discovery blob We use the number_instance index that we get from the fw discovery blob to index into an array for example. Update error messages (Alex) Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
59066d00 |
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09-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: handle VCN instances when harvesting (v2) There may be multiple instances and only one is harvested. v2: fix typo in commit message Fixes: 83a0b8639185 ("drm/amdgpu: add judgement when add ip blocks (v2)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1673 Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7cbe08a9 |
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09-Aug-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: handle VCN instances when harvesting (v2) There may be multiple instances and only one is harvested. v2: fix typo in commit message Fixes: 83a0b8639185 ("drm/amdgpu: add judgement when add ip blocks (v2)") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1673 Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
376002f4 |
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05-Jan-2021 |
Bokun Zhang <Bokun.Zhang@amd.com> |
drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of MMSCH In the past, we use MMSCH to determine whether a VCN is enabled or not. This is not reliable since after a FLR, MMSCH may report junk data. It is better to use IP discovery data. Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c89d2a2f |
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03-Jun-2021 |
Peng Ju Zhou <PengJu.Zhou@amd.com> |
drm/amd/amdgpu: add instance_number check in amdgpu_discovery_get_ip_version The original code returns IP version of instantce_0 for every IP. This implementation may be correct for most of IPs. However, for certain IP block (VCN for example), it may have 2 instances and both of them have the same hw_id, BUT they have different revision number (0 and 1). In this case, the original amdgpu_discovery_get_ip_version cannot correct reflects the result and returns false information Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7bd939d0 |
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29-Apr-2021 |
Likun GAO <Likun.Gao@amd.com> |
drm/amdgpu: add judgement when add ip blocks (v2) Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
83a0b863 |
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29-Apr-2021 |
Likun GAO <Likun.Gao@amd.com> |
drm/amdgpu: add judgement when add ip blocks (v2) Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6bfbfe8c |
|
11-Nov-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: add UMC to ip discovery map resolve issue with UMC base offset not being set correctly in ip discovery sequence Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
72de33f8 |
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29-Jul-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move IP discovery data to mman It's related to the memory manager so move it there. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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d215a2a3 |
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24-Jun-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: reduce ip discovery data reading size Only read first 4K data instead of whole TMR block, so we can reduce the time in full access mode. Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f3167919 |
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18-Jun-2020 |
Nirmoy Das <nirmoy.das@amd.com> |
drm/amdgpu: label internally used symbols as static Used sparse(make C=1) to find these loose ends. v2: removed unwanted extra line Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e0c116c1 |
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31-Mar-2020 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: re-structue members for ip discovery This is to prepare for initializing discovery tmr size per ASIC type Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dffa11b4 |
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04-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: adjust sequence of ip_discovery init and timeout_setting what: 1)move timtout setting before ip_early_init to reduce exclusive mode cost for SRIOV 2)move ip_discovery_init() to inside of amdgpu_discovery_reg_base_init() it is a prepare for the later upcoming patches. why: in later upcoming patches we would use a new mailbox event -- "req_gpu_init_data", which is a callback hooked in adev->virt.ops and this callback send a new event "REQ_GPU_INIT_DAT" to host to notify host to do some preparation like "IP discovery/vbios on the VF FB" and this callback must be: A) invoked after set_ip_block() because virt.ops is configured during set_ip_block() B) invoked before ip_discovery_init() becausen ip_discovery_init() need host side prepares everything in VF FB first. current place of ip_discovery_init() is before we can invoke callback of adev->virt.ops, thus we must move ip_discovery_init() to a place after the adev->virt.ops all settle done, and the perfect place is in amdgpu_discovery_reg_base_init() Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8884532a |
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03-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: purge ip_discovery headers those two headers are not needed for ip discovery Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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91aeda18 |
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19-Feb-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/discovery: make the discovery code less chatty Make the IP block base output debug only. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e35e2b11 |
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29-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: add a generic fb accessing helper function(v3) add a generic helper function for accessing framebuffer via MMIO Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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45cf454e |
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29-Sep-2019 |
Tianci.Yin <tianci.yin@amd.com> |
drm/amdgpu: update amdgpu_discovery to handle revision update amdgpu_discovery to get IP revision. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5f6a556f |
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10-Oct-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: reserve discovery data at the top of VRAM IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a349b392 |
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11-Jul-2019 |
tiancyin <tianci.yin@amd.com> |
drm/amdgpu/discovery: fix DCE_HWIP mapping error in hw_id_map array ID of DCE_HWIP from vbios is DMU_HWID, mismatch cause null pointer crash in navi10 modprobe. Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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437298b8 |
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27-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: refactor ip list traversal for each ip, check whether it is needed by amdgpu driver, if yes, record its base addresses v2: change some DRM_INFO to DRM_DEBUG v3: remove unused variable (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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966f1d8fd |
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27-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: stop converting the units of base addresses the unit is already in dword Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8e84aa1b |
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26-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: stop taking psp header into account psp will write a header to vram, but the value exposed in RCC_CONFIG_MEMSIZE does not include the memory that this header is written to. Therefore, the interpretation of the table does not need to take the psp header into account. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2de00413 |
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26-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: fix hwid for nbio Properly set this. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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85f267a7 |
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26-Mar-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZE register base offset of nbio is not known before IP Discovery table is parsed, so hardcode this value. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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987da729 |
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20-Feb-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: fix calculations of some gfx info fix gfx info table handling. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f39f5bb1 |
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20-Jun-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu/discovery: add ip discovery initial support The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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