/linux-master/drivers/gpu/drm/radeon/ |
H A D | radeon_object.c | 529 lobj->tiling_flags = bo->tiling_flags; 534 lobj->tiling_flags = lobj->robj->tiling_flags; 550 if (!bo->tiling_flags) 588 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 610 uint32_t tiling_flags, uint32_t pitch) 618 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 619 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 620 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIF 609 radeon_bo_set_tiling_flags(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch) argument 669 radeon_bo_get_tiling_flags(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch) argument [all...] |
H A D | radeon_fbdev.c | 64 u32 tiling_flags = 0; local 91 tiling_flags = RADEON_TILING_MACRO; 96 tiling_flags |= RADEON_TILING_SWAP_32BIT; 99 tiling_flags |= RADEON_TILING_SWAP_16BIT; 106 if (tiling_flags) { 108 tiling_flags | RADEON_TILING_SURFACE,
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H A D | radeon_object.h | 158 u32 tiling_flags, u32 pitch); 160 u32 *tiling_flags, u32 *pitch);
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H A D | r200.c | 221 if (reloc->tiling_flags & RADEON_TILING_MACRO) 223 if (reloc->tiling_flags & RADEON_TILING_MICRO) 293 if (reloc->tiling_flags & RADEON_TILING_MACRO) 295 if (reloc->tiling_flags & RADEON_TILING_MICRO)
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H A D | r300.c | 717 if (reloc->tiling_flags & RADEON_TILING_MACRO) 719 if (reloc->tiling_flags & RADEON_TILING_MICRO) 721 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 786 if (reloc->tiling_flags & RADEON_TILING_MACRO) 788 if (reloc->tiling_flags & RADEON_TILING_MICRO) 790 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) 871 if (reloc->tiling_flags & RADEON_TILING_MACRO) 873 if (reloc->tiling_flags & RADEON_TILING_MICRO) 875 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
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H A D | radeon_legacy_crtc.c | 386 uint32_t tiling_flags; local 464 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 466 if (tiling_flags & RADEON_TILING_MICRO) 483 if (tiling_flags & RADEON_TILING_MACRO) { 499 if (tiling_flags & RADEON_TILING_MACRO) {
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H A D | evergreen_cs.c | 92 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) argument 94 if (tiling_flags & RADEON_TILING_MACRO) 96 else if (tiling_flags & RADEON_TILING_MICRO) 1179 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1180 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1181 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1184 evergreen_tiling_fields(reloc->tiling_flags, 1365 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1366 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); 1383 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); [all...] |
H A D | atombios_crtc.c | 1145 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local 1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1265 if (tiling_flags & RADEON_TILING_MACRO) { 1266 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1339 } else if (tiling_flags & RADEON_TILING_MICRO) 1466 uint32_t fb_format, fb_pitch_pixels, tiling_flags; local 1501 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1577 if (tiling_flags & RADEON_TILING_MACRO) 1579 else if (tiling_flags & RADEON_TILING_MICRO) 1582 if (tiling_flags [all...] |
H A D | r100.c | 1291 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1293 if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1633 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1635 if (reloc->tiling_flags & RADEON_TILING_MICRO) 1714 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1716 if (reloc->tiling_flags & RADEON_TILING_MICRO) 3091 uint32_t tiling_flags, uint32_t pitch, 3098 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3101 if (tiling_flags & RADEON_TILING_MACRO) 3104 if ((tiling_flags 3090 r100_set_surface_reg(struct radeon_device *rdev, int reg, uint32_t tiling_flags, uint32_t pitch, uint32_t offset, uint32_t obj_size) argument [all...] |
H A D | r600_cs.c | 1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) { 1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { 1464 * @tiling_flags: tiling flags 1474 u32 tiling_flags) 1496 if (tiling_flags & RADEON_TILING_MACRO) 1498 else if (tiling_flags & RADEON_TILING_MICRO) 1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) 1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) 1985 reloc->tiling_flags); 1469 r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, struct radeon_bo *texture, struct radeon_bo *mipmap, u64 base_offset, u64 mip_offset, u32 tiling_flags) argument [all...] |
H A D | radeon_gem.c | 570 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); 591 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
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H A D | radeon_vm.c | 147 list[0].tiling_flags = 0; 159 list[idx].tiling_flags = 0;
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H A D | radeon_display.c | 491 uint32_t tiling_flags, pitch_pixels; local 543 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); 551 if (tiling_flags & RADEON_TILING_MACRO) {
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H A D | radeon_asic.h | 91 uint32_t tiling_flags, uint32_t pitch, 338 uint32_t tiling_flags, uint32_t pitch,
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_plane.h | 46 const uint64_t tiling_flags,
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H A D | amdgpu_dm_plane.c | 181 uint64_t tiling_flags) 184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 203 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 209 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 763 const uint64_t tiling_flags, 180 amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info, uint64_t tiling_flags) argument 759 amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, const enum surface_pixel_format format, const enum dc_rotation_angle rotation, const uint64_t tiling_flags, union dc_tiling_info *tiling_info, struct plane_size *plane_size, struct dc_plane_dcc_param *dcc, struct dc_plane_address *address, bool tmz_surface, bool force_disable_dcc) argument [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_display.c | 203 u64 tiling_flags; local 258 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 731 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 734 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 743 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 829 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 836 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 861 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 921 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MOD 1109 amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, uint64_t *tiling_flags, bool *tmz_surface) argument [all...] |
H A D | amdgpu_object.h | 124 u64 tiling_flags; member in struct:amdgpu_bo_user 324 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 325 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
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H A D | amdgpu_object.c | 1111 * @tiling_flags: new flags 1119 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) argument 1126 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1130 ubo->tiling_flags = tiling_flags; 1137 * @tiling_flags: returned flags 1142 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) argument 1150 if (tiling_flags) 1151 *tiling_flags = ubo->tiling_flags; [all...] |
H A D | dce_v11_0.c | 1905 uint64_t fb_location, tiling_flags; local 1942 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MOD [all...] |
H A D | dce_v10_0.c | 1855 uint64_t fb_location, tiling_flags; local 1892 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1895 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1985 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1988 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1989 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1990 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1991 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1992 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2005 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MOD [all...] |
H A D | dce_v8_0.c | 1802 uint64_t fb_location, tiling_flags; local 1839 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1842 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1924 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1927 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1928 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1929 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1930 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1931 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1940 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MOD [all...] |
H A D | dce_v6_0.c | 1836 uint64_t fb_location, tiling_flags; local 1872 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1955 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1958 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1959 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1960 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1961 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1962 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1970 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1974 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFI [all...] |
H A D | amdgpu_mode.h | 301 uint64_t tiling_flags; member in struct:amdgpu_framebuffer
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/linux-master/include/uapi/drm/ |
H A D | radeon_drm.h | 858 __u32 tiling_flags; member in struct:drm_radeon_gem_set_tiling 864 __u32 tiling_flags; member in struct:drm_radeon_gem_get_tiling
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