#
a87076d3 |
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11-Jan-2024 |
XueBing Chen <chenxb_99091@126.com> |
drm/radeon/evergreen_cs: Clean up errors in evergreen_cs.c Fix the following errors reported by checkpatch: ERROR: space required after that ',' (ctx:VxV) ERROR: spaces required around that '>' (ctx:VxV) ERROR: spaces required around that '<' (ctx:VxV) Signed-off-by: XueBing Chen <chenxb_99091@126.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
f9eddd7c |
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16-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/radeon/evergreen_cs: Move 'r600_dma_cs_next_reloc()'s prototype to shared header Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/radeon/r600_cs.c:2343:5: warning: no previous prototype for ‘r600_dma_cs_next_reloc’ [-Wmissing-prototypes] 2343 | int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, | ^~~~~~~~~~~~~~~~~~~~~~ Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
33761307 |
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10-Nov-2020 |
Lee Jones <lee.jones@linaro.org> |
drm/radeon/evergreen_cs: Fix misnaming issues surrounding 'p' param Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/radeon/evergreen_cs.c:1026: warning: Function parameter or member 'p' not described in 'evergreen_cs_packet_parse_vline' drivers/gpu/drm/radeon/evergreen_cs.c:1026: warning: Excess function parameter 'parser' description in 'evergreen_cs_packet_parse_vline' drivers/gpu/drm/radeon/evergreen_cs.c:1095: warning: Function parameter or member 'p' not described in 'evergreen_cs_handle_reg' drivers/gpu/drm/radeon/evergreen_cs.c:1095: warning: Excess function parameter 'parser' description in 'evergreen_cs_handle_reg' drivers/gpu/drm/radeon/evergreen_cs.c:1757: warning: Function parameter or member 'p' not described in 'evergreen_is_safe_reg' drivers/gpu/drm/radeon/evergreen_cs.c:1757: warning: Excess function parameter 'parser' description in 'evergreen_is_safe_reg' Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c182615f |
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08-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/radeon: drop use of drmP.h (2/2) Drop use of drmP.h in remaining .c files. To ease review a little the drmP.h removal was divided in two commits. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190608080241.4958-8-sam@ravnborg.org
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#
cc5034a5 |
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15-Feb-2019 |
Gustavo A. R. Silva <gustavo@embeddedor.com> |
drm/radeon/evergreen_cs: fix missing break in switch statement Add missing break statement in order to prevent the code from falling through to case CB_TARGET_MASK. This bug was found thanks to the ongoing efforts to enable -Wimplicit-fallthrough. Fixes: dd220a00e8bd ("drm/radeon/kms: add support for streamout v7") Cc: stable@vger.kernel.org Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
59d76d6b |
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04-Oct-2018 |
Nick Alcock <nick.alcock@oracle.com> |
drm/radeon: ratelimit bo warnings So a few days ago I started getting sprays of these warnings -- sorry, but because it was a few days ago I'm not sure what I was running at the time (but it was probably either Stellaris or Chromium). Sep 25 22:06:34 mutilate err: : [ 544.718905] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.718909] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate err: : [ 544.719710] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.719714] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate err: : [ 544.719862] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.719865] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate err: : [ 544.720772] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc Sep 25 22:06:34 mutilate err: : [ 544.720778] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2! Sep 25 22:06:34 mutilate warning: : [ 544.721415] radeon 0000:01:00.0: vbo resource seems too big for the bo followed by a massive stream of "vbo resource seems too big for the bo". The most extreme flood ran from 23:01:58 to 23:02:47 and emitted 91,000 lines of log in that time. This... seems excessive, given that each log message after the first contains more or less no information. So ratelimit these messages. (We probably want to see at least *some* so that the underlying bug can be fixed -- always assuming the bug isn't in unfixable closed-source game code somewhere.) Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7ca85295 |
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28-Feb-2017 |
Joe Perches <joe@perches.com> |
gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level> Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
297b1286 |
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30-Sep-2016 |
Baoyou Xie <baoyou.xie@linaro.org> |
drm/radeon: add missing header dependencies We get a few warnings when building kernel with W=1: drivers/gpu/drm/radeon/radeon_clocks.c:35:10: warning: no previous prototype for 'radeon_legacy_get_engine_clock' [-Wmissing-prototypes] drivers/gpu/drm/radeon/atombios_encoders.c:75:1: warning: no previous prototype for 'atombios_get_backlight_level' [-Wmissing-prototypes] drivers/gpu/drm/radeon/r600_cs.c:2268:5: warning: no previous prototype for 'r600_cs_parse' [-Wmissing-prototypes] drivers/gpu/drm/radeon/evergreen_cs.c:2671:5: warning: no previous prototype for 'evergreen_cs_parse' [-Wmissing-prototypes] .... In fact, these functions are declared in drivers/gpu/drm/radeon/radeon_asic.h, so this patch adds missing header dependencies. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
662ce7bc |
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30-May-2016 |
Edmondo Tommasina <edmondo.tommasina@gmail.com> |
drm/radeon: allow PACKET3_PFP_SYNC_ME on evergreen Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
84ef4c12 |
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21-Apr-2016 |
Dave Airlie <airlied@redhat.com> |
drm/radeon: add cayman VM support for append packet. This adds support for SET_APPEND_CNT packet3 to the VM paths. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c4f2bbd |
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06-Apr-2016 |
Dave Airlie <airlied@redhat.com> |
drm/radeon: add support for SET_APPEND_CNT packet3 (v2) This adds support to the command parser for the set append counter packet3, this is required to support atomic counters on evergreen/cayman GPUs. v2: fixup some of the hardcoded numbers with real register names (Christian) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3cf8bb1a |
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15-Mar-2016 |
Jérome Glisse <jglisse@redhat.com> |
drm/radeon: fix indentation. I hate doing this but it hurts my eyes to go over code that does not comply with indentation rules. Only thing that is not only space change is in atom.c all other files are space indentation issues. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1c5dc335 |
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22-Aug-2015 |
Grazvydas Ignotas <notasas@gmail.com> |
drm/radeon: remove volatile qualifier There doesn't seem to be any need to have 'ib' volatile, the code is not even consistent with it and some places already miss it. As it is now it's just making gcc produce worse code. If there are special requirements for that memory, then proper primitives like memory barriers or accessor functions should be used, but it doesn't look like that is needed here. While at it, change the type to match the one in radeon_ib structure. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7874d390 |
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22-Aug-2015 |
Grazvydas Ignotas <notasas@gmail.com> |
drm/radeon: refactor register check loop After this patch the register check loop does the same thing as before, except that now gcc does better job optimizing it: it now sees that end_reg was already checked against PACKET3_SET_CONTEXT_REG_END and can optimize REG_SAFE_BM_SIZE comparison out of evergreen_is_safe_reg() as (PACKET3_SET_CONTEXT_REG_END >> 7) < REG_SAFE_BM_SIZE. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e5b69da6 |
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22-Aug-2015 |
Grazvydas Ignotas <notasas@gmail.com> |
drm/radeon: split evergreen_cs_check_reg evergreen_cs_check_reg() is a large function and gcc doesn't want to inline it. It has a quick check for reg_safe_bm[] to see if register needs special handling, which often results in early exit. However because the function is large, it has a long prologue/epilogue to save/restore all the callee-save registers which according to perf is taking significant amount of time. To avoid this, we can reuse evergreen_is_safe_reg() to do the early check directly in register loop. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4a985353 |
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22-Aug-2015 |
Grazvydas Ignotas <notasas@gmail.com> |
drm/radeon: simplify register checker To avoid having to distinguish between CAYMAN or older on every register check, place a pointer in evergreen_cs_track and use it unconditionally. Also make use of the fact that both reg_safe_bm[] arrays are of the same length to remove another CAYMAN check. Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
16613743 |
|
12-Dec-2014 |
Glenn Kennard <glenn.kennard@gmail.com> |
drm/radeon: evergreen/cayman indirect draw support (v2) Add the necessary set of commands to support OpenGL indirect draw calls on evergreen/cayman devices that do not have VM. v2: agd5f: fix warning on 32-bit Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6d2d13dd |
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03-Dec-2014 |
Christian König <christian.koenig@amd.com> |
drm/radeon: use pointers instead of indexes for CS chunks Nobody is interested at which index the chunk is. What's needed is a pointer to the chunk. Remove unused chunk_id field as well. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1d0c0942 |
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27-Nov-2014 |
Christian König <christian.koenig@amd.com> |
drm/radeon: rename radeon_cs_reloc to radeon_bo_list Better match what it is actually doing. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
df0af440 |
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02-Mar-2014 |
Christian König <christian.koenig@amd.com> |
drm/radeon: remove struct radeon_bo_list Just move all fields into radeon_cs_reloc, removing unused/duplicated fields. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
56492e0f |
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08-Jan-2014 |
Marek Olšák <marek.olsak@amd.com> |
drm/radeon: skip colorbuffer checking if COLOR_INFO.FORMAT is set to INVALID This fixes a bug which was causing rejections of valid GPU commands from userspace. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
774c389f |
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01-Mar-2013 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon: don't check mipmap alignment if MIP_ADDRESS is FMASK The MIP_ADDRESS state has 2 meanings. If the texture has one sample per pixel, it's a pointer to the mipmap chain. If the texture has multiple samples per pixel, it's a pointer to FMASK, a metadata buffer needed for reading compressed MSAA textures. The mipmap alignment rules do not apply to FMASK. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
de0babd6 |
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11-Feb-2013 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: enforce use of radeon_get_ib_value when reading user cmd When ever parsing cmd buffer supplied by userspace we need to use radeon_get_ib_value rather than directly accessing the ib as the user cmd might not yet be copied into the ib thus the parser might read value that does not correspond to what user is sending and possibly allowing user to send malicious command undected. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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#
0fcb6155 |
|
14-Jan-2013 |
Jerome Glisse <jglisse@redhat.com> |
radeon/kms: cleanup async dma packet checking This simplify and cleanup the async dma checking. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4e872ae2 |
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02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: consolidate redundant macros and constants After refactoring the _cs logic, we ended up with many macros and constants that #define the same thing. Clean'em up. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
012e976d |
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02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: use common next_reloc function This patch eliminates ASIC-specific ***_cs_packet_next_reloc functions and hooks up the new common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d6e18a34 |
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02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: add a check to wait_reg_mem command WAIT_REG_MEM on register does not allow the use of PFP. Enforce this restriction when checking packets sent from userland. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
40592a17 |
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02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: refactor vline packet parsing function vline packet parsing function for R600 and Evergreen+ are the same, except that they use different registers. Factor out the algorithm into a common function that uses register table passed from ASIC-specific caller. This reduces ASIC-specific function to (trivial) setup of register table and call into the common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9ffb7a6d |
|
02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: factor out cs_next_is_pkt3_nop function Once we factored out radeon_cs_packet_parse function, evergreen_cs_next_is_pkt3_nop and r600_cs_next_is_pkt3_nop functions became identical, so they can be factored out into a common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c38f34b5 |
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02-Jan-2013 |
Ilija Hadzic <ihadzic@research.bell-labs.com> |
drm/radeon: use common cs packet parse function We now have a common radeon_cs_packet_parse function that is good for all ASICs. Hook it up and eliminate ASIC-specific versions. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
668bbc81 |
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20-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add WAIT_UNTIL to evergreen VM safe reg list It's used in a recent mesa commit: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24b1206ab2dcd506aaac3ef656aebc8bc20cd27a and there may be some other cases in the future where it's required. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Cc: stable@vger.kernel.org
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#
4613ca14 |
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18-Dec-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: add support for MEM_WRITE packet To make it easier to debug some lockup from userspace add support to MEM_WRITE packet. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9d89d78e |
|
13-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add more pedantic checks in the CP DMA checker non-mem-to-mem transfers require dw aligned byte count. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
cd459e52 |
|
12-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add VM CS parser support for async DMA on cayman/TN/SI Allows us to use async DMA from userspace. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d2ead3ea |
|
13-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: add evergreen/cayman CS parser for async DMA (v2) Allows us to use the DMA ring from userspace. DMA doesn't have a good NOP packet in which to embed the reloc idx, so userspace has to add a reloc for each buffer used and order them to match the command stream. v2: fix address bounds checking Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4ac0533a |
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12-Dec-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: fix htile buffer size computation for command stream checker Fix the size computation of the htile buffer. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
94e014ee |
|
03-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cayman: add VM CS checker support for CP DMA Need to verify for copies involving registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8770b86b |
|
03-Dec-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add support for CP DMA packet to evergreen CS checker Currently only memory and GDS transfers are allowed. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
860fe2f0 |
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08-Nov-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/cayman: add some missing regs to the VM reg checker These regs were being wronly rejected leading to rendering issues. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=56876 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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#
74e4ca32 |
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24-Oct-2012 |
Peter Senna Tschudin <peter.senna@gmail.com> |
drivers/gpu/drm/radeon/evergreen_cs.c: Remove unnecessary semicolon A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r1@ statement S; position p,p1; @@ S@p1;@p @script:python r2@ p << r1.p; p1 << r1.p1; @@ if p[0].line != p1[0].line_end: cocci.include_match(False) @@ position r1.p; @@ -;@p // </smpl> Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c7172132 |
|
19-Oct-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon: add error output if VM CS fails on cayman So we know why the CS was rejected. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
760285e7 |
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02-Oct-2012 |
David Howells <dhowells@redhat.com> |
UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/ Convert #include "..." to #include <path/...> in drivers/gpu/. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
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#
61051afd |
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24-Sep-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon: allow MIP_ADDRESS=0 for MSAA textures on Evergreen MIP_ADDRESS should point to the resolved FMASK for an MSAA texture. Setting MIP_ADDRESS to 0 means the FMASK pointer is invalid (the GPU won't read the memory then). The userspace has to set MIP_ADDRESS to 0 and *not* emit any relocation for it. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
1109ca09 |
|
31-Aug-2012 |
Lauri Kasanen <cand@gmx.com> |
drm/radeon: Mark all possible functions / structs as static Let's allow GCC to optimize better. This exposed some five unused functions, but this patch doesn't remove them. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b51ad12a |
|
09-Aug-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: add MSAA texture support for r600-evergreen Most of the checking seems to be in place already. As you can see, log2(number of samples) resides in LAST_LEVEL. This is required for MSAA support (namely for depth-stencil resolve and blitting between MSAA resources). Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0f457e48 |
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29-Jul-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: allow "invalid" DB formats as a means to disable DB Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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d2609875 |
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09-Jun-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: fix tiling and command stream checking on evergreen v3 Fix regresson since the introduction of command stream checking on evergreen (thread referenced below). Issue is cause by ddx allocating bo with formula width*height*bpp while programming the GPU command stream with ALIGN(height, 8). In some case (where page alignment does not hide the extra size bo should be according to height alignment) the kernel will reject the command stream. This patch reprogram the command stream to slice - 1 (slice is a derivative value from height) which avoid rejecting the command stream while keeping the value of command stream checking from a security point of view. This patch also fix wrong computation of layer size for 2D tiled surface. Which should fix issue when 2D color tiling is enabled. This dump the radeon KMS_DRIVER_MINOR so userspace can know if they are on a fixed kernel or not. https://lkml.org/lkml/2012/6/3/80 https://bugs.freedesktop.org/show_bug.cgi?id=50892 https://bugs.freedesktop.org/show_bug.cgi?id=50857 !!! STABLE need a custom version of this patch for 3.4 !!! v2: actually bump the minor version and add comment about stable v3: do compute the height the ddx was trying to use [airlied: drop left over debug] Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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f2e39221 |
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09-May-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: make the ib an inline object No need to malloc it any more. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Dave Airlie <airlied@redhat.com>
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88f50c80 |
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21-Mar-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon/kms: add htile support to the cs checker v3 For 6xx+. Required for mesa to use htile support for HiZ/HiS. Userspace will check radeon version 2.14 with is bumped either by tiling patch or stream out patch. This patch only add support for htile relocation which should be enough for any userspace to implement the hyperz (using htile buffer) feature. v2: Jerome: Fix size checking for htile buffer. v3: Jerome: Adapt on top of r600/evergreen cs checker changes, also check htile surface in case only stencil is present. Signed-off-by: Pierre-Eric Pelloux-Prayer <pelloux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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747e42a10 |
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18-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: remove some unused variables in evergreen_cs_track and document the other unused ones. Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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30838578 |
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18-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: skip db/cb/streamout checking when possible on evergreen Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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7e9fa5f6 |
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18-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: optimize streamout checking for evergreen Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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78857131 |
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18-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: compute GPU addresses correctly on evergreen There are also two fixes: - In DRAW_INDEX_2, we read idx_value, but should have read idx+1. - When correcting SQ_VTX_CONSTANT_WORD1_0.SIZE, we should subtract the offset. Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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7df7c547 |
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18-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: make some DRM errors more informative Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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779923bc |
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07-Mar-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: skip cb/db checking if SX_MISC is 1 on r600+ Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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42b923b5 |
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14-Feb-2012 |
Dan Carpenter <dan.carpenter@oracle.com> |
drm/radeon/evergreen: make texdw[] array larger We store stuff in texdw[7] so this array needs to have 8 elements. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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285484e2 |
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16-Dec-2011 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: add support for evergreen/ni tiling informations v11 evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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dd220a00 |
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26-Jan-2012 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: add support for streamout v7 v2: agd5f: add strmout CS checking, copy_dw register checking v3: agd5f: don't use cs_check_reg() for copy_dw checking as it will incorrectly patch the command stream for certain regs. v4: agd5f: add warning if safe reg check fails for copy_dw v5: agd5f: add stricter checking for 6xx/7xx v6: agd5f: add range checking for copy_dw on eg+, add sx_surface_sync to safe reg list for 7xx. v7: agd5f: add stricter checking for eg+ Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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0b41da60 |
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12-Jan-2012 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms/ni: fix packet2 handling for VM IB parser Packet2 is only one dword. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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721604a1 |
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05-Jan-2012 |
Jerome Glisse <jglisse@redhat.com> |
drm/radeon: GPU virtual memory support v22 Virtual address space are per drm client (opener of /dev/drm). Client are in charge of virtual address space, they need to map bo into it by calling DRM_RADEON_GEM_VA ioctl. First 16M of virtual address space is reserved by the kernel. Once using 2 level page table we should be able to have a small vram memory footprint for each pt (there would be one pt for all gart, one for all vram and then one first level for each virtual address space). Plan include using the sub allocator for a common vm page table area and using memcpy to copy vm page table in & out. Or use a gart object and copy things in & out using dma. v2: agd5f fixes: - Add vram base offset for vram pages. The GPU physical address of a vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete cards and the physical bus address of the stolen memory on integrated chips. - VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1 v3: agd5f: - integrate with the semaphore/multi-ring stuff v4: - rebase on top ttm dma & multi-ring stuff - userspace is now in charge of the address space - no more specific cs vm ioctl, instead cs ioctl has a new chunk v5: - properly handle mem == NULL case from move_notify callback - fix the vm cleanup path v6: - fix update of page table to only happen on valid mem placement v7: - add tlb flush for each vm context - add flags to define mapping property (readable, writeable, snooped) - make ring id implicit from ib->fence->ring, up to each asic callback to then do ring specific scheduling if vm ib scheduling function v8: - add query for ib limit and kernel reserved virtual space - rename vm->size to max_pfn (maximum number of page) - update gem_va ioctl to also allow unmap operation - bump kernel version to allow userspace to query for vm support v9: - rebuild page table only when bind and incrementaly depending on bo referenced by cs and that have been moved - allow virtual address space to grow - use sa allocator for vram page table - return invalid when querying vm limit on non cayman GPU - dump vm fault register on lockup v10: agd5f: - Move the vm schedule_ib callback to a standalone function, remove the callback and use the existing ib_execute callback for VM IBs. v11: - rebase on top of lastest Linus v12: agd5f: - remove spurious backslash - set IB vm_id to 0 in radeon_ib_get() v13: agd5f: - fix handling of RADEON_CHUNK_ID_FLAGS v14: - fix va destruction - fix suspend resume - forbid bo to have several different va in same vm v15: - rebase v16: - cleanup left over of vm init/fini v17: agd5f: - cs checker v18: agd5f: - reworks the CS ioctl to better support multiple rings and VM. Rather than adding a new chunk id for VM, just re-use the IB chunk id and add a new flags for VM mode. Also define additional dwords for the flags chunk id to define the what ring we want to use (gfx, compute, uvd, etc.) and the priority. v19: - fix cs fini in weird case of no ib - semi working flush fix for ni - rebase on top of sa allocator changes v20: agd5f: - further CS ioctl cleanups from Christian's comments v21: agd5f: - integrate CS checker improvements v22: agd5f: - final cleanups for release, only allow VM CS on cayman Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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f3a71df0 |
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28-Nov-2011 |
Alex Deucher <alexander.deucher@amd.com> |
drm/radeon/kms: fix 2D tiling CS support on EG/CM Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43191 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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e70f224c |
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24-Oct-2011 |
Marek Olšák <maraeo@gmail.com> |
drm/radeon/kms: add a CS ioctl flag not to rewrite tiling flags in the CS This adds a new optional chunk to the CS ioctl that specifies optional flags to the CS parser. Why this is useful is explained below. Note that some regs no longer need the NOP relocation packet if this feature is enabled. Tested on r300g and r600g with this flag disabled and enabled. Assume there are two contexts sharing the same mipmapped tiled texture. One context wants to render into the first mipmap and the other one wants to render into the last mipmap. As you probably know, the hardware has a MACRO_SWITCH feature, which turns off macro tiling for small mipmaps, but that only applies to samplers. (at least on r300-r500, though later hardware likely behaves the same) So we want to just re-set the tiling flags before rendering (writing packets), right? ... No. The contexts run in parallel, so they may set the tiling flags simultaneously and then fire their command streams also simultaneously. The last one setting the flags wins, the other one loses. Another problem is when one context wants to render into the first and the last mipmap in one CS. Impossible. It must flush before changing tiling flags and do the rendering into the smaller mipmaps in another CS. Yet another problem is that writing copy_blit in userspace would be a mess involving re-setting tiling flags to please the kernel, and causing races with other contexts at the same time. The only way out of this is to send tiling flags with each CS, ideally with each relocation. But we already do that through the registers. So let's just use what we have in the registers. Signed-off-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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6a2f371d |
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13-Oct-2011 |
Andi Kleen <ak@linux.intel.com> |
drm/radeon: Remove now unused functions in radeon driver With the dropped inlines gccs starts warning about genuinely unused functions. Remove r600_bpe_from_format, evergreen_cs_track_validate_cb, evergreen-cs_packet_next_is_pkt3_nop which are all unused. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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488479eb |
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13-Oct-2011 |
Andi Kleen <ak@linux.intel.com> |
drm/radeon: Drop inlines from evergreen_cs.c / r600_cs.c Fixes evergreen_cs_parse 4080 23124 +19044 and others compared to a non force inline kernel. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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88498839 |
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27-Jul-2011 |
Dan Carpenter <error27@gmail.com> |
drm/radeon: off by one in check_reg() functions This off by one range check was copy and pasted a couple places. It's not really harmful, but we should fix it anyway. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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033b5650 |
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08-Jun-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add initial CS checker support for compute - Add some new compute regs - Add new dispatch packets for evergreen/cayman Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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25985edc |
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30-Mar-2011 |
Lucas De Marchi <lucas.demarchi@profusion.mobi> |
Fix common misspellings Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
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a3a88a66 |
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16-Mar-2011 |
Paul Bolle <pebolle@tiscali.nl> |
drm: radeon: *_cs_packet_parse_vline() cleanup Simplify the way the return value is set a number of times (mostly on error). Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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8aa75009 |
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02-Mar-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: cayman/evergreen cs checker updates Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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c175ca9a |
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02-Mar-2011 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: add cayman CS check support Added to existing evergreen CS checker. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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2a19cac8 |
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27-Feb-2011 |
Dave Airlie <airlied@redhat.com> |
drm/r600: parse the set predication command. (v2) This is required for NV_conditional_render and EXT_transform_feedback. v2: add evergreen support. Signed-off-by: Dave Airlie <airlied@redhat.com>
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29508eb6 |
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21-Jul-2010 |
Dave Airlie <airlied@redhat.com> |
drm/radeon/kms: drop taking lock around crtc lookup. We only add/remove crtcs at driver load, you cannot remove when the GPU is running a CS packet since the fd is open, when GPU hotplugging on radeons actually is needed all this locking needs a review and I've started re-working kms core locking to deal with this better. But for now avoid long delays in CS processing when hotplug detect is happening in a different thread. this fixes a regression introduced with hotplug detection. Signed-off-by: Dave Airlie <airlied@redhat.com>
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09d7e785 |
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23-Jun-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms: fix typos in evergreen command checker Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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cb5fcbd5 |
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28-May-2010 |
Alex Deucher <alexdeucher@gmail.com> |
drm/radeon/kms/evergreen: add initial CS parser Advanced validation is not implemented yet. The mesa code that uses this will be released soon. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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