| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | smu_v12_0.c | 344 smu->smu_table.boot_values.socclk = 0;
361 smu->smu_table.boot_values.socclk = 0;
378 &smu->smu_table.boot_values.socclk);
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| H A D | renoir_ppt.c | 300 clock_limit = smu->smu_table.boot_values.socclk;
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| /linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | dcn_calcs.h | 127 float socclk; member in struct:dcn_bw_internal_vars
564 float socclk; /*MHz*/ member in struct:dcn_soc_bounding_box
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0.c | 566 smu->smu_table.boot_values.socclk = 0;
580 smu->smu_table.boot_values.socclk = 0;
595 smu->smu_table.boot_values.socclk = 0;
617 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
626 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
953 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | smu_v14_0_0_ppt.c | 762 clock_limit = smu->smu_table.boot_values.socclk;
882 clock_limit = smu->smu_table.boot_values.socclk;
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | smu_v11_0.c | 557 smu->smu_table.boot_values.socclk = 0;
574 smu->smu_table.boot_values.socclk = 0;
591 &smu->smu_table.boot_values.socclk);
838 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
1722 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | vangogh_ppt.c | 605 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
708 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
914 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | arcturus_ppt.c | 334 /* socclk dpm table setup */
346 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
715 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
807 dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
951 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
1011 * support mclk/socclk/fclk softmin/softmax settings
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| H A D | navi10_ppt.c | 973 /* socclk dpm table setup */
985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
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| H A D | sienna_cichlid_ppt.c | 962 /* socclk dpm table setup */
975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0.c | 609 smu->smu_table.boot_values.socclk = 0;
623 smu->smu_table.boot_values.socclk = 0;
638 smu->smu_table.boot_values.socclk = 0;
660 smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz;
669 smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz;
893 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
1572 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | smu_v13_0_5_ppt.c | 743 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | smu_v13_0_4_ppt.c | 766 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | yellow_carp_ppt.c | 877 clock_limit = smu->smu_table.boot_values.socclk;
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| H A D | aldebaran_ppt.c | 316 /* socclk dpm table setup */
326 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
692 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
807 dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string);
935 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
988 * support mclk/socclk/fclk softmin/softmax settings
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| H A D | smu_v13_0_7_ppt.c | 584 /* socclk dpm table setup */
594 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
909 /* socclk dpm table */
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| H A D | smu_v13_0_0_ppt.c | 577 /* socclk dpm table setup */
587 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
920 /* socclk dpm table */
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| /linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 113 .socclk = 208, /*MHz*/
498 input->clks_cfg.socclk_mhz = v->socclk;
797 v->socclk = dc->dcn_soc->socclk;
1497 *socclk_khz = dc->dcn_soc->socclk * 1000;
1582 "socclk: %f kHz\n"
1616 dc->dcn_soc->socclk * 1000,
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| H A D | dcn_calc_auto.c | 1337 v->writeback_dram_clock_change_watermark = v->dram_clock_change_latency + v->write_back_latency + v->writeback_chunk_size * 1024.0 / 32.0 / v->socclk;
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/ |
| H A D | amdgpu_smu.h | 289 uint32_t socclk; member in struct:smu_bios_boot_up_values
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| /linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega10_hwmgr.c | 517 uint16_t virtual_voltage_id, int32_t *socclk)
539 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
515 vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t virtual_voltage_id, int32_t *socclk) argument
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| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 477 unsigned int socclk = context->bw_ctx.dml.vba.SOCCLKPerState[vlevel]; local
505 pipes[0].clks_cfg.socclk_mhz = socclk;
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