1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "smu_types.h" 25#define SWSMU_CODE_LAYER_L2 26 27#include "amdgpu.h" 28#include "amdgpu_smu.h" 29#include "smu_v13_0.h" 30#include "smu13_driver_if_v13_0_4.h" 31#include "smu_v13_0_4_ppt.h" 32#include "smu_v13_0_4_ppsmc.h" 33#include "smu_v13_0_4_pmfw.h" 34#include "smu_cmn.h" 35 36/* 37 * DO NOT use these for err/warn/info/debug messages. 38 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 39 * They are more MGPU friendly. 40 */ 41#undef pr_err 42#undef pr_warn 43#undef pr_info 44#undef pr_debug 45 46#define mmMP1_SMN_C2PMSG_66 0x0282 47#define mmMP1_SMN_C2PMSG_66_BASE_IDX 1 48 49#define mmMP1_SMN_C2PMSG_82 0x0292 50#define mmMP1_SMN_C2PMSG_82_BASE_IDX 1 51 52#define mmMP1_SMN_C2PMSG_90 0x029a 53#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1 54 55#define FEATURE_MASK(feature) (1ULL << feature) 56 57#define SMU_13_0_4_UMD_PSTATE_GFXCLK 938 58#define SMU_13_0_4_UMD_PSTATE_SOCCLK 938 59#define SMU_13_0_4_UMD_PSTATE_FCLK 1875 60 61#define SMC_DPM_FEATURE ( \ 62 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ 63 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ 64 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ 65 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ 66 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ 67 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ 68 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ 69 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ 70 FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \ 71 FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ 72 FEATURE_MASK(FEATURE_GFX_DPM_BIT)) 73 74static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = { 75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1), 77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), 78 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), 79 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), 80 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), 81 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), 82 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1), 83 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), 84 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1), 85 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1), 86 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), 87 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), 88 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), 89 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), 90 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1), 91 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), 92 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1), 93 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1), 94 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), 95 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1), 96 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), 97 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), 98 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), 99 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1), 100 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), 101 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), 102 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1), 103 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1), 104 MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1), 105 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1), 106 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1), 107}; 108 109static struct cmn2asic_mapping smu_v13_0_4_feature_mask_map[SMU_FEATURE_COUNT] = { 110 FEA_MAP(CCLK_DPM), 111 FEA_MAP(FAN_CONTROLLER), 112 FEA_MAP(PPT), 113 FEA_MAP(TDC), 114 FEA_MAP(THERMAL), 115 FEA_MAP(VCN_DPM), 116 FEA_MAP_REVERSE(FCLK), 117 FEA_MAP_REVERSE(SOCCLK), 118 FEA_MAP(LCLK_DPM), 119 FEA_MAP(SHUBCLK_DPM), 120 FEA_MAP(DCFCLK_DPM), 121 FEA_MAP_HALF_REVERSE(GFX), 122 FEA_MAP(DS_GFXCLK), 123 FEA_MAP(DS_SOCCLK), 124 FEA_MAP(DS_LCLK), 125 FEA_MAP(DS_DCFCLK), 126 FEA_MAP(DS_FCLK), 127 FEA_MAP(DS_MP1CLK), 128 FEA_MAP(DS_MP0CLK), 129 FEA_MAP(GFX_DEM), 130 FEA_MAP(PSI), 131 FEA_MAP(PROCHOT), 132 FEA_MAP(CPUOFF), 133 FEA_MAP(STAPM), 134 FEA_MAP(S0I3), 135 FEA_MAP(PERF_LIMIT), 136 FEA_MAP(CORE_DLDO), 137 FEA_MAP(DS_VCN), 138 FEA_MAP(CPPC), 139 FEA_MAP(DF_CSTATES), 140 FEA_MAP(ATHUB_PG), 141}; 142 143static struct cmn2asic_mapping smu_v13_0_4_table_map[SMU_TABLE_COUNT] = { 144 TAB_MAP_VALID(WATERMARKS), 145 TAB_MAP_VALID(SMU_METRICS), 146 TAB_MAP_VALID(CUSTOM_DPM), 147 TAB_MAP_VALID(DPMCLOCKS), 148}; 149 150static int smu_v13_0_4_init_smc_tables(struct smu_context *smu) 151{ 152 struct smu_table_context *smu_table = &smu->smu_table; 153 struct smu_table *tables = smu_table->tables; 154 155 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), 156 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 157 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), 158 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 159 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), 160 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); 161 162 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); 163 if (!smu_table->clocks_table) 164 goto err0_out; 165 166 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); 167 if (!smu_table->metrics_table) 168 goto err1_out; 169 smu_table->metrics_time = 0; 170 171 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); 172 if (!smu_table->watermarks_table) 173 goto err2_out; 174 175 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); 176 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); 177 if (!smu_table->gpu_metrics_table) 178 goto err3_out; 179 180 return 0; 181 182err3_out: 183 kfree(smu_table->watermarks_table); 184err2_out: 185 kfree(smu_table->metrics_table); 186err1_out: 187 kfree(smu_table->clocks_table); 188err0_out: 189 return -ENOMEM; 190} 191 192static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) 193{ 194 struct smu_table_context *smu_table = &smu->smu_table; 195 196 kfree(smu_table->clocks_table); 197 smu_table->clocks_table = NULL; 198 199 kfree(smu_table->metrics_table); 200 smu_table->metrics_table = NULL; 201 202 kfree(smu_table->watermarks_table); 203 smu_table->watermarks_table = NULL; 204 205 kfree(smu_table->gpu_metrics_table); 206 smu_table->gpu_metrics_table = NULL; 207 208 return 0; 209} 210 211static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) 212{ 213 int ret = 0; 214 uint64_t feature_enabled; 215 216 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); 217 218 if (ret) 219 return false; 220 221 return !!(feature_enabled & SMC_DPM_FEATURE); 222} 223 224static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) 225{ 226 struct amdgpu_device *adev = smu->adev; 227 int ret = 0; 228 229 if (!en && !adev->in_s0ix) { 230 /* Adds a GFX reset as workaround just before sending the 231 * MP1_UNLOAD message to prevent GC/RLC/PMFW from entering 232 * an invalid state. 233 */ 234 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, 235 SMU_RESET_MODE_2, NULL); 236 if (ret) 237 return ret; 238 239 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); 240 } 241 242 return ret; 243} 244 245static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu, 246 void **table) 247{ 248 struct smu_table_context *smu_table = &smu->smu_table; 249 struct gpu_metrics_v2_1 *gpu_metrics = 250 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; 251 SmuMetrics_t metrics; 252 int ret = 0; 253 254 ret = smu_cmn_get_metrics_table(smu, &metrics, true); 255 if (ret) 256 return ret; 257 258 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1); 259 260 gpu_metrics->temperature_gfx = metrics.GfxTemperature; 261 gpu_metrics->temperature_soc = metrics.SocTemperature; 262 memcpy(&gpu_metrics->temperature_core[0], 263 &metrics.CoreTemperature[0], 264 sizeof(uint16_t) * 8); 265 gpu_metrics->temperature_l3[0] = metrics.L3Temperature; 266 267 gpu_metrics->average_gfx_activity = metrics.GfxActivity; 268 gpu_metrics->average_mm_activity = metrics.UvdActivity; 269 270 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 271 gpu_metrics->average_gfx_power = metrics.Power[0]; 272 gpu_metrics->average_soc_power = metrics.Power[1]; 273 memcpy(&gpu_metrics->average_core_power[0], 274 &metrics.CorePower[0], 275 sizeof(uint16_t) * 8); 276 277 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; 278 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; 279 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; 280 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency; 281 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; 282 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency; 283 284 memcpy(&gpu_metrics->current_coreclk[0], 285 &metrics.CoreFrequency[0], 286 sizeof(uint16_t) * 8); 287 gpu_metrics->current_l3clk[0] = metrics.L3Frequency; 288 289 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 290 291 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 292 293 *table = (void *)gpu_metrics; 294 295 return sizeof(struct gpu_metrics_v2_1); 296} 297 298static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu, 299 MetricsMember_t member, 300 uint32_t *value) 301{ 302 struct smu_table_context *smu_table = &smu->smu_table; 303 304 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; 305 int ret = 0; 306 307 ret = smu_cmn_get_metrics_table(smu, NULL, false); 308 if (ret) 309 return ret; 310 311 switch (member) { 312 case METRICS_AVERAGE_GFXCLK: 313 *value = metrics->GfxclkFrequency; 314 break; 315 case METRICS_AVERAGE_SOCCLK: 316 *value = metrics->SocclkFrequency; 317 break; 318 case METRICS_AVERAGE_VCLK: 319 *value = metrics->VclkFrequency; 320 break; 321 case METRICS_AVERAGE_DCLK: 322 *value = metrics->DclkFrequency; 323 break; 324 case METRICS_AVERAGE_UCLK: 325 *value = metrics->MemclkFrequency; 326 break; 327 case METRICS_AVERAGE_GFXACTIVITY: 328 *value = metrics->GfxActivity / 100; 329 break; 330 case METRICS_AVERAGE_VCNACTIVITY: 331 *value = metrics->UvdActivity; 332 break; 333 case METRICS_AVERAGE_SOCKETPOWER: 334 *value = (metrics->AverageSocketPower << 8) / 1000; 335 break; 336 case METRICS_CURR_SOCKETPOWER: 337 *value = (metrics->CurrentSocketPower << 8) / 1000; 338 break; 339 case METRICS_TEMPERATURE_EDGE: 340 *value = metrics->GfxTemperature / 100 * 341 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 342 break; 343 case METRICS_TEMPERATURE_HOTSPOT: 344 *value = metrics->SocTemperature / 100 * 345 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; 346 break; 347 case METRICS_THROTTLER_STATUS: 348 *value = metrics->ThrottlerStatus; 349 break; 350 case METRICS_VOLTAGE_VDDGFX: 351 *value = metrics->Voltage[0]; 352 break; 353 case METRICS_VOLTAGE_VDDSOC: 354 *value = metrics->Voltage[1]; 355 break; 356 case METRICS_SS_APU_SHARE: 357 /* return the percentage of APU power with respect to APU's power limit. 358 * percentage is reported, this isn't boost value. Smartshift power 359 * boost/shift is only when the percentage is more than 100. 360 */ 361 if (metrics->StapmOpnLimit > 0) 362 *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit; 363 else 364 *value = 0; 365 break; 366 case METRICS_SS_DGPU_SHARE: 367 /* return the percentage of dGPU power with respect to dGPU's power limit. 368 * percentage is reported, this isn't boost value. Smartshift power 369 * boost/shift is only when the percentage is more than 100. 370 */ 371 if ((metrics->dGpuPower > 0) && 372 (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)) 373 *value = (metrics->dGpuPower * 100) / 374 (metrics->StapmCurrentLimit - metrics->StapmOpnLimit); 375 else 376 *value = 0; 377 break; 378 default: 379 *value = UINT_MAX; 380 break; 381 } 382 383 return ret; 384} 385 386static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu, 387 enum smu_clk_type clk_type, 388 uint32_t *value) 389{ 390 MetricsMember_t member_type; 391 392 switch (clk_type) { 393 case SMU_SOCCLK: 394 member_type = METRICS_AVERAGE_SOCCLK; 395 break; 396 case SMU_VCLK: 397 member_type = METRICS_AVERAGE_VCLK; 398 break; 399 case SMU_DCLK: 400 member_type = METRICS_AVERAGE_DCLK; 401 break; 402 case SMU_MCLK: 403 member_type = METRICS_AVERAGE_UCLK; 404 break; 405 case SMU_FCLK: 406 return smu_cmn_send_smc_msg_with_param(smu, 407 SMU_MSG_GetFclkFrequency, 408 0, value); 409 case SMU_GFXCLK: 410 case SMU_SCLK: 411 return smu_cmn_send_smc_msg_with_param(smu, 412 SMU_MSG_GetGfxclkFrequency, 413 0, value); 414 break; 415 default: 416 return -EINVAL; 417 } 418 419 return smu_v13_0_4_get_smu_metrics_data(smu, member_type, value); 420} 421 422static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu, 423 enum smu_clk_type clk_type, 424 uint32_t dpm_level, 425 uint32_t *freq) 426{ 427 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 428 429 if (!clk_table || clk_type >= SMU_CLK_COUNT) 430 return -EINVAL; 431 432 switch (clk_type) { 433 case SMU_SOCCLK: 434 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) 435 return -EINVAL; 436 *freq = clk_table->SocClocks[dpm_level]; 437 break; 438 case SMU_VCLK: 439 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 440 return -EINVAL; 441 *freq = clk_table->VClocks[dpm_level]; 442 break; 443 case SMU_DCLK: 444 if (dpm_level >= clk_table->VcnClkLevelsEnabled) 445 return -EINVAL; 446 *freq = clk_table->DClocks[dpm_level]; 447 break; 448 case SMU_UCLK: 449 case SMU_MCLK: 450 if (dpm_level >= clk_table->NumDfPstatesEnabled) 451 return -EINVAL; 452 *freq = clk_table->DfPstateTable[dpm_level].MemClk; 453 break; 454 case SMU_FCLK: 455 if (dpm_level >= clk_table->NumDfPstatesEnabled) 456 return -EINVAL; 457 *freq = clk_table->DfPstateTable[dpm_level].FClk; 458 break; 459 default: 460 return -EINVAL; 461 } 462 463 return 0; 464} 465 466static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu, 467 enum smu_clk_type clk_type, 468 uint32_t *count) 469{ 470 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 471 472 switch (clk_type) { 473 case SMU_SOCCLK: 474 *count = clk_table->NumSocClkLevelsEnabled; 475 break; 476 case SMU_VCLK: 477 *count = clk_table->VcnClkLevelsEnabled; 478 break; 479 case SMU_DCLK: 480 *count = clk_table->VcnClkLevelsEnabled; 481 break; 482 case SMU_MCLK: 483 *count = clk_table->NumDfPstatesEnabled; 484 break; 485 case SMU_FCLK: 486 *count = clk_table->NumDfPstatesEnabled; 487 break; 488 default: 489 break; 490 } 491 492 return 0; 493} 494 495static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, 496 enum smu_clk_type clk_type, char *buf) 497{ 498 int i, idx, size = 0, ret = 0; 499 uint32_t cur_value = 0, value = 0, count = 0; 500 uint32_t min, max; 501 502 smu_cmn_get_sysfs_buf(&buf, &size); 503 504 switch (clk_type) { 505 case SMU_OD_SCLK: 506 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 507 size += sysfs_emit_at(buf, size, "0: %10uMhz\n", 508 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); 509 size += sysfs_emit_at(buf, size, "1: %10uMhz\n", 510 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); 511 break; 512 case SMU_OD_RANGE: 513 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 514 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", 515 smu->gfx_default_hard_min_freq, 516 smu->gfx_default_soft_max_freq); 517 break; 518 case SMU_SOCCLK: 519 case SMU_VCLK: 520 case SMU_DCLK: 521 case SMU_MCLK: 522 case SMU_FCLK: 523 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); 524 if (ret) 525 break; 526 527 ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count); 528 if (ret) 529 break; 530 531 for (i = 0; i < count; i++) { 532 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; 533 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value); 534 if (ret) 535 break; 536 537 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, 538 cur_value == value ? "*" : ""); 539 } 540 break; 541 case SMU_GFXCLK: 542 case SMU_SCLK: 543 ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); 544 if (ret) 545 break; 546 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; 547 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; 548 if (cur_value == max) 549 i = 2; 550 else if (cur_value == min) 551 i = 0; 552 else 553 i = 1; 554 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, 555 i == 0 ? "*" : ""); 556 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 557 i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */ 558 i == 1 ? "*" : ""); 559 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, 560 i == 2 ? "*" : ""); 561 break; 562 default: 563 break; 564 } 565 566 return size; 567} 568 569static int smu_v13_0_4_read_sensor(struct smu_context *smu, 570 enum amd_pp_sensors sensor, 571 void *data, uint32_t *size) 572{ 573 int ret = 0; 574 575 if (!data || !size) 576 return -EINVAL; 577 578 switch (sensor) { 579 case AMDGPU_PP_SENSOR_GPU_LOAD: 580 ret = smu_v13_0_4_get_smu_metrics_data(smu, 581 METRICS_AVERAGE_GFXACTIVITY, 582 (uint32_t *)data); 583 *size = 4; 584 break; 585 case AMDGPU_PP_SENSOR_GPU_AVG_POWER: 586 ret = smu_v13_0_4_get_smu_metrics_data(smu, 587 METRICS_AVERAGE_SOCKETPOWER, 588 (uint32_t *)data); 589 *size = 4; 590 break; 591 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 592 ret = smu_v13_0_4_get_smu_metrics_data(smu, 593 METRICS_CURR_SOCKETPOWER, 594 (uint32_t *)data); 595 *size = 4; 596 break; 597 case AMDGPU_PP_SENSOR_EDGE_TEMP: 598 ret = smu_v13_0_4_get_smu_metrics_data(smu, 599 METRICS_TEMPERATURE_EDGE, 600 (uint32_t *)data); 601 *size = 4; 602 break; 603 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 604 ret = smu_v13_0_4_get_smu_metrics_data(smu, 605 METRICS_TEMPERATURE_HOTSPOT, 606 (uint32_t *)data); 607 *size = 4; 608 break; 609 case AMDGPU_PP_SENSOR_GFX_MCLK: 610 ret = smu_v13_0_4_get_smu_metrics_data(smu, 611 METRICS_AVERAGE_UCLK, 612 (uint32_t *)data); 613 *(uint32_t *)data *= 100; 614 *size = 4; 615 break; 616 case AMDGPU_PP_SENSOR_GFX_SCLK: 617 ret = smu_v13_0_4_get_smu_metrics_data(smu, 618 METRICS_AVERAGE_GFXCLK, 619 (uint32_t *)data); 620 *(uint32_t *)data *= 100; 621 *size = 4; 622 break; 623 case AMDGPU_PP_SENSOR_VDDGFX: 624 ret = smu_v13_0_4_get_smu_metrics_data(smu, 625 METRICS_VOLTAGE_VDDGFX, 626 (uint32_t *)data); 627 *size = 4; 628 break; 629 case AMDGPU_PP_SENSOR_VDDNB: 630 ret = smu_v13_0_4_get_smu_metrics_data(smu, 631 METRICS_VOLTAGE_VDDSOC, 632 (uint32_t *)data); 633 *size = 4; 634 break; 635 case AMDGPU_PP_SENSOR_SS_APU_SHARE: 636 ret = smu_v13_0_4_get_smu_metrics_data(smu, 637 METRICS_SS_APU_SHARE, 638 (uint32_t *)data); 639 *size = 4; 640 break; 641 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: 642 ret = smu_v13_0_4_get_smu_metrics_data(smu, 643 METRICS_SS_DGPU_SHARE, 644 (uint32_t *)data); 645 *size = 4; 646 break; 647 default: 648 ret = -EOPNOTSUPP; 649 break; 650 } 651 652 return ret; 653} 654 655static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu, 656 struct pp_smu_wm_range_sets *clock_ranges) 657{ 658 int i; 659 int ret = 0; 660 Watermarks_t *table = smu->smu_table.watermarks_table; 661 662 if (!table || !clock_ranges) 663 return -EINVAL; 664 665 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || 666 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) 667 return -EINVAL; 668 669 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { 670 table->WatermarkRow[WM_DCFCLK][i].MinClock = 671 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; 672 table->WatermarkRow[WM_DCFCLK][i].MaxClock = 673 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; 674 table->WatermarkRow[WM_DCFCLK][i].MinMclk = 675 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; 676 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = 677 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; 678 679 table->WatermarkRow[WM_DCFCLK][i].WmSetting = 680 clock_ranges->reader_wm_sets[i].wm_inst; 681 } 682 683 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { 684 table->WatermarkRow[WM_SOCCLK][i].MinClock = 685 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; 686 table->WatermarkRow[WM_SOCCLK][i].MaxClock = 687 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; 688 table->WatermarkRow[WM_SOCCLK][i].MinMclk = 689 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; 690 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = 691 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; 692 693 table->WatermarkRow[WM_SOCCLK][i].WmSetting = 694 clock_ranges->writer_wm_sets[i].wm_inst; 695 } 696 697 smu->watermarks_bitmap |= WATERMARKS_EXIST; 698 699 /* pass data to smu controller */ 700 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && 701 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { 702 ret = smu_cmn_write_watermarks_table(smu); 703 if (ret) { 704 dev_err(smu->adev->dev, "Failed to update WMTABLE!"); 705 return ret; 706 } 707 smu->watermarks_bitmap |= WATERMARKS_LOADED; 708 } 709 710 return 0; 711} 712 713static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu, 714 enum smu_clk_type clk_type) 715{ 716 enum smu_feature_mask feature_id = 0; 717 718 switch (clk_type) { 719 case SMU_MCLK: 720 case SMU_UCLK: 721 case SMU_FCLK: 722 feature_id = SMU_FEATURE_DPM_FCLK_BIT; 723 break; 724 case SMU_GFXCLK: 725 case SMU_SCLK: 726 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; 727 break; 728 case SMU_SOCCLK: 729 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; 730 break; 731 case SMU_VCLK: 732 case SMU_DCLK: 733 feature_id = SMU_FEATURE_VCN_DPM_BIT; 734 break; 735 default: 736 return true; 737 } 738 739 return smu_cmn_feature_is_enabled(smu, feature_id); 740} 741 742static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu, 743 enum smu_clk_type clk_type, 744 uint32_t *min, 745 uint32_t *max) 746{ 747 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 748 uint32_t clock_limit; 749 uint32_t max_dpm_level, min_dpm_level; 750 int ret = 0; 751 752 if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) { 753 switch (clk_type) { 754 case SMU_MCLK: 755 case SMU_UCLK: 756 clock_limit = smu->smu_table.boot_values.uclk; 757 break; 758 case SMU_FCLK: 759 clock_limit = smu->smu_table.boot_values.fclk; 760 break; 761 case SMU_GFXCLK: 762 case SMU_SCLK: 763 clock_limit = smu->smu_table.boot_values.gfxclk; 764 break; 765 case SMU_SOCCLK: 766 clock_limit = smu->smu_table.boot_values.socclk; 767 break; 768 case SMU_VCLK: 769 clock_limit = smu->smu_table.boot_values.vclk; 770 break; 771 case SMU_DCLK: 772 clock_limit = smu->smu_table.boot_values.dclk; 773 break; 774 default: 775 clock_limit = 0; 776 break; 777 } 778 779 /* clock in Mhz unit */ 780 if (min) 781 *min = clock_limit / 100; 782 if (max) 783 *max = clock_limit / 100; 784 785 return 0; 786 } 787 788 if (max) { 789 switch (clk_type) { 790 case SMU_GFXCLK: 791 case SMU_SCLK: 792 *max = clk_table->MaxGfxClk; 793 break; 794 case SMU_MCLK: 795 case SMU_UCLK: 796 case SMU_FCLK: 797 max_dpm_level = 0; 798 break; 799 case SMU_SOCCLK: 800 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; 801 break; 802 case SMU_VCLK: 803 case SMU_DCLK: 804 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; 805 break; 806 default: 807 return -EINVAL; 808 } 809 810 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 811 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, 812 max_dpm_level, 813 max); 814 if (ret) 815 return ret; 816 } 817 } 818 819 if (min) { 820 switch (clk_type) { 821 case SMU_GFXCLK: 822 case SMU_SCLK: 823 *min = clk_table->MinGfxClk; 824 break; 825 case SMU_MCLK: 826 case SMU_UCLK: 827 case SMU_FCLK: 828 min_dpm_level = clk_table->NumDfPstatesEnabled - 1; 829 break; 830 case SMU_SOCCLK: 831 min_dpm_level = 0; 832 break; 833 case SMU_VCLK: 834 case SMU_DCLK: 835 min_dpm_level = 0; 836 break; 837 default: 838 return -EINVAL; 839 } 840 841 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { 842 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, 843 min_dpm_level, 844 min); 845 } 846 } 847 848 return ret; 849} 850 851static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu, 852 enum smu_clk_type clk_type, 853 uint32_t min, 854 uint32_t max) 855{ 856 enum smu_message_type msg_set_min, msg_set_max; 857 uint32_t min_clk = min; 858 uint32_t max_clk = max; 859 int ret = 0; 860 861 if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) 862 return -EINVAL; 863 864 switch (clk_type) { 865 case SMU_GFXCLK: 866 case SMU_SCLK: 867 msg_set_min = SMU_MSG_SetHardMinGfxClk; 868 msg_set_max = SMU_MSG_SetSoftMaxGfxClk; 869 break; 870 case SMU_FCLK: 871 msg_set_min = SMU_MSG_SetHardMinFclkByFreq; 872 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; 873 break; 874 case SMU_SOCCLK: 875 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq; 876 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; 877 break; 878 case SMU_VCLK: 879 case SMU_DCLK: 880 msg_set_min = SMU_MSG_SetHardMinVcn; 881 msg_set_max = SMU_MSG_SetSoftMaxVcn; 882 break; 883 default: 884 return -EINVAL; 885 } 886 887 if (clk_type == SMU_VCLK) { 888 min_clk = min << SMU_13_VCLK_SHIFT; 889 max_clk = max << SMU_13_VCLK_SHIFT; 890 } 891 892 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL); 893 if (ret) 894 return ret; 895 896 return smu_cmn_send_smc_msg_with_param(smu, msg_set_max, 897 max_clk, NULL); 898} 899 900static int smu_v13_0_4_force_clk_levels(struct smu_context *smu, 901 enum smu_clk_type clk_type, 902 uint32_t mask) 903{ 904 uint32_t soft_min_level = 0, soft_max_level = 0; 905 uint32_t min_freq = 0, max_freq = 0; 906 int ret = 0; 907 908 soft_min_level = mask ? (ffs(mask) - 1) : 0; 909 soft_max_level = mask ? (fls(mask) - 1) : 0; 910 911 switch (clk_type) { 912 case SMU_SOCCLK: 913 case SMU_FCLK: 914 case SMU_VCLK: 915 case SMU_DCLK: 916 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); 917 if (ret) 918 break; 919 920 ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); 921 if (ret) 922 break; 923 924 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); 925 break; 926 default: 927 ret = -EINVAL; 928 break; 929 } 930 931 return ret; 932} 933 934static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu, 935 enum amd_dpm_forced_level level, 936 enum smu_clk_type clk_type, 937 uint32_t *min_clk, 938 uint32_t *max_clk) 939{ 940 int ret = 0; 941 uint32_t clk_limit = 0; 942 943 switch (clk_type) { 944 case SMU_GFXCLK: 945 case SMU_SCLK: 946 clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK; 947 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 948 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit); 949 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 950 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL); 951 break; 952 case SMU_SOCCLK: 953 clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK; 954 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 955 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit); 956 break; 957 case SMU_FCLK: 958 clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK; 959 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 960 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit); 961 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) 962 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL); 963 break; 964 case SMU_VCLK: 965 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit); 966 break; 967 case SMU_DCLK: 968 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit); 969 break; 970 default: 971 ret = -EINVAL; 972 break; 973 } 974 *min_clk = *max_clk = clk_limit; 975 return ret; 976} 977 978static int smu_v13_0_4_set_performance_level(struct smu_context *smu, 979 enum amd_dpm_forced_level level) 980{ 981 struct amdgpu_device *adev = smu->adev; 982 uint32_t sclk_min = 0, sclk_max = 0; 983 uint32_t fclk_min = 0, fclk_max = 0; 984 uint32_t socclk_min = 0, socclk_max = 0; 985 uint32_t vclk_min = 0, vclk_max = 0; 986 uint32_t dclk_min = 0, dclk_max = 0; 987 int ret = 0; 988 989 switch (level) { 990 case AMD_DPM_FORCED_LEVEL_HIGH: 991 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); 992 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max); 993 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max); 994 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max); 995 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); 996 sclk_min = sclk_max; 997 fclk_min = fclk_max; 998 socclk_min = socclk_max; 999 vclk_min = vclk_max; 1000 dclk_min = dclk_max; 1001 break; 1002 case AMD_DPM_FORCED_LEVEL_LOW: 1003 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); 1004 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL); 1005 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL); 1006 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL); 1007 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL); 1008 sclk_max = sclk_min; 1009 fclk_max = fclk_min; 1010 socclk_max = socclk_min; 1011 vclk_max = vclk_min; 1012 dclk_max = dclk_min; 1013 break; 1014 case AMD_DPM_FORCED_LEVEL_AUTO: 1015 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); 1016 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max); 1017 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max); 1018 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max); 1019 smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); 1020 break; 1021 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1022 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1023 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1024 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1025 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max); 1026 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max); 1027 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max); 1028 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max); 1029 smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); 1030 break; 1031 case AMD_DPM_FORCED_LEVEL_MANUAL: 1032 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1033 return 0; 1034 default: 1035 dev_err(adev->dev, "Invalid performance level %d\n", level); 1036 return -EINVAL; 1037 } 1038 1039 if (sclk_min && sclk_max) { 1040 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 1041 SMU_SCLK, 1042 sclk_min, 1043 sclk_max); 1044 if (ret) 1045 return ret; 1046 1047 smu->gfx_actual_hard_min_freq = sclk_min; 1048 smu->gfx_actual_soft_max_freq = sclk_max; 1049 } 1050 1051 if (fclk_min && fclk_max) { 1052 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 1053 SMU_FCLK, 1054 fclk_min, 1055 fclk_max); 1056 if (ret) 1057 return ret; 1058 } 1059 1060 if (socclk_min && socclk_max) { 1061 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 1062 SMU_SOCCLK, 1063 socclk_min, 1064 socclk_max); 1065 if (ret) 1066 return ret; 1067 } 1068 1069 if (vclk_min && vclk_max) { 1070 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 1071 SMU_VCLK, 1072 vclk_min, 1073 vclk_max); 1074 if (ret) 1075 return ret; 1076 } 1077 1078 if (dclk_min && dclk_max) { 1079 ret = smu_v13_0_4_set_soft_freq_limited_range(smu, 1080 SMU_DCLK, 1081 dclk_min, 1082 dclk_max); 1083 if (ret) 1084 return ret; 1085 } 1086 return ret; 1087} 1088 1089static int smu_v13_0_4_mode2_reset(struct smu_context *smu) 1090{ 1091 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, 1092 SMU_RESET_MODE_2, NULL); 1093} 1094 1095static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) 1096{ 1097 DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1098 1099 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; 1100 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; 1101 smu->gfx_actual_hard_min_freq = 0; 1102 smu->gfx_actual_soft_max_freq = 0; 1103 1104 return 0; 1105} 1106 1107static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { 1108 .check_fw_status = smu_v13_0_check_fw_status, 1109 .check_fw_version = smu_v13_0_check_fw_version, 1110 .init_smc_tables = smu_v13_0_4_init_smc_tables, 1111 .fini_smc_tables = smu_v13_0_4_fini_smc_tables, 1112 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, 1113 .system_features_control = smu_v13_0_4_system_features_control, 1114 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, 1115 .send_smc_msg = smu_cmn_send_smc_msg, 1116 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, 1117 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, 1118 .set_default_dpm_table = smu_v13_0_set_default_dpm_tables, 1119 .read_sensor = smu_v13_0_4_read_sensor, 1120 .is_dpm_running = smu_v13_0_4_is_dpm_running, 1121 .set_watermarks_table = smu_v13_0_4_set_watermarks_table, 1122 .get_gpu_metrics = smu_v13_0_4_get_gpu_metrics, 1123 .get_enabled_mask = smu_cmn_get_enabled_mask, 1124 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, 1125 .set_driver_table_location = smu_v13_0_set_driver_table_location, 1126 .gfx_off_control = smu_v13_0_gfx_off_control, 1127 .mode2_reset = smu_v13_0_4_mode2_reset, 1128 .get_dpm_ultimate_freq = smu_v13_0_4_get_dpm_ultimate_freq, 1129 .od_edit_dpm_table = smu_v13_0_od_edit_dpm_table, 1130 .print_clk_levels = smu_v13_0_4_print_clk_levels, 1131 .force_clk_levels = smu_v13_0_4_force_clk_levels, 1132 .set_performance_level = smu_v13_0_4_set_performance_level, 1133 .set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters, 1134 .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, 1135}; 1136 1137static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu) 1138{ 1139 struct amdgpu_device *adev = smu->adev; 1140 1141 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); 1142 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); 1143 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 1144} 1145 1146void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) 1147{ 1148 struct amdgpu_device *adev = smu->adev; 1149 1150 smu->ppt_funcs = &smu_v13_0_4_ppt_funcs; 1151 smu->message_map = smu_v13_0_4_message_map; 1152 smu->feature_map = smu_v13_0_4_feature_mask_map; 1153 smu->table_map = smu_v13_0_4_table_map; 1154 smu->smc_driver_if_version = SMU13_0_4_DRIVER_IF_VERSION; 1155 smu->is_apu = true; 1156 1157 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 4)) 1158 smu_v13_0_4_set_smu_mailbox_registers(smu); 1159 else 1160 smu_v13_0_set_smu_mailbox_registers(smu); 1161} 1162