Searched refs:reg_val (Results 1 - 25 of 396) sorted by relevance

1234567891011>>

/linux-master/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.c23 u32 reg_val; local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);
26 reg_val &= ETS_RST;
31 reg_val &= ETS_WRR;
34 reg_val |= ETS_WFQ;
37 reg_val |= ETS_DWRR;
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
44 reg_val &= RAA_SP;
47 reg_val |= RAA_WSP;
50 writel(reg_val, ioadd
64 u32 fifo_bits, reg_val; local
76 u32 fifo_bits, reg_val; local
87 u32 reg_val; local
96 u32 reg_val; local
106 u32 reg_val; local
117 u32 reg_val; local
127 u32 reg_val; local
138 u32 reg_val; local
148 u32 reg_val; local
158 u32 reg_val; local
168 u32 reg_val; local
180 u32 reg_val; local
211 u32 reg_val; local
[all...]
/linux-master/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h83 __be64 reg_val; member in struct:hdat_fadump_reg_entry
88 u64 reg_val)
92 regs->gpr[reg_num] = reg_val;
98 regs->ctr = reg_val;
101 regs->link = reg_val;
104 regs->xer = reg_val;
107 regs->dar = reg_val;
110 regs->dsisr = reg_val;
113 regs->nip = reg_val;
116 regs->msr = reg_val;
86 opal_fadump_set_regval_regnum(struct pt_regs *regs, u32 reg_type, u32 reg_num, u64 reg_val) argument
[all...]
/linux-master/drivers/input/keyboard/
H A Dimx_keypad.c83 unsigned short reg_val; local
94 reg_val = readw(keypad->mmio_base + KPDR);
95 reg_val |= 0xff00;
96 writew(reg_val, keypad->mmio_base + KPDR);
98 reg_val = readw(keypad->mmio_base + KPCR);
99 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8);
100 writew(reg_val, keypad->mmio_base + KPCR);
104 reg_val = readw(keypad->mmio_base + KPCR);
105 reg_val |= (keypad->cols_en_mask & 0xff) << 8;
106 writew(reg_val, keypa
188 unsigned short reg_val; local
291 unsigned short reg_val; local
315 unsigned short reg_val; local
351 unsigned short reg_val; local
522 unsigned short reg_val = readw(kbd->mmio_base + KPSR); local
[all...]
/linux-master/arch/mips/pci/
H A Dfixup-malta.c70 unsigned char reg_val; local
84 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, &reg_val);
85 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
88 pci_irq[PCIA+i] = piixirqmap[reg_val &
98 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, &reg_val);
99 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
109 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
110 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
111 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
124 unsigned char reg_val; local
[all...]
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c63 u32 reg_val; local
81 reg_val = DPU_REG_READ(c, reg_off);
82 reg_val &= ~(0x7 << bit_off);
83 reg_val |= (value & 0x7) << bit_off;
84 DPU_REG_WRITE(c, reg_off, reg_val);
91 u32 reg_val; local
102 reg_val = DPU_REG_READ(c, reg_off);
103 reg_val &= ~(0xFF << bit_off);
104 reg_val |= (limit) << bit_off;
105 DPU_REG_WRITE(c, reg_off, reg_val);
112 u32 reg_val; local
134 u32 reg_val; local
150 u32 reg_val; local
161 u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift; local
190 u32 reg_val; local
[all...]
/linux-master/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cnxk.c141 u64 reg_val; local
143 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(0));
144 conf->ring_cfg.max_io_rings = (reg_val >> CNXK_VF_R_IN_CTL_RPVF_POS) &
168 u64 reg_val; local
170 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));
173 if (!(reg_val & CNXK_VF_R_IN_CTL_IDLE)) {
175 reg_val = octep_vf_read_csr64(oct, CNXK_VF_SDP_R_IN_CONTROL(iq_no));
176 } while (!(reg_val & CNXK_VF_R_IN_CTL_IDLE));
178 reg_val |= CNXK_VF_R_IN_CTL_RDSIZE;
179 reg_val |
207 u64 reg_val; local
285 u64 reg_val; local
323 u64 reg_val; local
344 u64 reg_val; local
380 u64 reg_val; local
401 u64 reg_val; local
428 u64 reg_val; local
438 u64 reg_val; local
[all...]
H A Doctep_vf_cn9k.c139 u64 reg_val; local
141 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(0));
142 conf->ring_cfg.max_io_rings = (reg_val >> CN93_VF_R_IN_CTL_RPVF_POS) &
165 u64 reg_val; local
167 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no));
170 if (!(reg_val & CN93_VF_R_IN_CTL_IDLE)) {
172 reg_val = octep_vf_read_csr64(oct, CN93_VF_SDP_R_IN_CONTROL(iq_no));
173 } while (!(reg_val & CN93_VF_R_IN_CTL_IDLE));
175 reg_val |= CN93_VF_R_IN_CTL_RDSIZE;
176 reg_val |
204 u64 reg_val; local
274 u64 reg_val; local
312 u64 reg_val; local
333 u64 reg_val; local
369 u64 reg_val; local
390 u64 reg_val; local
417 u64 reg_val; local
427 u64 reg_val; local
[all...]
/linux-master/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_cnxk_pf.c287 u64 reg_val; local
290 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));
293 if (!(reg_val & CNXK_R_IN_CTL_IDLE)) {
295 reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no));
296 } while (!(reg_val & CNXK_R_IN_CTL_IDLE));
299 reg_val |= CNXK_R_IN_CTL_RDSIZE;
300 reg_val |= CNXK_R_IN_CTL_IS_64B;
301 reg_val |= CNXK_R_IN_CTL_ESR;
302 octep_write_csr64(oct, CNXK_SDP_R_IN_CONTROL(iq_no), reg_val);
325 reg_val
332 u64 reg_val; local
475 u64 reg_val = 0; local
505 u64 reg_val = 0; local
533 u64 reg_val = 0; local
550 u64 reg_val = 0; local
566 u64 reg_val = 0; local
581 u64 reg_val = 0; local
598 u64 reg_val = 0; local
615 u64 reg_val = 0; local
765 u64 reg_val; local
788 u64 reg_val = 0ULL; local
817 u64 reg_val = 0ULL; local
829 u64 reg_val = 0ULL; local
[all...]
H A Doctep_cn9k_pf.c267 u64 reg_val; local
270 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
273 if (!(reg_val & CN93_R_IN_CTL_IDLE)) {
275 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
276 } while (!(reg_val & CN93_R_IN_CTL_IDLE));
279 reg_val |= CN93_R_IN_CTL_RDSIZE;
280 reg_val |= CN93_R_IN_CTL_IS_64B;
281 reg_val |= CN93_R_IN_CTL_ESR;
282 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val);
305 reg_val
312 u64 reg_val; local
454 u64 reg_val = 0; local
484 u64 reg_val = 0; local
512 u64 reg_val = 0; local
529 u64 reg_val = 0; local
545 u64 reg_val = 0; local
560 u64 reg_val = 0; local
577 u64 reg_val = 0; local
594 u64 reg_val = 0; local
742 u64 reg_val; local
765 u64 reg_val = 0ULL; local
794 u64 reg_val = 0ULL; local
806 u64 reg_val = 0ULL; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.c76 uint32_t reg_val; local
84 reg_val = srv->funcs.reg_read(srv->user_ctx, addr);
85 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
86 srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
89 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, argument
100 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
101 srv->funcs.reg_write(srv->user_ctx, addr, reg_val);
107 uint32_t reg_val local
[all...]
/linux-master/drivers/spi/
H A Dspi-mt65xx.c272 u32 reg_val; local
275 reg_val = readl(mdata->base + SPI_CMD_REG);
276 reg_val |= SPI_CMD_RST;
277 writel(reg_val, mdata->base + SPI_CMD_REG);
279 reg_val = readl(mdata->base + SPI_CMD_REG);
280 reg_val &= ~SPI_CMD_RST;
281 writel(reg_val, mdata->base + SPI_CMD_REG);
291 u32 reg_val; local
310 reg_val = readl(mdata->base + SPI_CFG0_REG);
314 reg_val
355 u32 reg_val; local
464 u32 reg_val; local
485 u32 div, sck_time, reg_val; local
517 u32 packet_size, packet_loop, reg_val; local
629 u32 reg_val; local
704 u32 reg_val = 0; local
748 u32 cmd, reg_val, cnt, remainder, len; local
948 u32 reg_val, nio, tx_size; local
[all...]
H A Dspi-slave-mt27xx.c100 u32 reg_val; local
102 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG);
103 reg_val &= ~RX_DMA_EN;
104 reg_val &= ~TX_DMA_EN;
105 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG);
110 u32 reg_val; local
112 reg_val = readl(mdata->base + SPIS_CFG_REG);
113 reg_val &= ~SPIS_TX_EN;
114 reg_val &= ~SPIS_RX_EN;
115 writel(reg_val, mdat
135 u32 reg_val; local
167 int reg_val, cnt, remainder, ret; local
205 int reg_val, ret; local
301 u32 reg_val; local
332 u32 int_status, reg_val, cnt, remainder; local
[all...]
/linux-master/arch/arm/mach-qcom/
H A Dplatsmp.c84 u32 reg_val; local
103 reg_val = CORE_RST | COREPOR_RST | CLAMP | CORE_MEM_CLAMP;
104 writel(reg_val, reg + APCS_CPU_PWR_CTL);
111 reg_val &= ~CORE_MEM_CLAMP;
112 writel(reg_val, reg + APCS_CPU_PWR_CTL);
113 reg_val |= L2DT_SLP;
114 writel(reg_val, reg + APCS_CPU_PWR_CTL);
117 reg_val = (reg_val | BIT(17)) & ~CLAMP;
118 writel(reg_val, re
219 unsigned reg_val; local
[all...]
/linux-master/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c105 unsigned int reg_val; local
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
109 reg_val &= ~EMAC_MAC_SUPP_100M;
111 reg_val |= EMAC_MAC_SUPP_100M;
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
118 unsigned int reg_val; local
121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
125 writel(reg_val, d
250 u32 reg_val; local
364 unsigned int reg_val; local
407 unsigned int reg_val; local
427 unsigned int reg_val; local
495 unsigned int reg_val; local
623 unsigned int reg_val; local
764 unsigned int reg_val; local
857 unsigned int reg_val; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c149 uint32_t reg_val)
167 cmd_buf->write_values[offload->reg_seq_count] = reg_val;
232 uint32_t reg_val; local
248 reg_val = dm_read_reg(ctx, addr);
249 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
250 dm_write_reg(ctx, addr, reg_val);
251 return reg_val;
255 uint32_t addr, uint32_t reg_val, int n,
271 reg_val
148 dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val) argument
254 generic_reg_set_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument
286 uint32_t reg_val = dm_read_reg(ctx, addr); local
295 uint32_t reg_val = dm_read_reg(ctx, addr); local
306 uint32_t reg_val = dm_read_reg(ctx, addr); local
319 uint32_t reg_val = dm_read_reg(ctx, addr); local
334 uint32_t reg_val = dm_read_reg(ctx, addr); local
351 uint32_t reg_val = dm_read_reg(ctx, addr); local
370 uint32_t reg_val = dm_read_reg(ctx, addr); local
391 uint32_t reg_val = dm_read_reg(ctx, addr); local
439 uint32_t reg_val; local
542 generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument
573 generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) argument
[all...]
/linux-master/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c45 u32 reg_val; member in struct:hdmi_hdcp_reg_data
199 u32 reg_val, hdcp_int_status; local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL);
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK;
210 reg_val |= hdcp_int_status << 1;
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK;
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val);
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
230 __func__, reg_val);
284 u32 reg_val, failur local
402 u32 reg_val; local
459 u32 reg_val; local
540 u32 reg_val; local
558 u32 reg_val; local
1120 u32 reg_val, data, reg; local
1307 u32 reg_val; local
1333 u32 reg_val; local
[all...]
/linux-master/arch/riscv/kvm/
H A Dvcpu_onereg.c191 unsigned long reg_val; local
198 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
203 reg_val = riscv_cbom_block_size;
208 reg_val = riscv_cboz_block_size;
211 reg_val = vcpu->arch.mvendorid;
214 reg_val = vcpu->arch.marchid;
217 reg_val = vcpu->arch.mimpid;
220 reg_val = satp_mode >> SATP_MODE_SHIFT;
226 if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
240 unsigned long i, isa_ext, reg_val; local
345 unsigned long reg_val; local
378 unsigned long reg_val; local
423 kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
445 kvm_riscv_vcpu_smstateen_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
482 unsigned long reg_val, reg_subtype; local
524 unsigned long reg_val, reg_subtype; local
557 riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
578 riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
616 riscv_vcpu_get_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
639 riscv_vcpu_set_isa_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) argument
668 unsigned long reg_val, reg_subtype; local
707 unsigned long reg_val, reg_subtype; local
[all...]
H A Dvcpu_fp.c87 void *reg_val; local
94 reg_val = &cntx->fp.f.fcsr;
97 reg_val = &cntx->fp.f.f[reg_num];
105 reg_val = &cntx->fp.d.fcsr;
110 reg_val = &cntx->fp.d.f[reg_num];
116 if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id)))
132 void *reg_val; local
139 reg_val = &cntx->fp.f.fcsr;
142 reg_val = &cntx->fp.f.f[reg_num];
150 reg_val
[all...]
H A Dvcpu_sbi.c173 unsigned long reg_val)
178 if (reg_val != 1 && reg_val != 0)
185 scontext->ext_status[sext->ext_idx] = (reg_val) ?
194 unsigned long *reg_val)
203 *reg_val = scontext->ext_status[sext->ext_idx] ==
211 unsigned long reg_val, bool enable)
218 for_each_set_bit(i, &reg_val, BITS_PER_LONG) {
231 unsigned long *reg_val)
246 *reg_val |
171 riscv_vcpu_set_sbi_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) argument
192 riscv_vcpu_get_sbi_ext_single(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
209 riscv_vcpu_set_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val, bool enable) argument
229 riscv_vcpu_get_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long *reg_val) argument
260 unsigned long reg_val, reg_subtype; local
297 unsigned long reg_val, reg_subtype; local
336 unsigned long reg_subtype, reg_val; local
365 unsigned long reg_subtype, reg_val; local
[all...]
/linux-master/sound/drivers/opl3/
H A Dopl3_synth.c396 unsigned char reg_val; local
416 reg_val = (unsigned char) note->fnum;
418 opl3->command(opl3, opl3_reg, reg_val);
420 reg_val = 0x00;
423 reg_val |= OPL3_KEYON_BIT;
425 reg_val |= (note->octave << 2) & OPL3_BLOCKNUM_MASK;
427 reg_val |= (unsigned char) (note->fnum >> 8) & OPL3_FNUM_HIGH_MASK;
431 opl3->command(opl3, opl3_reg, reg_val);
444 unsigned char reg_val; local
470 reg_val
543 unsigned char reg_val; local
595 unsigned char reg_val; local
[all...]
/linux-master/drivers/ata/
H A Dahci_sunxi.c55 u32 reg_val; local
57 reg_val = readl(reg);
58 reg_val &= ~(clr_val);
59 writel(reg_val, reg);
64 u32 reg_val; local
66 reg_val = readl(reg);
67 reg_val |= set_val;
68 writel(reg_val, reg);
73 u32 reg_val; local
75 reg_val
88 u32 reg_val; local
[all...]
/linux-master/sound/soc/amd/vangogh/
H A Dacp5x-i2s.c93 u32 reg_val, frmt_reg; local
131 reg_val = ACP_HSTDM_ITER;
136 reg_val = ACP_I2STDM_ITER;
142 reg_val = ACP_HSTDM_IRER;
147 reg_val = ACP_I2STDM_IRER;
152 val = acp_readl(rtd->acp5x_base + reg_val);
153 acp_writel(val | 0x2, rtd->acp5x_base + reg_val);
156 val = acp_readl(rtd->acp5x_base + reg_val);
159 acp_writel(val, rtd->acp5x_base + reg_val);
237 u32 ret, val, period_bytes, reg_val, ier_va local
[all...]
/linux-master/sound/soc/amd/raven/
H A Dacp3x-i2s.c81 u32 reg_val, frmt_reg; local
116 reg_val = mmACP_BTTDM_ITER;
121 reg_val = mmACP_I2STDM_ITER;
127 reg_val = mmACP_BTTDM_IRER;
132 reg_val = mmACP_I2STDM_IRER;
137 val = rv_readl(rtd->acp3x_base + reg_val);
138 rv_writel(val | 0x2, rtd->acp3x_base + reg_val);
141 val = rv_readl(rtd->acp3x_base + reg_val);
144 rv_writel(val, rtd->acp3x_base + reg_val);
152 u32 ret, val, period_bytes, reg_val, ier_va local
[all...]
/linux-master/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_vf_device.c68 u64 reg_val = octeon_read_csr64(oct, local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
73 WRITE_ONCE(reg_val, octeon_read_csr64(
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
86 READ_ONCE(reg_val));
88 WRITE_ONCE(reg_val, octeon_read_csr64(
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
153 u32 reg_val; local
321 u64 reg_val; local
342 u32 reg_val; local
620 u64 reg_val; local
[all...]
/linux-master/drivers/gpu/drm/xe/tests/
H A Dxe_mocs.c43 u32 reg_val; local
58 reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i));
60 reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i));
62 XELP_LNCFCMOCS(i).addr, reg_val, l3cc);
63 if (reg_val != l3cc)
78 u32 reg_val; local
93 reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
95 reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));
97 XELP_GLOBAL_MOCS(i).addr, reg_val, mocs);
98 if (reg_val !
[all...]

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