Lines Matching refs:reg_val
63 u32 reg_val;
81 reg_val = DPU_REG_READ(c, reg_off);
82 reg_val &= ~(0x7 << bit_off);
83 reg_val |= (value & 0x7) << bit_off;
84 DPU_REG_WRITE(c, reg_off, reg_val);
91 u32 reg_val;
102 reg_val = DPU_REG_READ(c, reg_off);
103 reg_val &= ~(0xFF << bit_off);
104 reg_val |= (limit) << bit_off;
105 DPU_REG_WRITE(c, reg_off, reg_val);
112 u32 reg_val;
124 reg_val = DPU_REG_READ(c, reg_off);
125 limit = (reg_val >> bit_off) & 0xFF;
134 u32 reg_val;
136 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL0);
139 reg_val |= BIT(xin_id);
141 reg_val &= ~BIT(xin_id);
143 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val);
150 u32 reg_val;
152 reg_val = DPU_REG_READ(c, VBIF_XIN_HALT_CTRL1);
154 return (reg_val & BIT(xin_id)) ? true : false;
161 u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift;
172 reg_val = DPU_REG_READ(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high);
177 reg_val &= ~mask;
178 reg_val |= (remap_level << reg_shift) & mask;
183 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val);
190 u32 reg_val;
197 reg_val = DPU_REG_READ(c, VBIF_WRITE_GATHER_EN);
198 reg_val |= BIT(xin_id);
199 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val);