marvell/octeon_ep/octep_cn9k_pf.c

267 	u64 reg_val;
270 	reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
273 	if (!(reg_val & CN93_R_IN_CTL_IDLE)) {
275 			reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
276 		} while (!(reg_val & CN93_R_IN_CTL_IDLE));
279 	reg_val |= CN93_R_IN_CTL_RDSIZE;
280 	reg_val |= CN93_R_IN_CTL_IS_64B;
281 	reg_val |= CN93_R_IN_CTL_ESR;
282 	octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val);
305 	reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff;
306 	octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val);
312 	u64 reg_val;
318 	reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));
321 	if (!(reg_val & CN93_R_OUT_CTL_IDLE)) {
323 			reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));
324 		} while (!(reg_val & CN93_R_OUT_CTL_IDLE));
327 	reg_val &= ~(CN93_R_OUT_CTL_IMODE);
328 	reg_val &= ~(CN93_R_OUT_CTL_ROR_P);
329 	reg_val &= ~(CN93_R_OUT_CTL_NSR_P);
330 	reg_val &= ~(CN93_R_OUT_CTL_ROR_I);
331 	reg_val &= ~(CN93_R_OUT_CTL_NSR_I);
332 	reg_val &= ~(CN93_R_OUT_CTL_ES_I);
333 	reg_val &= ~(CN93_R_OUT_CTL_ROR_D);
334 	reg_val &= ~(CN93_R_OUT_CTL_NSR_D);
335 	reg_val &= ~(CN93_R_OUT_CTL_ES_D);
336 	reg_val |= (CN93_R_OUT_CTL_ES_P);
338 	octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), reg_val);
355 	reg_val = ((u64)time_threshold << 32) |
357 	octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);
454 	u64 reg_val = 0;
458 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_IRERR_RINT);
459 	if (reg_val) {
461 			 "received IRERR_RINT intr: 0x%llx\n", reg_val);
462 		octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT, reg_val);
465 			reg_val = octep_read_csr64(oct,
467 			if (reg_val) {
470 					 i, reg_val);
472 						  reg_val);
484 	u64 reg_val = 0;
488 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_ORERR_RINT);
489 	if (reg_val) {
491 			 "Received ORERR_RINT intr: 0x%llx\n", reg_val);
492 		octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT, reg_val);
494 			reg_val = octep_read_csr64(oct, CN93_SDP_R_ERR_TYPE(i));
495 			if (reg_val) {
498 					 i, reg_val);
500 						  reg_val);
512 	u64 reg_val = 0;
515 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0));
516 	if (reg_val) {
518 			 "Received VFIRE_RINT intr: 0x%llx\n", reg_val);
519 		octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0), reg_val);
529 	u64 reg_val = 0;
532 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0));
533 	if (reg_val) {
535 			 "Received VFORE_RINT intr: 0x%llx\n", reg_val);
536 		octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0), reg_val);
545 	u64 reg_val = 0;
548 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT);
549 	if (reg_val) {
550 		octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT, reg_val);
560 	u64 reg_val = 0;
563 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0));
564 	if (reg_val) {
566 			 "Received DMA_VF_RINT intr: 0x%llx\n", reg_val);
567 		octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0), reg_val);
577 	u64 reg_val = 0;
580 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0));
581 	if (reg_val) {
583 			 "Received PP_VF_RINT intr: 0x%llx\n", reg_val);
584 		octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0), reg_val);
594 	u64 reg_val = 0;
597 	reg_val = octep_read_csr64(oct, CN93_SDP_EPF_MISC_RINT);
598 	if (reg_val) {
600 			 "Received MISC_RINT intr: 0x%llx\n", reg_val);
601 		octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT, reg_val);
742 	u64 reg_val;
753 	reg_val = octep_read_csr64(oct,  CN93_SDP_R_IN_INT_LEVELS(iq_no));
754 	reg_val |= (0x1ULL << 62);
755 	octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val);
757 	reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no));
758 	reg_val |= 0x1ULL;
759 	octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val);
765 	u64 reg_val = 0ULL;
769 	reg_val = octep_read_csr64(oct,  CN93_SDP_R_OUT_INT_LEVELS(oq_no));
770 	reg_val |= (0x1ULL << 62);
771 	octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);
775 	reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no));
776 	reg_val |= 0x1ULL;
777 	octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val);
794 	u64 reg_val = 0ULL;
798 	reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no));
799 	reg_val &= ~0x1ULL;
800 	octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val);
806 	u64 reg_val = 0ULL;
809 	reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no));
810 	reg_val &= ~0x1ULL;
811 	octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val);