samsung/sxgbe/sxgbe_mtl.c

23 	u32 reg_val;
25 	reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);
26 	reg_val &= ETS_RST;
31 		reg_val &= ETS_WRR;
34 		reg_val |= ETS_WFQ;
37 		reg_val |= ETS_DWRR;
40 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
44 		reg_val &= RAA_SP;
47 		reg_val |= RAA_WSP;
50 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
64 	u32 fifo_bits, reg_val;
68 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
69 	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);
70 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
76 	u32 fifo_bits, reg_val;
80 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
81 	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);
82 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
87 	u32 reg_val;
89 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
90 	reg_val |= SXGBE_MTL_ENABLE_QUEUE;
91 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
96 	u32 reg_val;
98 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
99 	reg_val &= ~SXGBE_MTL_ENABLE_QUEUE;
100 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
106 	u32 reg_val;
108 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
109 	reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_ACTIVE);
110 	reg_val |= (threshold << RX_FC_ACTIVE);
112 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
117 	u32 reg_val;
119 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
120 	reg_val |= SXGBE_MTL_ENABLE_FC;
121 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
127 	u32 reg_val;
129 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
130 	reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_DEACTIVE);
131 	reg_val |= (threshold << RX_FC_DEACTIVE);
133 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
138 	u32 reg_val;
140 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
141 	reg_val |= SXGBE_MTL_RXQ_OP_FEP;
143 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
148 	u32 reg_val;
150 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
151 	reg_val &= ~(SXGBE_MTL_RXQ_OP_FEP);
153 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
158 	u32 reg_val;
160 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
161 	reg_val |= SXGBE_MTL_RXQ_OP_FUP;
163 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
168 	u32 reg_val;
170 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
171 	reg_val &= ~(SXGBE_MTL_RXQ_OP_FUP);
173 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
180 	u32 reg_val;
182 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
185 		reg_val |= SXGBE_MTL_SFMODE;
189 			reg_val |= MTL_CONTROL_TTC_64;
191 			reg_val |= MTL_CONTROL_TTC_96;
193 			reg_val |= MTL_CONTROL_TTC_128;
195 			reg_val |= MTL_CONTROL_TTC_192;
197 			reg_val |= MTL_CONTROL_TTC_256;
199 			reg_val |= MTL_CONTROL_TTC_384;
201 			reg_val |= MTL_CONTROL_TTC_512;
205 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
211 	u32 reg_val;
213 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
216 		reg_val |= SXGBE_RX_MTL_SFMODE;
219 			reg_val |= MTL_CONTROL_RTC_64;
221 			reg_val |= MTL_CONTROL_RTC_96;
223 			reg_val |= MTL_CONTROL_RTC_128;
227 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));