cavium/liquidio/cn23xx_vf_device.c

68 		u64 reg_val = octeon_read_csr64(oct,
70 		while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
71 		       !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
73 			WRITE_ONCE(reg_val, octeon_read_csr64(
83 		WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
86 				   READ_ONCE(reg_val));
88 		WRITE_ONCE(reg_val, octeon_read_csr64(
90 		if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
153 	u32 reg_val;
160 		reg_val =
163 		reg_val &= 0xEFFFFFFFFFFFFFFFL;
165 		reg_val =
169 		reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR;
172 		reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;
175 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
180 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
181 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
184 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
186 		reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
191 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
192 		reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
194 		reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
198 				 reg_val);
321 		u64 reg_val;
325 			reg_val = octeon_read_csr64(
327 			reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B;
329 			    oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
334 			reg_val = octeon_read_csr64(
336 			reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB;
338 			    oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
342 		u32 reg_val;
346 			reg_val = octeon_read_csr(
348 			reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB;
350 			    oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val);
620 	u64 reg_val;
626 	reg_val = octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(0));
628 	oct->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
630 	oct->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) &
633 	reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS;
635 	rings_per_vf = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK;