msm/hdmi/hdmi_hdcp.c

45 	u32 reg_val;
199 	u32 reg_val, hdcp_int_status;
203 	reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL);
204 	hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK;
210 	reg_val |= hdcp_int_status << 1;
213 		reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK;
214 	hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val);
228 		reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS);
230 			__func__, reg_val);
284 	u32 reg_val, failure, nack0;
288 	reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);
289 	failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED;
290 	nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0;
292 		reg_val, failure, nack0);
309 		reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1);
310 		reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK;
311 		hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val);
314 		reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS);
315 		if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED)
327 		reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
328 		reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET;
329 		hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
333 		reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
334 		reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET;
335 		hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
338 		reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
339 		reg_val |= HDMI_DDC_CTRL_SOFT_RESET;
340 		hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
346 		reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL);
347 		reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET;
348 		hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val);
402 	u32 reg_val;
412 	reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
413 	reg_val &= ~HDMI_HPD_CTRL_ENABLE;
414 	hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
434 	reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
435 	reg_val |= HDMI_HPD_CTRL_ENABLE;
436 	hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
459 	u32 reg_val;
475 	reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
476 	reg_val &= ~HDMI_CTRL_ENCRYPTED;
477 	hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
480 	reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION);
481 	reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION;
482 	hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val);
501 	reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL);
502 	reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER;
503 	hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val);
540 	u32 reg_val;
546 	reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
547 	reg_val &= ~HDMI_CTRL_ENCRYPTED;
548 	hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
558 	u32 reg_val;
566 	reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION);
567 	reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION;
568 	hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val);
573 	reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
574 	reg_val |= HDMI_CTRL_ENCRYPTED;
575 	hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
1120 	u32 reg_val, data, reg;
1127 		reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS);
1128 		DBG("HDCP_SHA_STATUS=%08x", reg_val);
1131 			if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) {
1139 			if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE))
1157 		reg_val = ksv_fifo[i] << 16;
1159 			reg_val |= HDMI_HDCP_SHA_DATA_DONE;
1162 		data = reg_val;
1307 	u32 reg_val;
1318 	reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
1319 	reg_val &= ~HDMI_CTRL_ENCRYPTED;
1320 	hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
1333 	u32 reg_val;
1348 	reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
1349 	reg_val &= ~HDMI_HPD_CTRL_ENABLE;
1350 	hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);
1378 	reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
1379 	reg_val &= ~HDMI_CTRL_ENCRYPTED;
1380 	hdmi_write(hdmi, REG_HDMI_CTRL, reg_val);
1383 	reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL);
1384 	reg_val |= HDMI_HPD_CTRL_ENABLE;
1385 	hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val);