/linux-master/drivers/scsi/mvsas/ |
H A D | mv_sas.h | 64 #define SATA_RECEIVED_FIS_LIST(reg_set) \ 65 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 66 #define SATA_RECEIVED_SDB_FIS(reg_set) \ 67 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 68 #define SATA_RECEIVED_D2H_FIS(reg_set) \ 69 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 70 #define SATA_RECEIVED_PIO_FIS(reg_set) \ 71 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 72 #define SATA_RECEIVED_DMA_FIS(reg_set) \ 73 (SATA_RECEIVED_FIS_LIST(reg_set) [all...] |
H A D | mv_94xx.c | 667 mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) argument 684 if (reg_set > 31) 689 if (tmp & (1 << (reg_set % 32))) { 690 mv_dprintk("register set 0x%x was stopped.\n", reg_set); 691 if (reg_set > 31) 692 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32)); 694 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); 744 u8 reg_set = *tfs; local 749 mvi->sata_reg_set &= ~bit(reg_set); 750 if (reg_set < 3 [all...] |
H A D | mv_64xx.c | 124 mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) argument 136 if (tmp & (1 << (reg_set % 32))) { 138 reg_set); 139 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
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/linux-master/drivers/gpio/ |
H A D | gpio-mmio.c | 137 return !!(gc->read_reg(gc->reg_set) & pinmask); 159 *bits |= gc->read_reg(gc->reg_set) & set_mask; 240 gc->write_reg(gc->reg_set, mask); 257 gc->write_reg(gc->reg_set, gc->bgpio_data); 309 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 321 gc->write_reg(gc->reg_set, set_mask); 499 gc->reg_set = set; 504 gc->reg_set = set; 640 gc->bgpio_data = gc->read_reg(gc->reg_set);
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/linux-master/drivers/media/i2c/ |
H A D | rj54n1cb0c.c | 464 static int reg_set(struct i2c_client *client, const u16 reg, function 506 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80); 895 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1); 1033 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); 1038 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); 1043 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); 1048 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); 1053 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); 1060 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); 1067 ret = reg_set(clien [all...] |
H A D | ak881x.c | 46 static int reg_set(struct i2c_client *client, const u8 reg, function 172 reg_set(client, AK881X_VIDEO_PROCESS1, vp1, 0xf);
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H A D | mt9m111.c | 140 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) macro 438 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 440 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); 828 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); 837 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); 917 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); 919 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
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H A D | mt9m001.c | 125 static int reg_set(struct i2c_client *client, const u8 reg, function 514 ret = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000);
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/linux-master/drivers/leds/ |
H A D | leds-tca6507.c | 154 int reg_set; /* One bit per register where member in struct:tca6507_chip 269 tca->reg_set |= (1 << bit); 290 tca->reg_set |= 1 << reg; 351 set = tca->reg_set; 353 tca->reg_set = 0; 537 if (tca->reg_set) 605 if (tca->reg_set) 765 tca->reg_set = 0x7f;
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/linux-master/drivers/scsi/megaraid/ |
H A D | megaraid_sas_base.c | 230 struct megasas_register_set __iomem *reg_set); 308 cmd->frame_phys_addr, 0, instance->reg_set); 463 regs = instance->reg_set; 480 regs = instance->reg_set; 493 return readl(&instance->reg_set->outbound_msg_0); 505 regs = instance->reg_set; 643 regs = instance->reg_set; 662 regs = instance->reg_set; 675 return readl(&instance->reg_set->outbound_scratch_pad_0); 687 regs = instance->reg_set; 1018 megasas_adp_reset_gen2(struct megasas_instance *instance, struct megasas_register_set __iomem *reg_set) argument 2984 megasas_dump_reg_set(void __iomem *reg_set) argument 3039 megasas_dump_sys_regs(void __iomem *reg_set, char *buf) argument [all...] |
H A D | megaraid_sas_fusion.c | 107 (instance, instance->reg_set)) 168 regs = instance->reg_set; 191 regs = instance->reg_set; 205 regs = instance->reg_set; 299 writeq(req_data, &instance->reg_set->inbound_low_queue_port); 304 &instance->reg_set->inbound_low_queue_port); 306 &instance->reg_set->inbound_high_queue_port); 325 &instance->reg_set->inbound_single_queue_port); 351 &instance->reg_set->outbound_scratch_pad_2) & 0x00FFFF; 1107 (instance, &instance->reg_set [all...] |
/linux-master/drivers/media/platform/st/stm32/stm32-dcmipp/ |
H A D | dcmipp-common.h | 167 #define reg_set(device, reg, mask) \ macro
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H A D | dcmipp-bytecap.c | 378 reg_set(vcap, DCMIPP_P0FCTCR, DCMIPP_P0FCTCR_CPTREQ); 424 reg_set(vcap, DCMIPP_P0FSCR, DCMIPP_P0FSCR_PIPEN); 438 reg_set(vcap, DCMIPP_CMIER, vcap->cmier);
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H A D | dcmipp-parallel.c | 351 reg_set(par, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
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/linux-master/drivers/media/pci/mgb4/ |
H A D | mgb4_cmt.c | 196 const u16 *reg_set; local 203 reg_set = cmt_vals_out[index]; 210 mgb4_write_reg(&voutdev->mgbdev->cmt, addr[i], reg_set[i]); 225 const u16 *reg_set; local 231 reg_set = cmt_vals_in[freq_range]; 238 mgb4_write_reg(&vindev->mgbdev->cmt, addr[i], reg_set[i]);
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/linux-master/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mtk-common.c | 244 unsigned int reg_pupd, reg_set, reg_rst; local 263 reg_set = spec_pupd_pin->offset + devdata->port_align; 269 reg_pupd = reg_set; 283 regmap_write(regmap, reg_set, bit_r0); 288 regmap_write(regmap, reg_set, bit_r1); 291 regmap_write(regmap, reg_set, bit_r0); 292 regmap_write(regmap, reg_set, bit_r1);
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/linux-master/drivers/gpu/drm/i2c/ |
H A D | tda998x_drv.c | 689 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) function 718 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 845 reg_set(priv, REG_DIP_IF_FLAGS, bit); 996 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 998 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1043 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1303 reg_set(priv, REG_TX4, TX4_PD_RAM); 1547 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1557 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); 1590 reg_set(pri [all...] |
/linux-master/drivers/pci/controller/ |
H A D | pci-xgene-msi.c | 144 u32 reg_set = hwirq_to_reg_set(data->hwirq); local 146 u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16);
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/linux-master/drivers/i3c/master/mipi-i3c-hci/ |
H A D | core.c | 32 #define reg_set(r, v) reg_write(r, reg_read(r) | (v)) macro 155 reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE); 177 reg_set(HC_CONTROL, HC_CONTROL_RESUME); 762 reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE);
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/linux-master/arch/arm/net/ |
H A D | bpf_jit_32.c | 1487 u16 reg_set = 0; local 1491 reg_set = (1 << rt[1]) | (1 << rt[0]); 1492 emit(ARM_PUSH(reg_set), ctx); 1504 u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC; local 1506 emit(ARM_PUSH(reg_set), ctx); 1541 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP; local 1542 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx); 1543 emit(ARM_LDM(ARM_SP, reg_set), ctx);
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/linux-master/drivers/media/platform/st/stm32/ |
H A D | stm32-dcmi.c | 189 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) function 372 reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE); 396 reg_set(dcmi->regs, DCMI_CR, CR_CROP); 479 reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR); 778 reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */ 781 reg_set(dcmi->regs, DCMI_CR, CR_ENABLE); 816 reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); 818 reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR);
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/linux-master/drivers/gpu/drm/i915/ |
H A D | intel_uncore.c | 124 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) 125 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) 2208 i915_reg_t reg_set, 2223 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); 2228 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset; 2206 __fw_domain_init(struct intel_uncore *uncore, enum forcewake_domain_id domain_id, i915_reg_t reg_set, i915_reg_t reg_ack) argument
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H A D | intel_uncore.h | 186 u32 __iomem *reg_set; member in struct:intel_uncore::intel_uncore_forcewake_domain
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/linux-master/include/linux/gpio/ |
H A D | driver.h | 393 * @reg_set: output set register (out=high) for generic GPIO 478 void __iomem *reg_set; member in struct:gpio_chip 716 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 719 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
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/linux-master/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_link.c | 3634 static struct bnx2x_reg_set reg_set[] = { local 3658 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3659 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3660 reg_set[i].val); 3673 static struct bnx2x_reg_set reg_set[] = { local 3693 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3694 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, 3695 reg_set[ 3735 static struct bnx2x_reg_set reg_set[] = { local 3887 static struct bnx2x_reg_set reg_set[] = { local 9649 static struct bnx2x_reg_set reg_set[] = { local 9717 static struct bnx2x_reg_set reg_set[] = { local [all...] |