1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __LINUX_GPIO_DRIVER_H 3#define __LINUX_GPIO_DRIVER_H 4 5#include <linux/bits.h> 6#include <linux/cleanup.h> 7#include <linux/err.h> 8#include <linux/irqchip/chained_irq.h> 9#include <linux/irqdomain.h> 10#include <linux/irqhandler.h> 11#include <linux/lockdep.h> 12#include <linux/pinctrl/pinconf-generic.h> 13#include <linux/pinctrl/pinctrl.h> 14#include <linux/property.h> 15#include <linux/spinlock_types.h> 16#include <linux/types.h> 17 18#ifdef CONFIG_GENERIC_MSI_IRQ 19#include <asm/msi.h> 20#endif 21 22struct device; 23struct irq_chip; 24struct irq_data; 25struct module; 26struct of_phandle_args; 27struct pinctrl_dev; 28struct seq_file; 29 30struct gpio_chip; 31struct gpio_desc; 32struct gpio_device; 33 34enum gpio_lookup_flags; 35enum gpiod_flags; 36 37union gpio_irq_fwspec { 38 struct irq_fwspec fwspec; 39#ifdef CONFIG_GENERIC_MSI_IRQ 40 msi_alloc_info_t msiinfo; 41#endif 42}; 43 44#define GPIO_LINE_DIRECTION_IN 1 45#define GPIO_LINE_DIRECTION_OUT 0 46 47/** 48 * struct gpio_irq_chip - GPIO interrupt controller 49 */ 50struct gpio_irq_chip { 51 /** 52 * @chip: 53 * 54 * GPIO IRQ chip implementation, provided by GPIO driver. 55 */ 56 struct irq_chip *chip; 57 58 /** 59 * @domain: 60 * 61 * Interrupt translation domain; responsible for mapping between GPIO 62 * hwirq number and Linux IRQ number. 63 */ 64 struct irq_domain *domain; 65 66#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 67 /** 68 * @fwnode: 69 * 70 * Firmware node corresponding to this gpiochip/irqchip, necessary 71 * for hierarchical irqdomain support. 72 */ 73 struct fwnode_handle *fwnode; 74 75 /** 76 * @parent_domain: 77 * 78 * If non-NULL, will be set as the parent of this GPIO interrupt 79 * controller's IRQ domain to establish a hierarchical interrupt 80 * domain. The presence of this will activate the hierarchical 81 * interrupt support. 82 */ 83 struct irq_domain *parent_domain; 84 85 /** 86 * @child_to_parent_hwirq: 87 * 88 * This callback translates a child hardware IRQ offset to a parent 89 * hardware IRQ offset on a hierarchical interrupt chip. The child 90 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the 91 * ngpio field of struct gpio_chip) and the corresponding parent 92 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by 93 * the driver. The driver can calculate this from an offset or using 94 * a lookup table or whatever method is best for this chip. Return 95 * 0 on successful translation in the driver. 96 * 97 * If some ranges of hardware IRQs do not have a corresponding parent 98 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and 99 * @need_valid_mask to make these GPIO lines unavailable for 100 * translation. 101 */ 102 int (*child_to_parent_hwirq)(struct gpio_chip *gc, 103 unsigned int child_hwirq, 104 unsigned int child_type, 105 unsigned int *parent_hwirq, 106 unsigned int *parent_type); 107 108 /** 109 * @populate_parent_alloc_arg : 110 * 111 * This optional callback allocates and populates the specific struct 112 * for the parent's IRQ domain. If this is not specified, then 113 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell 114 * variant named &gpiochip_populate_parent_fwspec_fourcell is also 115 * available. 116 */ 117 int (*populate_parent_alloc_arg)(struct gpio_chip *gc, 118 union gpio_irq_fwspec *fwspec, 119 unsigned int parent_hwirq, 120 unsigned int parent_type); 121 122 /** 123 * @child_offset_to_irq: 124 * 125 * This optional callback is used to translate the child's GPIO line 126 * offset on the GPIO chip to an IRQ number for the GPIO to_irq() 127 * callback. If this is not specified, then a default callback will be 128 * provided that returns the line offset. 129 */ 130 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc, 131 unsigned int pin); 132 133 /** 134 * @child_irq_domain_ops: 135 * 136 * The IRQ domain operations that will be used for this GPIO IRQ 137 * chip. If no operations are provided, then default callbacks will 138 * be populated to setup the IRQ hierarchy. Some drivers need to 139 * supply their own translate function. 140 */ 141 struct irq_domain_ops child_irq_domain_ops; 142#endif 143 144 /** 145 * @handler: 146 * 147 * The IRQ handler to use (often a predefined IRQ core function) for 148 * GPIO IRQs, provided by GPIO driver. 149 */ 150 irq_flow_handler_t handler; 151 152 /** 153 * @default_type: 154 * 155 * Default IRQ triggering type applied during GPIO driver 156 * initialization, provided by GPIO driver. 157 */ 158 unsigned int default_type; 159 160 /** 161 * @lock_key: 162 * 163 * Per GPIO IRQ chip lockdep class for IRQ lock. 164 */ 165 struct lock_class_key *lock_key; 166 167 /** 168 * @request_key: 169 * 170 * Per GPIO IRQ chip lockdep class for IRQ request. 171 */ 172 struct lock_class_key *request_key; 173 174 /** 175 * @parent_handler: 176 * 177 * The interrupt handler for the GPIO chip's parent interrupts, may be 178 * NULL if the parent interrupts are nested rather than cascaded. 179 */ 180 irq_flow_handler_t parent_handler; 181 182 union { 183 /** 184 * @parent_handler_data: 185 * 186 * If @per_parent_data is false, @parent_handler_data is a 187 * single pointer used as the data associated with every 188 * parent interrupt. 189 */ 190 void *parent_handler_data; 191 192 /** 193 * @parent_handler_data_array: 194 * 195 * If @per_parent_data is true, @parent_handler_data_array is 196 * an array of @num_parents pointers, and is used to associate 197 * different data for each parent. This cannot be NULL if 198 * @per_parent_data is true. 199 */ 200 void **parent_handler_data_array; 201 }; 202 203 /** 204 * @num_parents: 205 * 206 * The number of interrupt parents of a GPIO chip. 207 */ 208 unsigned int num_parents; 209 210 /** 211 * @parents: 212 * 213 * A list of interrupt parents of a GPIO chip. This is owned by the 214 * driver, so the core will only reference this list, not modify it. 215 */ 216 unsigned int *parents; 217 218 /** 219 * @map: 220 * 221 * A list of interrupt parents for each line of a GPIO chip. 222 */ 223 unsigned int *map; 224 225 /** 226 * @threaded: 227 * 228 * True if set the interrupt handling uses nested threads. 229 */ 230 bool threaded; 231 232 /** 233 * @per_parent_data: 234 * 235 * True if parent_handler_data_array describes a @num_parents 236 * sized array to be used as parent data. 237 */ 238 bool per_parent_data; 239 240 /** 241 * @initialized: 242 * 243 * Flag to track GPIO chip irq member's initialization. 244 * This flag will make sure GPIO chip irq members are not used 245 * before they are initialized. 246 */ 247 bool initialized; 248 249 /** 250 * @domain_is_allocated_externally: 251 * 252 * True it the irq_domain was allocated outside of gpiolib, in which 253 * case gpiolib won't free the irq_domain itself. 254 */ 255 bool domain_is_allocated_externally; 256 257 /** 258 * @init_hw: optional routine to initialize hardware before 259 * an IRQ chip will be added. This is quite useful when 260 * a particular driver wants to clear IRQ related registers 261 * in order to avoid undesired events. 262 */ 263 int (*init_hw)(struct gpio_chip *gc); 264 265 /** 266 * @init_valid_mask: optional routine to initialize @valid_mask, to be 267 * used if not all GPIO lines are valid interrupts. Sometimes some 268 * lines just cannot fire interrupts, and this routine, when defined, 269 * is passed a bitmap in "valid_mask" and it will have ngpios 270 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can 271 * then directly set some bits to "0" if they cannot be used for 272 * interrupts. 273 */ 274 void (*init_valid_mask)(struct gpio_chip *gc, 275 unsigned long *valid_mask, 276 unsigned int ngpios); 277 278 /** 279 * @valid_mask: 280 * 281 * If not %NULL, holds bitmask of GPIOs which are valid to be included 282 * in IRQ domain of the chip. 283 */ 284 unsigned long *valid_mask; 285 286 /** 287 * @first: 288 * 289 * Required for static IRQ allocation. If set, irq_domain_add_simple() 290 * will allocate and map all IRQs during initialization. 291 */ 292 unsigned int first; 293 294 /** 295 * @irq_enable: 296 * 297 * Store old irq_chip irq_enable callback 298 */ 299 void (*irq_enable)(struct irq_data *data); 300 301 /** 302 * @irq_disable: 303 * 304 * Store old irq_chip irq_disable callback 305 */ 306 void (*irq_disable)(struct irq_data *data); 307 /** 308 * @irq_unmask: 309 * 310 * Store old irq_chip irq_unmask callback 311 */ 312 void (*irq_unmask)(struct irq_data *data); 313 314 /** 315 * @irq_mask: 316 * 317 * Store old irq_chip irq_mask callback 318 */ 319 void (*irq_mask)(struct irq_data *data); 320}; 321 322/** 323 * struct gpio_chip - abstract a GPIO controller 324 * @label: a functional name for the GPIO device, such as a part 325 * number or the name of the SoC IP-block implementing it. 326 * @gpiodev: the internal state holder, opaque struct 327 * @parent: optional parent device providing the GPIOs 328 * @fwnode: optional fwnode providing this controller's properties 329 * @owner: helps prevent removal of modules exporting active GPIOs 330 * @request: optional hook for chip-specific activation, such as 331 * enabling module power and clock; may sleep 332 * @free: optional hook for chip-specific deactivation, such as 333 * disabling module power and clock; may sleep 334 * @get_direction: returns direction for signal "offset", 0=out, 1=in, 335 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN), 336 * or negative error. It is recommended to always implement this 337 * function, even on input-only or output-only gpio chips. 338 * @direction_input: configures signal "offset" as input, returns 0 on success 339 * or a negative error number. This can be omitted on input-only or 340 * output-only gpio chips. 341 * @direction_output: configures signal "offset" as output, returns 0 on 342 * success or a negative error number. This can be omitted on input-only 343 * or output-only gpio chips. 344 * @get: returns value for signal "offset", 0=low, 1=high, or negative error 345 * @get_multiple: reads values for multiple signals defined by "mask" and 346 * stores them in "bits", returns 0 on success or negative error 347 * @set: assigns output value for signal "offset" 348 * @set_multiple: assigns output values for multiple signals defined by "mask" 349 * @set_config: optional hook for all kinds of settings. Uses the same 350 * packed config format as generic pinconf. 351 * @to_irq: optional hook supporting non-static gpiod_to_irq() mappings; 352 * implementation may not sleep 353 * @dbg_show: optional routine to show contents in debugfs; default code 354 * will be used when this is omitted, but custom code can show extra 355 * state (such as pullup/pulldown configuration). 356 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if 357 * not all GPIOs are valid. 358 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when 359 * requires special mapping of the pins that provides GPIO functionality. 360 * It is called after adding GPIO chip and before adding IRQ chip. 361 * @en_hw_timestamp: Dependent on GPIO chip, an optional routine to 362 * enable hardware timestamp. 363 * @dis_hw_timestamp: Dependent on GPIO chip, an optional routine to 364 * disable hardware timestamp. 365 * @base: identifies the first GPIO number handled by this chip; 366 * or, if negative during registration, requests dynamic ID allocation. 367 * DEPRECATION: providing anything non-negative and nailing the base 368 * offset of GPIO chips is deprecated. Please pass -1 as base to 369 * let gpiolib select the chip base in all possible cases. We want to 370 * get rid of the static GPIO number space in the long run. 371 * @ngpio: the number of GPIOs handled by this controller; the last GPIO 372 * handled is (base + ngpio - 1). 373 * @offset: when multiple gpio chips belong to the same device this 374 * can be used as offset within the device so friendly names can 375 * be properly assigned. 376 * @names: if set, must be an array of strings to use as alternative 377 * names for the GPIOs in this chip. Any entry in the array 378 * may be NULL if there is no alias for the GPIO, however the 379 * array must be @ngpio entries long. A name can include a single printk 380 * format specifier for an unsigned int. It is substituted by the actual 381 * number of the gpio. 382 * @can_sleep: flag must be set iff get()/set() methods sleep, as they 383 * must while accessing GPIO expander chips over I2C or SPI. This 384 * implies that if the chip supports IRQs, these IRQs need to be threaded 385 * as the chip access may sleep when e.g. reading out the IRQ status 386 * registers. 387 * @read_reg: reader function for generic GPIO 388 * @write_reg: writer function for generic GPIO 389 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing 390 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the 391 * generic GPIO core. It is for internal housekeeping only. 392 * @reg_dat: data (in) register for generic GPIO 393 * @reg_set: output set register (out=high) for generic GPIO 394 * @reg_clr: output clear register (out=low) for generic GPIO 395 * @reg_dir_out: direction out setting register for generic GPIO 396 * @reg_dir_in: direction in setting register for generic GPIO 397 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot 398 * be read and we need to rely on out internal state tracking. 399 * @bgpio_bits: number of register bits used for a generic GPIO i.e. 400 * <register width> * 8 401 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep 402 * shadowed and real data registers writes together. 403 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits 404 * safely. 405 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set 406 * direction safely. A "1" in this word means the line is set as 407 * output. 408 * 409 * A gpio_chip can help platforms abstract various sources of GPIOs so 410 * they can all be accessed through a common programming interface. 411 * Example sources would be SOC controllers, FPGAs, multifunction 412 * chips, dedicated GPIO expanders, and so on. 413 * 414 * Each chip controls a number of signals, identified in method calls 415 * by "offset" values in the range 0..(@ngpio - 1). When those signals 416 * are referenced through calls like gpio_get_value(gpio), the offset 417 * is calculated by subtracting @base from the gpio number. 418 */ 419struct gpio_chip { 420 const char *label; 421 struct gpio_device *gpiodev; 422 struct device *parent; 423 struct fwnode_handle *fwnode; 424 struct module *owner; 425 426 int (*request)(struct gpio_chip *gc, 427 unsigned int offset); 428 void (*free)(struct gpio_chip *gc, 429 unsigned int offset); 430 int (*get_direction)(struct gpio_chip *gc, 431 unsigned int offset); 432 int (*direction_input)(struct gpio_chip *gc, 433 unsigned int offset); 434 int (*direction_output)(struct gpio_chip *gc, 435 unsigned int offset, int value); 436 int (*get)(struct gpio_chip *gc, 437 unsigned int offset); 438 int (*get_multiple)(struct gpio_chip *gc, 439 unsigned long *mask, 440 unsigned long *bits); 441 void (*set)(struct gpio_chip *gc, 442 unsigned int offset, int value); 443 void (*set_multiple)(struct gpio_chip *gc, 444 unsigned long *mask, 445 unsigned long *bits); 446 int (*set_config)(struct gpio_chip *gc, 447 unsigned int offset, 448 unsigned long config); 449 int (*to_irq)(struct gpio_chip *gc, 450 unsigned int offset); 451 452 void (*dbg_show)(struct seq_file *s, 453 struct gpio_chip *gc); 454 455 int (*init_valid_mask)(struct gpio_chip *gc, 456 unsigned long *valid_mask, 457 unsigned int ngpios); 458 459 int (*add_pin_ranges)(struct gpio_chip *gc); 460 461 int (*en_hw_timestamp)(struct gpio_chip *gc, 462 u32 offset, 463 unsigned long flags); 464 int (*dis_hw_timestamp)(struct gpio_chip *gc, 465 u32 offset, 466 unsigned long flags); 467 int base; 468 u16 ngpio; 469 u16 offset; 470 const char *const *names; 471 bool can_sleep; 472 473#if IS_ENABLED(CONFIG_GPIO_GENERIC) 474 unsigned long (*read_reg)(void __iomem *reg); 475 void (*write_reg)(void __iomem *reg, unsigned long data); 476 bool be_bits; 477 void __iomem *reg_dat; 478 void __iomem *reg_set; 479 void __iomem *reg_clr; 480 void __iomem *reg_dir_out; 481 void __iomem *reg_dir_in; 482 bool bgpio_dir_unreadable; 483 int bgpio_bits; 484 raw_spinlock_t bgpio_lock; 485 unsigned long bgpio_data; 486 unsigned long bgpio_dir; 487#endif /* CONFIG_GPIO_GENERIC */ 488 489#ifdef CONFIG_GPIOLIB_IRQCHIP 490 /* 491 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib 492 * to handle IRQs for most practical cases. 493 */ 494 495 /** 496 * @irq: 497 * 498 * Integrates interrupt chip functionality with the GPIO chip. Can be 499 * used to handle IRQs for most practical cases. 500 */ 501 struct gpio_irq_chip irq; 502#endif /* CONFIG_GPIOLIB_IRQCHIP */ 503 504 /** 505 * @valid_mask: 506 * 507 * If not %NULL, holds bitmask of GPIOs which are valid to be used 508 * from the chip. 509 */ 510 unsigned long *valid_mask; 511 512#if defined(CONFIG_OF_GPIO) 513 /* 514 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in 515 * the device tree automatically may have an OF translation 516 */ 517 518 /** 519 * @of_gpio_n_cells: 520 * 521 * Number of cells used to form the GPIO specifier. 522 */ 523 unsigned int of_gpio_n_cells; 524 525 /** 526 * @of_xlate: 527 * 528 * Callback to translate a device tree GPIO specifier into a chip- 529 * relative GPIO number and flags. 530 */ 531 int (*of_xlate)(struct gpio_chip *gc, 532 const struct of_phandle_args *gpiospec, u32 *flags); 533#endif /* CONFIG_OF_GPIO */ 534}; 535 536char *gpiochip_dup_line_label(struct gpio_chip *gc, unsigned int offset); 537 538 539struct _gpiochip_for_each_data { 540 const char **label; 541 unsigned int *i; 542}; 543 544DEFINE_CLASS(_gpiochip_for_each_data, 545 struct _gpiochip_for_each_data, 546 if (*_T.label) kfree(*_T.label), 547 ({ 548 struct _gpiochip_for_each_data _data = { label, i }; 549 *_data.i = 0; 550 _data; 551 }), 552 const char **label, int *i) 553 554/** 555 * for_each_hwgpio - Iterates over all GPIOs for given chip. 556 * @_chip: Chip to iterate over. 557 * @_i: Loop counter. 558 * @_label: Place to store the address of the label if the GPIO is requested. 559 * Set to NULL for unused GPIOs. 560 */ 561#define for_each_hwgpio(_chip, _i, _label) \ 562 for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \ 563 *_data.i < _chip->ngpio; \ 564 (*_data.i)++, kfree(*(_data.label)), *_data.label = NULL) \ 565 if (IS_ERR(*_data.label = \ 566 gpiochip_dup_line_label(_chip, *_data.i))) {} \ 567 else 568 569/** 570 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range 571 * @_chip: the chip to query 572 * @_i: loop variable 573 * @_base: first GPIO in the range 574 * @_size: amount of GPIOs to check starting from @base 575 * @_label: label of current GPIO 576 */ 577#define for_each_requested_gpio_in_range(_chip, _i, _base, _size, _label) \ 578 for (CLASS(_gpiochip_for_each_data, _data)(&_label, &_i); \ 579 *_data.i < _size; \ 580 (*_data.i)++, kfree(*(_data.label)), *_data.label = NULL) \ 581 if ((*_data.label = \ 582 gpiochip_dup_line_label(_chip, _base + *_data.i)) == NULL) {} \ 583 else if (IS_ERR(*_data.label)) {} \ 584 else 585 586/* Iterates over all requested GPIO of the given @chip */ 587#define for_each_requested_gpio(chip, i, label) \ 588 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label) 589 590/* add/remove chips */ 591int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data, 592 struct lock_class_key *lock_key, 593 struct lock_class_key *request_key); 594 595/** 596 * gpiochip_add_data() - register a gpio_chip 597 * @gc: the chip to register, with gc->base initialized 598 * @data: driver-private data associated with this chip 599 * 600 * Context: potentially before irqs will work 601 * 602 * When gpiochip_add_data() is called very early during boot, so that GPIOs 603 * can be freely used, the gc->parent device must be registered before 604 * the gpio framework's arch_initcall(). Otherwise sysfs initialization 605 * for GPIOs will fail rudely. 606 * 607 * gpiochip_add_data() must only be called after gpiolib initialization, 608 * i.e. after core_initcall(). 609 * 610 * If gc->base is negative, this requests dynamic assignment of 611 * a range of valid GPIOs. 612 * 613 * Returns: 614 * A negative errno if the chip can't be registered, such as because the 615 * gc->base is invalid or already associated with a different chip. 616 * Otherwise it returns zero as a success code. 617 */ 618#ifdef CONFIG_LOCKDEP 619#define gpiochip_add_data(gc, data) ({ \ 620 static struct lock_class_key lock_key; \ 621 static struct lock_class_key request_key; \ 622 gpiochip_add_data_with_key(gc, data, &lock_key, \ 623 &request_key); \ 624 }) 625#define devm_gpiochip_add_data(dev, gc, data) ({ \ 626 static struct lock_class_key lock_key; \ 627 static struct lock_class_key request_key; \ 628 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \ 629 &request_key); \ 630 }) 631#else 632#define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL) 633#define devm_gpiochip_add_data(dev, gc, data) \ 634 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL) 635#endif /* CONFIG_LOCKDEP */ 636 637static inline int gpiochip_add(struct gpio_chip *gc) 638{ 639 return gpiochip_add_data(gc, NULL); 640} 641void gpiochip_remove(struct gpio_chip *gc); 642int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, 643 void *data, struct lock_class_key *lock_key, 644 struct lock_class_key *request_key); 645 646struct gpio_device *gpio_device_find(const void *data, 647 int (*match)(struct gpio_chip *gc, 648 const void *data)); 649 650struct gpio_device *gpio_device_get(struct gpio_device *gdev); 651void gpio_device_put(struct gpio_device *gdev); 652 653DEFINE_FREE(gpio_device_put, struct gpio_device *, 654 if (!IS_ERR_OR_NULL(_T)) gpio_device_put(_T)) 655 656struct device *gpio_device_to_device(struct gpio_device *gdev); 657 658bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset); 659int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset); 660void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset); 661void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset); 662void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset); 663 664/* irq_data versions of the above */ 665int gpiochip_irq_reqres(struct irq_data *data); 666void gpiochip_irq_relres(struct irq_data *data); 667 668/* Paste this in your irq_chip structure */ 669#define GPIOCHIP_IRQ_RESOURCE_HELPERS \ 670 .irq_request_resources = gpiochip_irq_reqres, \ 671 .irq_release_resources = gpiochip_irq_relres 672 673static inline void gpio_irq_chip_set_chip(struct gpio_irq_chip *girq, 674 const struct irq_chip *chip) 675{ 676 /* Yes, dropping const is ugly, but it isn't like we have a choice */ 677 girq->chip = (struct irq_chip *)chip; 678} 679 680/* Line status inquiry for drivers */ 681bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset); 682bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset); 683 684/* Sleep persistence inquiry for drivers */ 685bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset); 686bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset); 687 688/* get driver data */ 689void *gpiochip_get_data(struct gpio_chip *gc); 690 691struct bgpio_pdata { 692 const char *label; 693 int base; 694 int ngpio; 695}; 696 697#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 698 699int gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc, 700 union gpio_irq_fwspec *gfwspec, 701 unsigned int parent_hwirq, 702 unsigned int parent_type); 703int gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc, 704 union gpio_irq_fwspec *gfwspec, 705 unsigned int parent_hwirq, 706 unsigned int parent_type); 707 708#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ 709 710int bgpio_init(struct gpio_chip *gc, struct device *dev, 711 unsigned long sz, void __iomem *dat, void __iomem *set, 712 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 713 unsigned long flags); 714 715#define BGPIOF_BIG_ENDIAN BIT(0) 716#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */ 717#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */ 718#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3) 719#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */ 720#define BGPIOF_NO_OUTPUT BIT(5) /* only input */ 721#define BGPIOF_NO_SET_ON_INPUT BIT(6) 722 723#ifdef CONFIG_GPIOLIB_IRQCHIP 724int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 725 struct irq_domain *domain); 726#else 727 728#include <asm/bug.h> 729 730static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc, 731 struct irq_domain *domain) 732{ 733 WARN_ON(1); 734 return -EINVAL; 735} 736#endif 737 738int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset); 739void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset); 740int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset, 741 unsigned long config); 742 743/** 744 * struct gpio_pin_range - pin range controlled by a gpio chip 745 * @node: list for maintaining set of pin ranges, used internally 746 * @pctldev: pinctrl device which handles corresponding pins 747 * @range: actual range of pins controlled by a gpio controller 748 */ 749struct gpio_pin_range { 750 struct list_head node; 751 struct pinctrl_dev *pctldev; 752 struct pinctrl_gpio_range range; 753}; 754 755#ifdef CONFIG_PINCTRL 756 757int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 758 unsigned int gpio_offset, unsigned int pin_offset, 759 unsigned int npins); 760int gpiochip_add_pingroup_range(struct gpio_chip *gc, 761 struct pinctrl_dev *pctldev, 762 unsigned int gpio_offset, const char *pin_group); 763void gpiochip_remove_pin_ranges(struct gpio_chip *gc); 764 765#else /* ! CONFIG_PINCTRL */ 766 767static inline int 768gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name, 769 unsigned int gpio_offset, unsigned int pin_offset, 770 unsigned int npins) 771{ 772 return 0; 773} 774static inline int 775gpiochip_add_pingroup_range(struct gpio_chip *gc, 776 struct pinctrl_dev *pctldev, 777 unsigned int gpio_offset, const char *pin_group) 778{ 779 return 0; 780} 781 782static inline void 783gpiochip_remove_pin_ranges(struct gpio_chip *gc) 784{ 785} 786 787#endif /* CONFIG_PINCTRL */ 788 789struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc, 790 unsigned int hwnum, 791 const char *label, 792 enum gpio_lookup_flags lflags, 793 enum gpiod_flags dflags); 794void gpiochip_free_own_desc(struct gpio_desc *desc); 795 796struct gpio_desc *gpiochip_get_desc(struct gpio_chip *gc, unsigned int hwnum); 797struct gpio_desc * 798gpio_device_get_desc(struct gpio_device *gdev, unsigned int hwnum); 799 800struct gpio_chip *gpio_device_get_chip(struct gpio_device *gdev); 801 802#ifdef CONFIG_GPIOLIB 803 804/* lock/unlock as IRQ */ 805int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset); 806void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset); 807 808struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc); 809struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc); 810 811/* struct gpio_device getters */ 812int gpio_device_get_base(struct gpio_device *gdev); 813const char *gpio_device_get_label(struct gpio_device *gdev); 814 815struct gpio_device *gpio_device_find_by_label(const char *label); 816struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode); 817 818#else /* CONFIG_GPIOLIB */ 819 820#include <asm/bug.h> 821 822static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc) 823{ 824 /* GPIO can never have been requested */ 825 WARN_ON(1); 826 return ERR_PTR(-ENODEV); 827} 828 829static inline struct gpio_device *gpiod_to_gpio_device(struct gpio_desc *desc) 830{ 831 WARN_ON(1); 832 return ERR_PTR(-ENODEV); 833} 834 835static inline int gpio_device_get_base(struct gpio_device *gdev) 836{ 837 WARN_ON(1); 838 return -ENODEV; 839} 840 841static inline const char *gpio_device_get_label(struct gpio_device *gdev) 842{ 843 WARN_ON(1); 844 return NULL; 845} 846 847static inline struct gpio_device *gpio_device_find_by_label(const char *label) 848{ 849 WARN_ON(1); 850 return NULL; 851} 852 853static inline struct gpio_device *gpio_device_find_by_fwnode(const struct fwnode_handle *fwnode) 854{ 855 WARN_ON(1); 856 return NULL; 857} 858 859static inline int gpiochip_lock_as_irq(struct gpio_chip *gc, 860 unsigned int offset) 861{ 862 WARN_ON(1); 863 return -EINVAL; 864} 865 866static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc, 867 unsigned int offset) 868{ 869 WARN_ON(1); 870} 871#endif /* CONFIG_GPIOLIB */ 872 873#define for_each_gpiochip_node(dev, child) \ 874 device_for_each_child_node(dev, child) \ 875 if (!fwnode_property_present(child, "gpio-controller")) {} else 876 877static inline unsigned int gpiochip_node_count(struct device *dev) 878{ 879 struct fwnode_handle *child; 880 unsigned int count = 0; 881 882 for_each_gpiochip_node(dev, child) 883 count++; 884 885 return count; 886} 887 888static inline struct fwnode_handle *gpiochip_node_get_first(struct device *dev) 889{ 890 struct fwnode_handle *fwnode; 891 892 for_each_gpiochip_node(dev, fwnode) 893 return fwnode; 894 895 return NULL; 896} 897 898#endif /* __LINUX_GPIO_DRIVER_H */ 899