1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Marvell 88SE64xx/88SE94xx main function head file 4 * 5 * Copyright 2007 Red Hat, Inc. 6 * Copyright 2008 Marvell. <kewei@marvell.com> 7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 8*/ 9 10#ifndef _MV_SAS_H_ 11#define _MV_SAS_H_ 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/spinlock.h> 16#include <linux/delay.h> 17#include <linux/types.h> 18#include <linux/ctype.h> 19#include <linux/dma-mapping.h> 20#include <linux/pci.h> 21#include <linux/platform_device.h> 22#include <linux/interrupt.h> 23#include <linux/irq.h> 24#include <linux/slab.h> 25#include <linux/vmalloc.h> 26#include <asm/unaligned.h> 27#include <scsi/libsas.h> 28#include <scsi/scsi.h> 29#include <scsi/scsi_tcq.h> 30#include <scsi/sas_ata.h> 31#include "mv_defs.h" 32 33#define DRV_NAME "mvsas" 34#define DRV_VERSION "0.8.16" 35#define MVS_ID_NOT_MAPPED 0x7f 36#define WIDE_PORT_MAX_PHY 4 37#define mv_printk(fmt, arg ...) \ 38 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg) 39#ifdef MV_DEBUG 40#define mv_dprintk(format, arg...) \ 41 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg) 42#else 43#define mv_dprintk(format, arg...) no_printk(format, ## arg) 44#endif 45#define MV_MAX_U32 0xffffffff 46 47extern int interrupt_coalescing; 48extern struct mvs_tgt_initiator mvs_tgt; 49extern struct mvs_info *tgt_mvi; 50extern const struct mvs_dispatch mvs_64xx_dispatch; 51extern const struct mvs_dispatch mvs_94xx_dispatch; 52 53#define bit(n) ((u64)1 << n) 54 55#define for_each_phy(__lseq_mask, __mc, __lseq) \ 56 for ((__mc) = (__lseq_mask), (__lseq) = 0; \ 57 (__mc) != 0 ; \ 58 (++__lseq), (__mc) >>= 1) 59 60#define MVS_PHY_ID (1U << sas_phy->id) 61#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f) 62#define UNASSOC_D2H_FIS(id) \ 63 ((void *) mvi->rx_fis + 0x100 * id) 64#define SATA_RECEIVED_FIS_LIST(reg_set) \ 65 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set) 66#define SATA_RECEIVED_SDB_FIS(reg_set) \ 67 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58) 68#define SATA_RECEIVED_D2H_FIS(reg_set) \ 69 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40) 70#define SATA_RECEIVED_PIO_FIS(reg_set) \ 71 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20) 72#define SATA_RECEIVED_DMA_FIS(reg_set) \ 73 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00) 74 75enum dev_status { 76 MVS_DEV_NORMAL = 0x0, 77 MVS_DEV_EH = 0x1, 78}; 79 80enum dev_reset { 81 MVS_SOFT_RESET = 0, 82 MVS_HARD_RESET = 1, 83 MVS_PHY_TUNE = 2, 84}; 85 86struct mvs_info; 87struct mvs_prv_info; 88 89struct mvs_dispatch { 90 char *name; 91 int (*chip_init)(struct mvs_info *mvi); 92 int (*spi_init)(struct mvs_info *mvi); 93 int (*chip_ioremap)(struct mvs_info *mvi); 94 void (*chip_iounmap)(struct mvs_info *mvi); 95 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat); 96 u32 (*isr_status)(struct mvs_info *mvi, int irq); 97 void (*interrupt_enable)(struct mvs_info *mvi); 98 void (*interrupt_disable)(struct mvs_info *mvi); 99 100 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port); 101 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val); 102 103 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port); 104 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val); 105 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr); 106 107 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port); 108 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val); 109 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr); 110 111 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port); 112 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val); 113 114 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port); 115 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val); 116 117 void (*command_active)(struct mvs_info *mvi, u32 slot_idx); 118 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all); 119 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type, 120 u32 tfs); 121 void (*start_delivery)(struct mvs_info *mvi, u32 tx); 122 u32 (*rx_update)(struct mvs_info *mvi); 123 void (*int_full)(struct mvs_info *mvi); 124 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs); 125 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs); 126 u32 (*prd_size)(void); 127 u32 (*prd_count)(void); 128 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd); 129 void (*detect_porttype)(struct mvs_info *mvi, int i); 130 int (*oob_done)(struct mvs_info *mvi, int i); 131 void (*fix_phy_info)(struct mvs_info *mvi, int i, 132 struct sas_identify_frame *id); 133 void (*phy_work_around)(struct mvs_info *mvi, int i); 134 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id, 135 struct sas_phy_linkrates *rates); 136 u32 (*phy_max_link_rate)(void); 137 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id); 138 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id); 139 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard); 140 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id); 141 void (*clear_active_cmds)(struct mvs_info *mvi); 142 u32 (*spi_read_data)(struct mvs_info *mvi); 143 void (*spi_write_data)(struct mvs_info *mvi, u32 data); 144 int (*spi_buildcmd)(struct mvs_info *mvi, 145 u32 *dwCmd, 146 u8 cmd, 147 u8 read, 148 u8 length, 149 u32 addr 150 ); 151 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd); 152 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout); 153 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask, 154 int buf_len, int from, void *prd); 155 void (*tune_interrupt)(struct mvs_info *mvi, u32 time); 156 void (*non_spec_ncq_error)(struct mvs_info *mvi); 157 int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type, 158 u8 reg_index, u8 reg_count, u8 *write_data); 159 160}; 161 162struct mvs_chip_info { 163 u32 n_host; 164 u32 n_phy; 165 u32 fis_offs; 166 u32 fis_count; 167 u32 srs_sz; 168 u32 sg_width; 169 u32 slot_width; 170 const struct mvs_dispatch *dispatch; 171}; 172#define MVS_MAX_SG (1U << mvi->chip->sg_width) 173#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) 174#define MVS_RX_FISL_SZ \ 175 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100)) 176#define MVS_CHIP_DISP (mvi->chip->dispatch) 177 178struct mvs_err_info { 179 __le32 flags; 180 __le32 flags2; 181}; 182 183struct mvs_cmd_hdr { 184 __le32 flags; /* PRD tbl len; SAS, SATA ctl */ 185 __le32 lens; /* cmd, max resp frame len */ 186 __le32 tags; /* targ port xfer tag; tag */ 187 __le32 data_len; /* data xfer len */ 188 __le64 cmd_tbl; /* command table address */ 189 __le64 open_frame; /* open addr frame address */ 190 __le64 status_buf; /* status buffer address */ 191 __le64 prd_tbl; /* PRD tbl address */ 192 __le32 reserved[4]; 193}; 194 195struct mvs_port { 196 struct asd_sas_port sas_port; 197 u8 port_attached; 198 u8 wide_port_phymap; 199 struct list_head list; 200}; 201 202struct mvs_phy { 203 struct mvs_info *mvi; 204 struct mvs_port *port; 205 struct asd_sas_phy sas_phy; 206 struct sas_identify identify; 207 struct scsi_device *sdev; 208 struct timer_list timer; 209 u64 dev_sas_addr; 210 u64 att_dev_sas_addr; 211 u32 att_dev_info; 212 u32 dev_info; 213 u32 phy_type; 214 u32 phy_status; 215 u32 irq_status; 216 u32 frame_rcvd_size; 217 u8 frame_rcvd[32]; 218 u8 phy_attached; 219 u8 phy_mode; 220 u8 reserved[2]; 221 u32 phy_event; 222 enum sas_linkrate minimum_linkrate; 223 enum sas_linkrate maximum_linkrate; 224}; 225 226struct mvs_device { 227 struct list_head dev_entry; 228 enum sas_device_type dev_type; 229 struct mvs_info *mvi_info; 230 struct domain_device *sas_device; 231 u32 attached_phy; 232 u32 device_id; 233 u32 running_req; 234 u8 taskfileset; 235 u8 dev_status; 236 u16 reserved; 237}; 238 239/* Generate PHY tunning parameters */ 240struct phy_tuning { 241 /* 1 bit, transmitter emphasis enable */ 242 u8 trans_emp_en:1; 243 /* 4 bits, transmitter emphasis amplitude */ 244 u8 trans_emp_amp:4; 245 /* 3 bits, reserved space */ 246 u8 Reserved_2bit_1:3; 247 /* 5 bits, transmitter amplitude */ 248 u8 trans_amp:5; 249 /* 2 bits, transmitter amplitude adjust */ 250 u8 trans_amp_adj:2; 251 /* 1 bit, reserved space */ 252 u8 resv_2bit_2:1; 253 /* 2 bytes, reserved space */ 254 u8 reserved[2]; 255}; 256 257struct ffe_control { 258 /* 4 bits, FFE Capacitor Select (value range 0~F) */ 259 u8 ffe_cap_sel:4; 260 /* 3 bits, FFE Resistor Select (value range 0~7) */ 261 u8 ffe_rss_sel:3; 262 /* 1 bit reserve*/ 263 u8 reserved:1; 264}; 265 266/* 267 * HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes. 268 * The data area is valid only Signature="MRVL". 269 * If any member fills with 0xFF, the member is invalid. 270 */ 271struct hba_info_page { 272 /* Dword 0 */ 273 /* 4 bytes, structure signature,should be "MRVL" at first initial */ 274 u8 signature[4]; 275 276 /* Dword 1-13 */ 277 u32 reserved1[13]; 278 279 /* Dword 14-29 */ 280 /* 64 bytes, SAS address for each port */ 281 u64 sas_addr[8]; 282 283 /* Dword 30-31 */ 284 /* 8 bytes for vanir 8 port PHY FFE seeting 285 * BIT 0~3 : FFE Capacitor select(value range 0~F) 286 * BIT 4~6 : FFE Resistor select(value range 0~7) 287 * BIT 7: reserve. 288 */ 289 290 struct ffe_control ffe_ctl[8]; 291 /* Dword 32 -43 */ 292 u32 reserved2[12]; 293 294 /* Dword 44-45 */ 295 /* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */ 296 u8 phy_rate[8]; 297 298 /* Dword 46-53 */ 299 /* 32 bytes, PHY tuning parameters for each PHY*/ 300 struct phy_tuning phy_tuning[8]; 301 302 /* Dword 54-63 */ 303 u32 reserved3[10]; 304}; /* total 256 bytes */ 305 306struct mvs_slot_info { 307 struct list_head entry; 308 union { 309 struct sas_task *task; 310 void *tdata; 311 }; 312 u32 n_elem; 313 u32 tx; 314 u32 slot_tag; 315 316 /* DMA buffer for storing cmd tbl, open addr frame, status buffer, 317 * and PRD table 318 */ 319 void *buf; 320 dma_addr_t buf_dma; 321 void *response; 322 struct mvs_port *port; 323 struct mvs_device *device; 324 void *open_frame; 325}; 326 327struct mvs_info { 328 unsigned long flags; 329 330 /* host-wide lock */ 331 spinlock_t lock; 332 333 /* our device */ 334 struct pci_dev *pdev; 335 struct device *dev; 336 337 /* enhanced mode registers */ 338 void __iomem *regs; 339 340 /* peripheral or soc registers */ 341 void __iomem *regs_ex; 342 u8 sas_addr[SAS_ADDR_SIZE]; 343 344 /* SCSI/SAS glue */ 345 struct sas_ha_struct *sas; 346 struct Scsi_Host *shost; 347 348 /* TX (delivery) DMA ring */ 349 __le32 *tx; 350 dma_addr_t tx_dma; 351 352 /* cached next-producer idx */ 353 u32 tx_prod; 354 355 /* RX (completion) DMA ring */ 356 __le32 *rx; 357 dma_addr_t rx_dma; 358 359 /* RX consumer idx */ 360 u32 rx_cons; 361 362 /* RX'd FIS area */ 363 __le32 *rx_fis; 364 dma_addr_t rx_fis_dma; 365 366 /* DMA command header slots */ 367 struct mvs_cmd_hdr *slot; 368 dma_addr_t slot_dma; 369 370 u32 chip_id; 371 const struct mvs_chip_info *chip; 372 373 unsigned long *rsvd_tags; 374 /* further per-slot information */ 375 struct mvs_phy phy[MVS_MAX_PHYS]; 376 struct mvs_port port[MVS_MAX_PHYS]; 377 u32 id; 378 u64 sata_reg_set; 379 struct list_head *hba_list; 380 struct list_head soc_entry; 381 struct list_head wq_list; 382 unsigned long instance; 383 u16 flashid; 384 u32 flashsize; 385 u32 flashsectSize; 386 387 void *addon; 388 struct hba_info_page hba_info_param; 389 struct mvs_device devices[MVS_MAX_DEVICES]; 390 void *bulk_buffer; 391 dma_addr_t bulk_buffer_dma; 392 void *bulk_buffer1; 393 dma_addr_t bulk_buffer_dma1; 394#define TRASH_BUCKET_SIZE 0x20000 395 void *dma_pool; 396 struct mvs_slot_info slot_info[]; 397}; 398 399struct mvs_prv_info{ 400 u8 n_host; 401 u8 n_phy; 402 u8 scan_finished; 403 u8 reserve; 404 struct mvs_info *mvi[2]; 405 struct tasklet_struct mv_tasklet; 406}; 407 408struct mvs_wq { 409 struct delayed_work work_q; 410 struct mvs_info *mvi; 411 void *data; 412 int handler; 413 struct list_head entry; 414}; 415 416struct mvs_task_exec_info { 417 struct sas_task *task; 418 struct mvs_cmd_hdr *hdr; 419 struct mvs_port *port; 420 u32 tag; 421 int n_elem; 422}; 423 424/******************** function prototype *********************/ 425void mvs_get_sas_addr(void *buf, u32 buflen); 426void mvs_iounmap(void __iomem *regs); 427int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex); 428void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard); 429int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, 430 void *funcdata); 431void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo, 432 u32 off_hi, u64 sas_addr); 433void mvs_scan_start(struct Scsi_Host *shost); 434int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); 435int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags); 436int mvs_abort_task(struct sas_task *task); 437void mvs_port_formed(struct asd_sas_phy *sas_phy); 438void mvs_port_deformed(struct asd_sas_phy *sas_phy); 439int mvs_dev_found(struct domain_device *dev); 440void mvs_dev_gone(struct domain_device *dev); 441int mvs_lu_reset(struct domain_device *dev, u8 *lun); 442int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags); 443int mvs_I_T_nexus_reset(struct domain_device *dev); 444int mvs_query_task(struct sas_task *task); 445void mvs_release_task(struct mvs_info *mvi, 446 struct domain_device *dev); 447void mvs_do_release_task(struct mvs_info *mvi, int phy_no, 448 struct domain_device *dev); 449void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events); 450void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st); 451int mvs_int_rx(struct mvs_info *mvi, bool self_clear); 452struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set); 453int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index, 454 u8 reg_count, u8 *write_data); 455#endif 456 457