/linux-master/drivers/mmc/host/ |
H A D | cavium.h | 37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off) 38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off) 39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off) 40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off) 41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off) 42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off) 43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off) 44 #define MIO_EMM_INT(x) (0x78 + x->reg_off) 45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off) 46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off) 59 int reg_off; member in struct:cvm_mmc_host [all...] |
/linux-master/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_vbif.c | 61 u32 reg_off; local 76 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; 78 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; 81 reg_val = DPU_REG_READ(c, reg_off); 84 DPU_REG_WRITE(c, reg_off, reg_val); 92 u32 reg_off; local 96 reg_off = VBIF_IN_RD_LIM_CONF0; 98 reg_off = VBIF_IN_WR_LIM_CONF0; 100 reg_off += (xin_id / 4) * 4; 102 reg_val = DPU_REG_READ(c, reg_off); 113 u32 reg_off; local [all...] |
/linux-master/tools/lib/bpf/ |
H A D | usdt.c | 208 short reg_off; member in struct:usdt_arg_spec 1244 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg64) macro 1246 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg32) 1248 { {"rip", "eip", "", ""}, reg_off(rip, eip) }, 1249 { {"rax", "eax", "ax", "al"}, reg_off(rax, eax) }, 1250 { {"rbx", "ebx", "bx", "bl"}, reg_off(rbx, ebx) }, 1251 { {"rcx", "ecx", "cx", "cl"}, reg_off(rcx, ecx) }, 1252 { {"rdx", "edx", "dx", "dl"}, reg_off(rdx, edx) }, 1253 { {"rsi", "esi", "si", "sil"}, reg_off(rsi, esi) }, 1254 { {"rdi", "edi", "di", "dil"}, reg_off(rd 1257 #undef reg_off macro 1285 int len, reg_off; local 1386 int len, reg_off; local 1480 int len, reg_off; local 1551 int len, reg_off; local [all...] |
/linux-master/tools/testing/selftests/kvm/riscv/ |
H A D | get-reg-list.c | 179 /* reg_off is the offset into struct kvm_riscv_config */ 180 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); local 184 switch (reg_off) { 201 return strdup_printf("%lld /* UNKNOWN */", reg_off); 206 /* reg_off is the offset into struct kvm_riscv_core */ 207 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); local 211 switch (reg_off) { 224 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); 227 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); 230 reg_off 251 general_csr_id_to_str(__u64 reg_off) argument 282 aia_csr_id_to_str(__u64 reg_off) argument 305 smstateen_csr_id_to_str(__u64 reg_off) argument 319 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); local 341 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); local 362 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); local 380 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); local 398 isa_ext_single_id_to_str(__u64 reg_off) argument 463 isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) argument 482 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); local 503 sbi_ext_single_id_to_str(__u64 reg_off) argument 526 sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) argument 545 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); local 563 sbi_sta_id_to_str(__u64 reg_off) argument 574 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); local [all...] |
/linux-master/drivers/pinctrl/sunplus/ |
H A D | sppctl.c | 112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) argument 117 *reg_off = (offset / 32) * 4; 123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) argument 133 *reg_off = (offset / 16) * 4; 139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) argument 143 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); 227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, argument 240 writel(reg, pctl->moon1_base + reg_off * 4); 264 u32 reg_off, bit_off, reg; local 266 bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); 299 u32 reg_off, bit_off, reg; local 310 u32 reg_off, bit_off, reg; local 346 u32 reg_off, reg; local 355 u32 reg_off, reg; local 364 u32 reg_off, bit_off, reg; local 376 u32 reg_off, reg; local 385 u32 reg_off, bit_off, reg; local 396 u32 reg_off, bit_off, reg; local 417 u32 reg_off, reg; local 433 u32 reg_off, reg; local 456 u32 reg_off, bit_off, reg; local 467 u32 reg_off, reg; local 478 u32 reg_off, reg; local [all...] |
/linux-master/drivers/clk/meson/ |
H A D | s4-pll.c | 32 .reg_off = ANACTRL_FIXPLL_CTRL0, 37 .reg_off = ANACTRL_FIXPLL_CTRL0, 42 .reg_off = ANACTRL_FIXPLL_CTRL0, 47 .reg_off = ANACTRL_FIXPLL_CTRL0, 52 .reg_off = ANACTRL_FIXPLL_CTRL0, 266 .reg_off = ANACTRL_GP0PLL_CTRL0, 271 .reg_off = ANACTRL_GP0PLL_CTRL0, 276 .reg_off = ANACTRL_GP0PLL_CTRL0, 281 .reg_off = ANACTRL_GP0PLL_CTRL0, 286 .reg_off [all...] |
H A D | a1-pll.c | 22 .reg_off = ANACTRL_FIXPLL_CTRL0, 27 .reg_off = ANACTRL_FIXPLL_CTRL0, 32 .reg_off = ANACTRL_FIXPLL_CTRL0, 37 .reg_off = ANACTRL_FIXPLL_CTRL1, 42 .reg_off = ANACTRL_FIXPLL_STS, 47 .reg_off = ANACTRL_FIXPLL_CTRL0, 93 .reg_off = ANACTRL_HIFIPLL_CTRL0, 98 .reg_off = ANACTRL_HIFIPLL_CTRL0, 103 .reg_off = ANACTRL_HIFIPLL_CTRL0, 108 .reg_off [all...] |
H A D | parm.h | 25 u16 reg_off; member in struct:parm 34 regmap_read(map, p->reg_off, &val); 41 regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift),
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H A D | meson8-ddr.c | 28 .reg_off = AM_DDR_PLL_CNTL, 33 .reg_off = AM_DDR_PLL_CNTL, 38 .reg_off = AM_DDR_PLL_CNTL, 43 .reg_off = AM_DDR_PLL_CNTL, 48 .reg_off = AM_DDR_PLL_CNTL,
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H A D | g12a-aoclk.c | 124 .reg_off = AO_RTC_ALT_CLK_CNTL0, 129 .reg_off = AO_RTC_ALT_CLK_CNTL0, 134 .reg_off = AO_RTC_ALT_CLK_CNTL1, 139 .reg_off = AO_RTC_ALT_CLK_CNTL1, 144 .reg_off = AO_RTC_ALT_CLK_CNTL0, 215 .reg_off = AO_CEC_CLK_CNTL_REG0, 220 .reg_off = AO_CEC_CLK_CNTL_REG0, 225 .reg_off = AO_CEC_CLK_CNTL_REG1, 230 .reg_off = AO_CEC_CLK_CNTL_REG1, 235 .reg_off [all...] |
H A D | axg.c | 31 .reg_off = HHI_MPLL_CNTL, 36 .reg_off = HHI_MPLL_CNTL, 41 .reg_off = HHI_MPLL_CNTL, 46 .reg_off = HHI_MPLL_CNTL2, 51 .reg_off = HHI_MPLL_CNTL, 56 .reg_off = HHI_MPLL_CNTL, 95 .reg_off = HHI_SYS_PLL_CNTL, 100 .reg_off = HHI_SYS_PLL_CNTL, 105 .reg_off = HHI_SYS_PLL_CNTL, 110 .reg_off [all...] |
H A D | axg-aoclk.c | 105 .reg_off = AO_RTC_ALT_CLK_CNTL0, 110 .reg_off = AO_RTC_ALT_CLK_CNTL0, 115 .reg_off = AO_RTC_ALT_CLK_CNTL1, 120 .reg_off = AO_RTC_ALT_CLK_CNTL1, 125 .reg_off = AO_RTC_ALT_CLK_CNTL0,
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H A D | gxbb-aoclk.c | 91 .reg_off = AO_RTC_ALT_CLK_CNTL0, 96 .reg_off = AO_RTC_ALT_CLK_CNTL0, 101 .reg_off = AO_RTC_ALT_CLK_CNTL1, 106 .reg_off = AO_RTC_ALT_CLK_CNTL1, 111 .reg_off = AO_RTC_ALT_CLK_CNTL0,
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/linux-master/drivers/pinctrl/ |
H A D | pinctrl-digicolor.c | 130 int bit_off, reg_off; local 133 dc_client_sel(group, ®_off, &bit_off); 135 reg = readb_relaxed(pmap->regs + reg_off); 138 writeb_relaxed(reg, pmap->regs + reg_off); 148 int bit_off, reg_off; local 151 dc_client_sel(offset, ®_off, &bit_off); 153 reg = readb_relaxed(pmap->regs + reg_off); 171 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); local 177 drive = readb_relaxed(pmap->regs + reg_off); 179 writeb_relaxed(drive, pmap->regs + reg_off); 191 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); local 210 int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION); local 222 int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION); local [all...] |
/linux-master/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_4_1_sdm670.h | 16 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 17 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 18 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 19 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 20 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
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H A D | dpu_3_0_msm8998.h | 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, 36 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 37 [DPU_CLK_CTRL_CURSOR1] = { .reg_off [all...] |
H A D | dpu_6_0_sm8250.h | 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 34 [DPU_CLK_CTRL_WB2] = { .reg_off [all...] |
H A D | dpu_8_1_sm8450.h | 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 35 [DPU_CLK_CTRL_REG_DMA] = { .reg_off [all...] |
H A D | dpu_7_0_sm8350.h | 25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off [all...] |
H A D | dpu_8_0_sc8280xp.h | 26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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H A D | dpu_6_2_sc7180.h | 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
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/linux-master/drivers/net/ethernet/marvell/octeon_ep_vf/ |
H A D | octep_vf_main.h | 305 #define octep_vf_write_csr(octep_vf_dev, reg_off, value) \ 306 writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off)) 308 #define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \ 309 writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off)) 311 #define octep_vf_read_csr(octep_vf_dev, reg_off) \ 312 readl((octep_vf_dev)->mmio.hw_addr + (reg_off)) 314 #define octep_vf_read_csr64(octep_vf_dev, reg_off) \ 315 readq((octep_vf_dev)->mmio.hw_addr + (reg_off))
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/linux-master/drivers/net/ethernet/marvell/octeon_ep/ |
H A D | octep_main.h | 336 #define octep_write_csr(octep_dev, reg_off, value) \ 337 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off)) 339 #define octep_write_csr64(octep_dev, reg_off, val64) \ 340 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off)) 342 #define octep_read_csr(octep_dev, reg_off) \ 343 readl((octep_dev)->mmio[0].hw_addr + (reg_off)) 345 #define octep_read_csr64(octep_dev, reg_off) \ 346 readq((octep_dev)->mmio[0].hw_addr + (reg_off))
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/linux-master/drivers/pinctrl/realtek/ |
H A D | pinctrl-rtd.c | 290 u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; local 307 reg_off = config_desc->reg_offset; 320 reg_off = config_desc->reg_offset; 332 reg_off = config_desc->reg_offset; 345 reg_off = config_desc->reg_offset; 358 reg_off = config_desc->reg_offset; 366 reg_off = config_desc->reg_offset; 400 reg_off = config_desc->reg_offset; 403 reg_off += 0x4; 418 reg_off [all...] |
/linux-master/sound/soc/tegra/ |
H A D | tegra210_mbdrc.c | 787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; local 790 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL, 791 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, 849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; local 852 reg_off + TEGRA210_MBDRC_IIR_CFG, 858 reg_off + TEGRA210_MBDRC_IN_ATTACK, 864 reg_off + TEGRA210_MBDRC_IN_RELEASE, 870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, 889 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, 906 reg_off [all...] |