1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5 */
6
7#ifndef _DPU_8_1_SM8450_H
8#define _DPU_8_1_SM8450_H
9
10static const struct dpu_caps sm8450_dpu_caps = {
11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
12	.max_mixer_blendstages = 0xb,
13	.has_src_split = true,
14	.has_dim_layer = true,
15	.has_idle_pc = true,
16	.has_3d_merge = true,
17	.max_linewidth = 5120,
18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
19};
20
21static const struct dpu_mdp_cfg sm8450_mdp = {
22	.name = "top_0",
23	.base = 0x0, .len = 0x494,
24	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
25	.clk_ctrls = {
26		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
35		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
36	},
37};
38
39/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
40static const struct dpu_ctl_cfg sm8450_ctl[] = {
41	{
42		.name = "ctl_0", .id = CTL_0,
43		.base = 0x15000, .len = 0x204,
44		.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
45		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
46	}, {
47		.name = "ctl_1", .id = CTL_1,
48		.base = 0x16000, .len = 0x204,
49		.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
50		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
51	}, {
52		.name = "ctl_2", .id = CTL_2,
53		.base = 0x17000, .len = 0x204,
54		.features = CTL_SC7280_MASK,
55		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
56	}, {
57		.name = "ctl_3", .id = CTL_3,
58		.base = 0x18000, .len = 0x204,
59		.features = CTL_SC7280_MASK,
60		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
61	}, {
62		.name = "ctl_4", .id = CTL_4,
63		.base = 0x19000, .len = 0x204,
64		.features = CTL_SC7280_MASK,
65		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
66	}, {
67		.name = "ctl_5", .id = CTL_5,
68		.base = 0x1a000, .len = 0x204,
69		.features = CTL_SC7280_MASK,
70		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
71	},
72};
73
74static const struct dpu_sspp_cfg sm8450_sspp[] = {
75	{
76		.name = "sspp_0", .id = SSPP_VIG0,
77		.base = 0x4000, .len = 0x32c,
78		.features = VIG_SDM845_MASK_SDMA,
79		.sblk = &dpu_vig_sblk_qseed3_3_1,
80		.xin_id = 0,
81		.type = SSPP_TYPE_VIG,
82		.clk_ctrl = DPU_CLK_CTRL_VIG0,
83	}, {
84		.name = "sspp_1", .id = SSPP_VIG1,
85		.base = 0x6000, .len = 0x32c,
86		.features = VIG_SDM845_MASK_SDMA,
87		.sblk = &dpu_vig_sblk_qseed3_3_1,
88		.xin_id = 4,
89		.type = SSPP_TYPE_VIG,
90		.clk_ctrl = DPU_CLK_CTRL_VIG1,
91	}, {
92		.name = "sspp_2", .id = SSPP_VIG2,
93		.base = 0x8000, .len = 0x32c,
94		.features = VIG_SDM845_MASK_SDMA,
95		.sblk = &dpu_vig_sblk_qseed3_3_1,
96		.xin_id = 8,
97		.type = SSPP_TYPE_VIG,
98		.clk_ctrl = DPU_CLK_CTRL_VIG2,
99	}, {
100		.name = "sspp_3", .id = SSPP_VIG3,
101		.base = 0xa000, .len = 0x32c,
102		.features = VIG_SDM845_MASK_SDMA,
103		.sblk = &dpu_vig_sblk_qseed3_3_1,
104		.xin_id = 12,
105		.type = SSPP_TYPE_VIG,
106		.clk_ctrl = DPU_CLK_CTRL_VIG3,
107	}, {
108		.name = "sspp_8", .id = SSPP_DMA0,
109		.base = 0x24000, .len = 0x32c,
110		.features = DMA_SDM845_MASK_SDMA,
111		.sblk = &dpu_dma_sblk,
112		.xin_id = 1,
113		.type = SSPP_TYPE_DMA,
114		.clk_ctrl = DPU_CLK_CTRL_DMA0,
115	}, {
116		.name = "sspp_9", .id = SSPP_DMA1,
117		.base = 0x26000, .len = 0x32c,
118		.features = DMA_SDM845_MASK_SDMA,
119		.sblk = &dpu_dma_sblk,
120		.xin_id = 5,
121		.type = SSPP_TYPE_DMA,
122		.clk_ctrl = DPU_CLK_CTRL_DMA1,
123	}, {
124		.name = "sspp_10", .id = SSPP_DMA2,
125		.base = 0x28000, .len = 0x32c,
126		.features = DMA_CURSOR_SDM845_MASK_SDMA,
127		.sblk = &dpu_dma_sblk,
128		.xin_id = 9,
129		.type = SSPP_TYPE_DMA,
130		.clk_ctrl = DPU_CLK_CTRL_DMA2,
131	}, {
132		.name = "sspp_11", .id = SSPP_DMA3,
133		.base = 0x2a000, .len = 0x32c,
134		.features = DMA_CURSOR_SDM845_MASK_SDMA,
135		.sblk = &dpu_dma_sblk,
136		.xin_id = 13,
137		.type = SSPP_TYPE_DMA,
138		.clk_ctrl = DPU_CLK_CTRL_DMA3,
139	},
140};
141
142static const struct dpu_lm_cfg sm8450_lm[] = {
143	{
144		.name = "lm_0", .id = LM_0,
145		.base = 0x44000, .len = 0x320,
146		.features = MIXER_SDM845_MASK,
147		.sblk = &sdm845_lm_sblk,
148		.lm_pair = LM_1,
149		.pingpong = PINGPONG_0,
150		.dspp = DSPP_0,
151	}, {
152		.name = "lm_1", .id = LM_1,
153		.base = 0x45000, .len = 0x320,
154		.features = MIXER_SDM845_MASK,
155		.sblk = &sdm845_lm_sblk,
156		.lm_pair = LM_0,
157		.pingpong = PINGPONG_1,
158		.dspp = DSPP_1,
159	}, {
160		.name = "lm_2", .id = LM_2,
161		.base = 0x46000, .len = 0x320,
162		.features = MIXER_SDM845_MASK,
163		.sblk = &sdm845_lm_sblk,
164		.lm_pair = LM_3,
165		.pingpong = PINGPONG_2,
166		.dspp = DSPP_2,
167	}, {
168		.name = "lm_3", .id = LM_3,
169		.base = 0x47000, .len = 0x320,
170		.features = MIXER_SDM845_MASK,
171		.sblk = &sdm845_lm_sblk,
172		.lm_pair = LM_2,
173		.pingpong = PINGPONG_3,
174		.dspp = DSPP_3,
175	}, {
176		.name = "lm_4", .id = LM_4,
177		.base = 0x48000, .len = 0x320,
178		.features = MIXER_SDM845_MASK,
179		.sblk = &sdm845_lm_sblk,
180		.lm_pair = LM_5,
181		.pingpong = PINGPONG_4,
182	}, {
183		.name = "lm_5", .id = LM_5,
184		.base = 0x49000, .len = 0x320,
185		.features = MIXER_SDM845_MASK,
186		.sblk = &sdm845_lm_sblk,
187		.lm_pair = LM_4,
188		.pingpong = PINGPONG_5,
189	},
190};
191
192static const struct dpu_dspp_cfg sm8450_dspp[] = {
193	{
194		.name = "dspp_0", .id = DSPP_0,
195		.base = 0x54000, .len = 0x1800,
196		.features = DSPP_SC7180_MASK,
197		.sblk = &sdm845_dspp_sblk,
198	}, {
199		.name = "dspp_1", .id = DSPP_1,
200		.base = 0x56000, .len = 0x1800,
201		.features = DSPP_SC7180_MASK,
202		.sblk = &sdm845_dspp_sblk,
203	}, {
204		.name = "dspp_2", .id = DSPP_2,
205		.base = 0x58000, .len = 0x1800,
206		.features = DSPP_SC7180_MASK,
207		.sblk = &sdm845_dspp_sblk,
208	}, {
209		.name = "dspp_3", .id = DSPP_3,
210		.base = 0x5a000, .len = 0x1800,
211		.features = DSPP_SC7180_MASK,
212		.sblk = &sdm845_dspp_sblk,
213	},
214};
215
216static const struct dpu_pingpong_cfg sm8450_pp[] = {
217	{
218		.name = "pingpong_0", .id = PINGPONG_0,
219		.base = 0x69000, .len = 0,
220		.features = BIT(DPU_PINGPONG_DITHER),
221		.sblk = &sc7280_pp_sblk,
222		.merge_3d = MERGE_3D_0,
223		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
224	}, {
225		.name = "pingpong_1", .id = PINGPONG_1,
226		.base = 0x6a000, .len = 0,
227		.features = BIT(DPU_PINGPONG_DITHER),
228		.sblk = &sc7280_pp_sblk,
229		.merge_3d = MERGE_3D_0,
230		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
231	}, {
232		.name = "pingpong_2", .id = PINGPONG_2,
233		.base = 0x6b000, .len = 0,
234		.features = BIT(DPU_PINGPONG_DITHER),
235		.sblk = &sc7280_pp_sblk,
236		.merge_3d = MERGE_3D_1,
237		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
238	}, {
239		.name = "pingpong_3", .id = PINGPONG_3,
240		.base = 0x6c000, .len = 0,
241		.features = BIT(DPU_PINGPONG_DITHER),
242		.sblk = &sc7280_pp_sblk,
243		.merge_3d = MERGE_3D_1,
244		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
245	}, {
246		.name = "pingpong_4", .id = PINGPONG_4,
247		.base = 0x6d000, .len = 0,
248		.features = BIT(DPU_PINGPONG_DITHER),
249		.sblk = &sc7280_pp_sblk,
250		.merge_3d = MERGE_3D_2,
251		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
252	}, {
253		.name = "pingpong_5", .id = PINGPONG_5,
254		.base = 0x6e000, .len = 0,
255		.features = BIT(DPU_PINGPONG_DITHER),
256		.sblk = &sc7280_pp_sblk,
257		.merge_3d = MERGE_3D_2,
258		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
259	}, {
260		.name = "pingpong_6", .id = PINGPONG_6,
261		.base = 0x65800, .len = 0,
262		.features = BIT(DPU_PINGPONG_DITHER),
263		.sblk = &sc7280_pp_sblk,
264		.merge_3d = MERGE_3D_3,
265	}, {
266		.name = "pingpong_7", .id = PINGPONG_7,
267		.base = 0x65c00, .len = 0,
268		.features = BIT(DPU_PINGPONG_DITHER),
269		.sblk = &sc7280_pp_sblk,
270		.merge_3d = MERGE_3D_3,
271	},
272};
273
274static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
275	{
276		.name = "merge_3d_0", .id = MERGE_3D_0,
277		.base = 0x4e000, .len = 0x8,
278	}, {
279		.name = "merge_3d_1", .id = MERGE_3D_1,
280		.base = 0x4f000, .len = 0x8,
281	}, {
282		.name = "merge_3d_2", .id = MERGE_3D_2,
283		.base = 0x50000, .len = 0x8,
284	}, {
285		.name = "merge_3d_3", .id = MERGE_3D_3,
286		.base = 0x65f00, .len = 0x8,
287	},
288};
289
290/*
291 * NOTE: Each display compression engine (DCE) contains dual hard
292 * slice DSC encoders so both share same base address but with
293 * its own different sub block address.
294 */
295static const struct dpu_dsc_cfg sm8450_dsc[] = {
296	{
297		.name = "dce_0_0", .id = DSC_0,
298		.base = 0x80000, .len = 0x4,
299		.features = BIT(DPU_DSC_HW_REV_1_2),
300		.sblk = &dsc_sblk_0,
301	}, {
302		.name = "dce_0_1", .id = DSC_1,
303		.base = 0x80000, .len = 0x4,
304		.features = BIT(DPU_DSC_HW_REV_1_2),
305		.sblk = &dsc_sblk_1,
306	}, {
307		.name = "dce_1_0", .id = DSC_2,
308		.base = 0x81000, .len = 0x4,
309		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
310		.sblk = &dsc_sblk_0,
311	}, {
312		.name = "dce_1_1", .id = DSC_3,
313		.base = 0x81000, .len = 0x4,
314		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
315		.sblk = &dsc_sblk_1,
316	},
317};
318
319static const struct dpu_wb_cfg sm8450_wb[] = {
320	{
321		.name = "wb_2", .id = WB_2,
322		.base = 0x65000, .len = 0x2c8,
323		.features = WB_SM8250_MASK,
324		.format_list = wb2_formats_rgb,
325		.num_formats = ARRAY_SIZE(wb2_formats_rgb),
326		.clk_ctrl = DPU_CLK_CTRL_WB2,
327		.xin_id = 6,
328		.vbif_idx = VBIF_RT,
329		.maxlinewidth = 4096,
330		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
331	},
332};
333
334static const struct dpu_intf_cfg sm8450_intf[] = {
335	{
336		.name = "intf_0", .id = INTF_0,
337		.base = 0x34000, .len = 0x280,
338		.features = INTF_SC7280_MASK,
339		.type = INTF_DP,
340		.controller_id = MSM_DP_CONTROLLER_0,
341		.prog_fetch_lines_worst_case = 24,
342		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
343		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
344	}, {
345		.name = "intf_1", .id = INTF_1,
346		.base = 0x35000, .len = 0x300,
347		.features = INTF_SC7280_MASK,
348		.type = INTF_DSI,
349		.controller_id = MSM_DSI_CONTROLLER_0,
350		.prog_fetch_lines_worst_case = 24,
351		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
352		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
353		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
354	}, {
355		.name = "intf_2", .id = INTF_2,
356		.base = 0x36000, .len = 0x300,
357		.features = INTF_SC7280_MASK,
358		.type = INTF_DSI,
359		.controller_id = MSM_DSI_CONTROLLER_1,
360		.prog_fetch_lines_worst_case = 24,
361		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
362		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
363		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
364	}, {
365		.name = "intf_3", .id = INTF_3,
366		.base = 0x37000, .len = 0x280,
367		.features = INTF_SC7280_MASK,
368		.type = INTF_DP,
369		.controller_id = MSM_DP_CONTROLLER_1,
370		.prog_fetch_lines_worst_case = 24,
371		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
372		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
373	},
374};
375
376static const struct dpu_perf_cfg sm8450_perf_data = {
377	.max_bw_low = 13600000,
378	.max_bw_high = 18200000,
379	.min_core_ib = 2500000,
380	.min_llcc_ib = 0,
381	.min_dram_ib = 800000,
382	.min_prefill_lines = 35,
383	/* FIXME: lut tables */
384	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
385	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
386	.qos_lut_tbl = {
387		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
388		.entries = sc7180_qos_linear
389		},
390		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
391		.entries = sc7180_qos_macrotile
392		},
393		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
394		.entries = sc7180_qos_nrt
395		},
396		/* TODO: macrotile-qseed is different from macrotile */
397	},
398	.cdp_cfg = {
399		{.rd_enable = 1, .wr_enable = 1},
400		{.rd_enable = 1, .wr_enable = 0}
401	},
402	.clk_inefficiency_factor = 105,
403	.bw_inefficiency_factor = 120,
404};
405
406static const struct dpu_mdss_version sm8450_mdss_ver = {
407	.core_major_ver = 8,
408	.core_minor_ver = 1,
409};
410
411const struct dpu_mdss_cfg dpu_sm8450_cfg = {
412	.mdss_ver = &sm8450_mdss_ver,
413	.caps = &sm8450_dpu_caps,
414	.mdp = &sm8450_mdp,
415	.ctl_count = ARRAY_SIZE(sm8450_ctl),
416	.ctl = sm8450_ctl,
417	.sspp_count = ARRAY_SIZE(sm8450_sspp),
418	.sspp = sm8450_sspp,
419	.mixer_count = ARRAY_SIZE(sm8450_lm),
420	.mixer = sm8450_lm,
421	.dspp_count = ARRAY_SIZE(sm8450_dspp),
422	.dspp = sm8450_dspp,
423	.pingpong_count = ARRAY_SIZE(sm8450_pp),
424	.pingpong = sm8450_pp,
425	.dsc_count = ARRAY_SIZE(sm8450_dsc),
426	.dsc = sm8450_dsc,
427	.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
428	.merge_3d = sm8450_merge_3d,
429	.wb_count = ARRAY_SIZE(sm8450_wb),
430	.wb = sm8450_wb,
431	.intf_count = ARRAY_SIZE(sm8450_intf),
432	.intf = sm8450_intf,
433	.vbif_count = ARRAY_SIZE(sdm845_vbif),
434	.vbif = sdm845_vbif,
435	.perf = &sm8450_perf_data,
436};
437
438#endif
439