1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Marvell Octeon EP (EndPoint) VF Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8#ifndef _OCTEP_VF_MAIN_H_ 9#define _OCTEP_VF_MAIN_H_ 10 11#include "octep_vf_tx.h" 12#include "octep_vf_rx.h" 13#include "octep_vf_mbox.h" 14 15#define OCTEP_VF_DRV_NAME "octeon_ep_vf" 16#define OCTEP_VF_DRV_STRING "Marvell Octeon EndPoint NIC VF Driver" 17 18#define OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203 //93xx VF 19#define OCTEP_PCI_DEVICE_ID_CNF95N_VF 0xB403 //95N VF 20#define OCTEP_PCI_DEVICE_ID_CN98_VF 0xB103 21#define OCTEP_PCI_DEVICE_ID_CN10KA_VF 0xB903 22#define OCTEP_PCI_DEVICE_ID_CNF10KA_VF 0xBA03 23#define OCTEP_PCI_DEVICE_ID_CNF10KB_VF 0xBC03 24#define OCTEP_PCI_DEVICE_ID_CN10KB_VF 0xBD03 25 26#define OCTEP_VF_MAX_QUEUES 63 27#define OCTEP_VF_MAX_IQ OCTEP_VF_MAX_QUEUES 28#define OCTEP_VF_MAX_OQ OCTEP_VF_MAX_QUEUES 29 30#define OCTEP_VF_MAX_MSIX_VECTORS OCTEP_VF_MAX_OQ 31 32#define OCTEP_VF_IQ_INTR_RESEND_BIT 59 33#define OCTEP_VF_OQ_INTR_RESEND_BIT 59 34 35#define IQ_INSTR_PENDING(iq) ({ typeof(iq) iq__ = (iq); \ 36 ((iq__)->host_write_index - (iq__)->flush_index) & \ 37 (iq__)->ring_size_mask; \ 38 }) 39#define IQ_INSTR_SPACE(iq) ({ typeof(iq) iq_ = (iq); \ 40 (iq_)->max_count - IQ_INSTR_PENDING(iq_); \ 41 }) 42 43/* PCI address space mapping information. 44 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 45 * Octeon gets mapped to different physical address spaces in 46 * the kernel. 47 */ 48struct octep_vf_mmio { 49 /* The physical address to which the PCI address space is mapped. */ 50 u8 __iomem *hw_addr; 51 52 /* Flag indicating the mapping was successful. */ 53 int mapped; 54}; 55 56struct octep_vf_hw_ops { 57 void (*setup_iq_regs)(struct octep_vf_device *oct, int q); 58 void (*setup_oq_regs)(struct octep_vf_device *oct, int q); 59 void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox); 60 61 irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector); 62 irqreturn_t (*ioq_intr_handler)(void *ioq_vector); 63 void (*reinit_regs)(struct octep_vf_device *oct); 64 u32 (*update_iq_read_idx)(struct octep_vf_iq *iq); 65 66 void (*enable_interrupts)(struct octep_vf_device *oct); 67 void (*disable_interrupts)(struct octep_vf_device *oct); 68 69 void (*enable_io_queues)(struct octep_vf_device *oct); 70 void (*disable_io_queues)(struct octep_vf_device *oct); 71 void (*enable_iq)(struct octep_vf_device *oct, int q); 72 void (*disable_iq)(struct octep_vf_device *oct, int q); 73 void (*enable_oq)(struct octep_vf_device *oct, int q); 74 void (*disable_oq)(struct octep_vf_device *oct, int q); 75 void (*reset_io_queues)(struct octep_vf_device *oct); 76 void (*dump_registers)(struct octep_vf_device *oct); 77}; 78 79/* Octeon mailbox data */ 80struct octep_vf_mbox_data { 81 /* Holds the offset of received data via mailbox. */ 82 u32 data_index; 83 84 /* Holds the received data via mailbox. */ 85 u8 recv_data[OCTEP_PFVF_MBOX_MAX_DATA_BUF_SIZE]; 86}; 87 88/* wrappers around work structs */ 89struct octep_vf_mbox_wk { 90 struct work_struct work; 91 void *ctxptr; 92}; 93 94/* Octeon device mailbox */ 95struct octep_vf_mbox { 96 /* A mutex to protect access to this q_mbox. */ 97 struct mutex lock; 98 99 u32 state; 100 101 /* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */ 102 u8 __iomem *mbox_int_reg; 103 104 /* SLI_PKT_PF_VF_MBOX_SIG(0) for PF, 105 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF. 106 */ 107 u8 __iomem *mbox_write_reg; 108 109 /* SLI_PKT_PF_VF_MBOX_SIG(1) for PF, 110 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF. 111 */ 112 u8 __iomem *mbox_read_reg; 113 114 /* Octeon mailbox data */ 115 struct octep_vf_mbox_data mbox_data; 116 117 /* Octeon mailbox work handler to process Mbox messages */ 118 struct octep_vf_mbox_wk wk; 119}; 120 121/* Tx/Rx queue vector per interrupt. */ 122struct octep_vf_ioq_vector { 123 char name[OCTEP_VF_MSIX_NAME_SIZE]; 124 struct napi_struct napi; 125 struct octep_vf_device *octep_vf_dev; 126 struct octep_vf_iq *iq; 127 struct octep_vf_oq *oq; 128 cpumask_t affinity_mask; 129}; 130 131/* Octeon hardware/firmware offload capability flags. */ 132#define OCTEP_VF_CAP_TX_CHECKSUM BIT(0) 133#define OCTEP_VF_CAP_RX_CHECKSUM BIT(1) 134#define OCTEP_VF_CAP_TSO BIT(2) 135 136/* Link modes */ 137enum octep_vf_link_mode_bit_indices { 138 OCTEP_VF_LINK_MODE_10GBASE_T = 0, 139 OCTEP_VF_LINK_MODE_10GBASE_R, 140 OCTEP_VF_LINK_MODE_10GBASE_CR, 141 OCTEP_VF_LINK_MODE_10GBASE_KR, 142 OCTEP_VF_LINK_MODE_10GBASE_LR, 143 OCTEP_VF_LINK_MODE_10GBASE_SR, 144 OCTEP_VF_LINK_MODE_25GBASE_CR, 145 OCTEP_VF_LINK_MODE_25GBASE_KR, 146 OCTEP_VF_LINK_MODE_25GBASE_SR, 147 OCTEP_VF_LINK_MODE_40GBASE_CR4, 148 OCTEP_VF_LINK_MODE_40GBASE_KR4, 149 OCTEP_VF_LINK_MODE_40GBASE_LR4, 150 OCTEP_VF_LINK_MODE_40GBASE_SR4, 151 OCTEP_VF_LINK_MODE_50GBASE_CR2, 152 OCTEP_VF_LINK_MODE_50GBASE_KR2, 153 OCTEP_VF_LINK_MODE_50GBASE_SR2, 154 OCTEP_VF_LINK_MODE_50GBASE_CR, 155 OCTEP_VF_LINK_MODE_50GBASE_KR, 156 OCTEP_VF_LINK_MODE_50GBASE_LR, 157 OCTEP_VF_LINK_MODE_50GBASE_SR, 158 OCTEP_VF_LINK_MODE_100GBASE_CR4, 159 OCTEP_VF_LINK_MODE_100GBASE_KR4, 160 OCTEP_VF_LINK_MODE_100GBASE_LR4, 161 OCTEP_VF_LINK_MODE_100GBASE_SR4, 162 OCTEP_VF_LINK_MODE_NBITS 163}; 164 165/* Hardware interface link state information. */ 166struct octep_vf_iface_link_info { 167 /* Bitmap of Supported link speeds/modes. */ 168 u64 supported_modes; 169 170 /* Bitmap of Advertised link speeds/modes. */ 171 u64 advertised_modes; 172 173 /* Negotiated link speed in Mbps. */ 174 u32 speed; 175 176 /* MTU */ 177 u16 mtu; 178 179 /* Autonegotiation state. */ 180#define OCTEP_VF_LINK_MODE_AUTONEG_SUPPORTED BIT(0) 181#define OCTEP_VF_LINK_MODE_AUTONEG_ADVERTISED BIT(1) 182 u8 autoneg; 183 184 /* Pause frames setting. */ 185#define OCTEP_VF_LINK_MODE_PAUSE_SUPPORTED BIT(0) 186#define OCTEP_VF_LINK_MODE_PAUSE_ADVERTISED BIT(1) 187 u8 pause; 188 189 /* Admin state of the link (ifconfig <iface> up/down */ 190 u8 admin_up; 191 192 /* Operational state of the link: physical link is up down */ 193 u8 oper_up; 194}; 195 196/* Hardware interface stats information. */ 197struct octep_vf_iface_rxtx_stats { 198 /* Hardware Interface Rx statistics */ 199 struct octep_vf_iface_rx_stats iface_rx_stats; 200 201 /* Hardware Interface Tx statistics */ 202 struct octep_vf_iface_tx_stats iface_tx_stats; 203}; 204 205struct octep_vf_fw_info { 206 /* pkind value to be used in every Tx hardware descriptor */ 207 u8 pkind; 208 /* front size data */ 209 u8 fsz; 210 /* supported rx offloads OCTEP_VF_RX_OFFLOAD_* */ 211 u16 rx_ol_flags; 212 /* supported tx offloads OCTEP_VF_TX_OFFLOAD_* */ 213 u16 tx_ol_flags; 214}; 215 216/* The Octeon device specific private data structure. 217 * Each Octeon device has this structure to represent all its components. 218 */ 219struct octep_vf_device { 220 struct octep_vf_config *conf; 221 222 /* Octeon Chip type. */ 223 u16 chip_id; 224 u16 rev_id; 225 226 /* Device capabilities enabled */ 227 u64 caps_enabled; 228 /* Device capabilities supported */ 229 u64 caps_supported; 230 231 /* Pointer to basic Linux device */ 232 struct device *dev; 233 /* Linux PCI device pointer */ 234 struct pci_dev *pdev; 235 /* Netdev corresponding to the Octeon device */ 236 struct net_device *netdev; 237 238 /* memory mapped io range */ 239 struct octep_vf_mmio mmio; 240 241 /* MAC address */ 242 u8 mac_addr[ETH_ALEN]; 243 244 /* Tx queues (IQ: Instruction Queue) */ 245 u16 num_iqs; 246 /* Pointers to Octeon Tx queues */ 247 struct octep_vf_iq *iq[OCTEP_VF_MAX_IQ]; 248 249 /* Rx queues (OQ: Output Queue) */ 250 u16 num_oqs; 251 /* Pointers to Octeon Rx queues */ 252 struct octep_vf_oq *oq[OCTEP_VF_MAX_OQ]; 253 254 /* Hardware port number of the PCIe interface */ 255 u16 pcie_port; 256 257 /* Hardware operations */ 258 struct octep_vf_hw_ops hw_ops; 259 260 /* IRQ info */ 261 u16 num_irqs; 262 u16 num_non_ioq_irqs; 263 char *non_ioq_irq_names; 264 struct msix_entry *msix_entries; 265 /* IOq information of it's corresponding MSI-X interrupt. */ 266 struct octep_vf_ioq_vector *ioq_vector[OCTEP_VF_MAX_QUEUES]; 267 268 /* Hardware Interface Tx statistics */ 269 struct octep_vf_iface_tx_stats iface_tx_stats; 270 /* Hardware Interface Rx statistics */ 271 struct octep_vf_iface_rx_stats iface_rx_stats; 272 273 /* Hardware Interface Link info like supported modes, aneg support */ 274 struct octep_vf_iface_link_info link_info; 275 276 /* Mailbox to talk to VFs */ 277 struct octep_vf_mbox *mbox; 278 279 /* Work entry to handle Tx timeout */ 280 struct work_struct tx_timeout_task; 281 282 /* offset for iface stats */ 283 u32 ctrl_mbox_ifstats_offset; 284 285 /* Negotiated Mbox version */ 286 u32 mbox_neg_ver; 287 288 /* firmware info */ 289 struct octep_vf_fw_info fw_info; 290}; 291 292static inline u16 OCTEP_VF_MAJOR_REV(struct octep_vf_device *oct) 293{ 294 u16 rev = (oct->rev_id & 0xC) >> 2; 295 296 return (rev == 0) ? 1 : rev; 297} 298 299static inline u16 OCTEP_VF_MINOR_REV(struct octep_vf_device *oct) 300{ 301 return (oct->rev_id & 0x3); 302} 303 304/* Octeon CSR read/write access APIs */ 305#define octep_vf_write_csr(octep_vf_dev, reg_off, value) \ 306 writel(value, (octep_vf_dev)->mmio.hw_addr + (reg_off)) 307 308#define octep_vf_write_csr64(octep_vf_dev, reg_off, val64) \ 309 writeq(val64, (octep_vf_dev)->mmio.hw_addr + (reg_off)) 310 311#define octep_vf_read_csr(octep_vf_dev, reg_off) \ 312 readl((octep_vf_dev)->mmio.hw_addr + (reg_off)) 313 314#define octep_vf_read_csr64(octep_vf_dev, reg_off) \ 315 readq((octep_vf_dev)->mmio.hw_addr + (reg_off)) 316 317extern struct workqueue_struct *octep_vf_wq; 318 319int octep_vf_device_setup(struct octep_vf_device *oct); 320int octep_vf_setup_iqs(struct octep_vf_device *oct); 321void octep_vf_free_iqs(struct octep_vf_device *oct); 322void octep_vf_clean_iqs(struct octep_vf_device *oct); 323int octep_vf_setup_oqs(struct octep_vf_device *oct); 324void octep_vf_free_oqs(struct octep_vf_device *oct); 325void octep_vf_oq_dbell_init(struct octep_vf_device *oct); 326void octep_vf_device_setup_cn93(struct octep_vf_device *oct); 327void octep_vf_device_setup_cnxk(struct octep_vf_device *oct); 328int octep_vf_iq_process_completions(struct octep_vf_iq *iq, u16 budget); 329int octep_vf_oq_process_rx(struct octep_vf_oq *oq, int budget); 330void octep_vf_set_ethtool_ops(struct net_device *netdev); 331int octep_vf_get_link_info(struct octep_vf_device *oct); 332int octep_vf_get_if_stats(struct octep_vf_device *oct); 333void octep_vf_mbox_work(struct work_struct *work); 334#endif /* _OCTEP_VF_MAIN_H_ */ 335