1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5 */
6
7#ifndef _DPU_3_0_MSM8998_H
8#define _DPU_3_0_MSM8998_H
9
10static const struct dpu_caps msm8998_dpu_caps = {
11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
12	.max_mixer_blendstages = 0x7,
13	.has_src_split = true,
14	.has_dim_layer = true,
15	.has_idle_pc = true,
16	.has_3d_merge = true,
17	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
19	.max_hdeci_exp = MAX_HORZ_DECIMATION,
20	.max_vdeci_exp = MAX_VERT_DECIMATION,
21};
22
23static const struct dpu_mdp_cfg msm8998_mdp = {
24	.name = "top_0",
25	.base = 0x0, .len = 0x458,
26	.features = BIT(DPU_MDP_VSYNC_SEL),
27	.clk_ctrls = {
28		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
29		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
30		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
31		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
32		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
34		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
35		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
36		[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
37		[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 },
38	},
39};
40
41static const struct dpu_ctl_cfg msm8998_ctl[] = {
42	{
43		.name = "ctl_0", .id = CTL_0,
44		.base = 0x1000, .len = 0x94,
45		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
46		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
47	}, {
48		.name = "ctl_1", .id = CTL_1,
49		.base = 0x1200, .len = 0x94,
50		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
51	}, {
52		.name = "ctl_2", .id = CTL_2,
53		.base = 0x1400, .len = 0x94,
54		.features = BIT(DPU_CTL_SPLIT_DISPLAY),
55		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
56	}, {
57		.name = "ctl_3", .id = CTL_3,
58		.base = 0x1600, .len = 0x94,
59		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
60	}, {
61		.name = "ctl_4", .id = CTL_4,
62		.base = 0x1800, .len = 0x94,
63		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
64	},
65};
66
67static const struct dpu_sspp_cfg msm8998_sspp[] = {
68	{
69		.name = "sspp_0", .id = SSPP_VIG0,
70		.base = 0x4000, .len = 0x1ac,
71		.features = VIG_MSM8998_MASK,
72		.sblk = &dpu_vig_sblk_qseed3_1_2,
73		.xin_id = 0,
74		.type = SSPP_TYPE_VIG,
75		.clk_ctrl = DPU_CLK_CTRL_VIG0,
76	}, {
77		.name = "sspp_1", .id = SSPP_VIG1,
78		.base = 0x6000, .len = 0x1ac,
79		.features = VIG_MSM8998_MASK,
80		.sblk = &dpu_vig_sblk_qseed3_1_2,
81		.xin_id = 4,
82		.type = SSPP_TYPE_VIG,
83		.clk_ctrl = DPU_CLK_CTRL_VIG1,
84	}, {
85		.name = "sspp_2", .id = SSPP_VIG2,
86		.base = 0x8000, .len = 0x1ac,
87		.features = VIG_MSM8998_MASK,
88		.sblk = &dpu_vig_sblk_qseed3_1_2,
89		.xin_id = 8,
90		.type = SSPP_TYPE_VIG,
91		.clk_ctrl = DPU_CLK_CTRL_VIG2,
92	}, {
93		.name = "sspp_3", .id = SSPP_VIG3,
94		.base = 0xa000, .len = 0x1ac,
95		.features = VIG_MSM8998_MASK,
96		.sblk = &dpu_vig_sblk_qseed3_1_2,
97		.xin_id = 12,
98		.type = SSPP_TYPE_VIG,
99		.clk_ctrl = DPU_CLK_CTRL_VIG3,
100	}, {
101		.name = "sspp_8", .id = SSPP_DMA0,
102		.base = 0x24000, .len = 0x1ac,
103		.features = DMA_MSM8998_MASK,
104		.sblk = &dpu_dma_sblk,
105		.xin_id = 1,
106		.type = SSPP_TYPE_DMA,
107		.clk_ctrl = DPU_CLK_CTRL_DMA0,
108	}, {
109		.name = "sspp_9", .id = SSPP_DMA1,
110		.base = 0x26000, .len = 0x1ac,
111		.features = DMA_MSM8998_MASK,
112		.sblk = &dpu_dma_sblk,
113		.xin_id = 5,
114		.type = SSPP_TYPE_DMA,
115		.clk_ctrl = DPU_CLK_CTRL_DMA1,
116	}, {
117		.name = "sspp_10", .id = SSPP_DMA2,
118		.base = 0x28000, .len = 0x1ac,
119		.features = DMA_CURSOR_MSM8998_MASK,
120		.sblk = &dpu_dma_sblk,
121		.xin_id = 9,
122		.type = SSPP_TYPE_DMA,
123		.clk_ctrl = DPU_CLK_CTRL_DMA2,
124	}, {
125		.name = "sspp_11", .id = SSPP_DMA3,
126		.base = 0x2a000, .len = 0x1ac,
127		.features = DMA_CURSOR_MSM8998_MASK,
128		.sblk = &dpu_dma_sblk,
129		.xin_id = 13,
130		.type = SSPP_TYPE_DMA,
131		.clk_ctrl = DPU_CLK_CTRL_DMA3,
132	},
133};
134
135static const struct dpu_lm_cfg msm8998_lm[] = {
136	{
137		.name = "lm_0", .id = LM_0,
138		.base = 0x44000, .len = 0x320,
139		.features = MIXER_MSM8998_MASK,
140		.sblk = &msm8998_lm_sblk,
141		.lm_pair = LM_1,
142		.pingpong = PINGPONG_0,
143		.dspp = DSPP_0,
144	}, {
145		.name = "lm_1", .id = LM_1,
146		.base = 0x45000, .len = 0x320,
147		.features = MIXER_MSM8998_MASK,
148		.sblk = &msm8998_lm_sblk,
149		.lm_pair = LM_0,
150		.pingpong = PINGPONG_1,
151		.dspp = DSPP_1,
152	}, {
153		.name = "lm_2", .id = LM_2,
154		.base = 0x46000, .len = 0x320,
155		.features = MIXER_MSM8998_MASK,
156		.sblk = &msm8998_lm_sblk,
157		.lm_pair = LM_5,
158		.pingpong = PINGPONG_2,
159	}, {
160		.name = "lm_3", .id = LM_3,
161		.base = 0x47000, .len = 0x320,
162		.features = MIXER_MSM8998_MASK,
163		.sblk = &msm8998_lm_sblk,
164		.pingpong = PINGPONG_NONE,
165	}, {
166		.name = "lm_4", .id = LM_4,
167		.base = 0x48000, .len = 0x320,
168		.features = MIXER_MSM8998_MASK,
169		.sblk = &msm8998_lm_sblk,
170		.pingpong = PINGPONG_NONE,
171	}, {
172		.name = "lm_5", .id = LM_5,
173		.base = 0x49000, .len = 0x320,
174		.features = MIXER_MSM8998_MASK,
175		.sblk = &msm8998_lm_sblk,
176		.lm_pair = LM_2,
177		.pingpong = PINGPONG_3,
178	},
179};
180
181static const struct dpu_pingpong_cfg msm8998_pp[] = {
182	{
183		.name = "pingpong_0", .id = PINGPONG_0,
184		.base = 0x70000, .len = 0xd4,
185		.features = PINGPONG_SDM845_TE2_MASK,
186		.sblk = &sdm845_pp_sblk_te,
187		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
188		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
189	}, {
190		.name = "pingpong_1", .id = PINGPONG_1,
191		.base = 0x70800, .len = 0xd4,
192		.features = PINGPONG_SDM845_TE2_MASK,
193		.sblk = &sdm845_pp_sblk_te,
194		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
195		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
196	}, {
197		.name = "pingpong_2", .id = PINGPONG_2,
198		.base = 0x71000, .len = 0xd4,
199		.features = PINGPONG_SDM845_MASK,
200		.sblk = &sdm845_pp_sblk,
201		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
202		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
203	}, {
204		.name = "pingpong_3", .id = PINGPONG_3,
205		.base = 0x71800, .len = 0xd4,
206		.features = PINGPONG_SDM845_MASK,
207		.sblk = &sdm845_pp_sblk,
208		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
209		.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
210	},
211};
212
213static const struct dpu_dsc_cfg msm8998_dsc[] = {
214	{
215		.name = "dsc_0", .id = DSC_0,
216		.base = 0x80000, .len = 0x140,
217	}, {
218		.name = "dsc_1", .id = DSC_1,
219		.base = 0x80400, .len = 0x140,
220	},
221};
222
223static const struct dpu_dspp_cfg msm8998_dspp[] = {
224	{
225		.name = "dspp_0", .id = DSPP_0,
226		.base = 0x54000, .len = 0x1800,
227		.features = DSPP_SC7180_MASK,
228		.sblk = &msm8998_dspp_sblk,
229	}, {
230		.name = "dspp_1", .id = DSPP_1,
231		.base = 0x56000, .len = 0x1800,
232		.features = DSPP_SC7180_MASK,
233		.sblk = &msm8998_dspp_sblk,
234	},
235};
236
237static const struct dpu_intf_cfg msm8998_intf[] = {
238	{
239		.name = "intf_0", .id = INTF_0,
240		.base = 0x6a000, .len = 0x280,
241		.type = INTF_DP,
242		.controller_id = MSM_DP_CONTROLLER_0,
243		.prog_fetch_lines_worst_case = 21,
244		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
245		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
246	}, {
247		.name = "intf_1", .id = INTF_1,
248		.base = 0x6a800, .len = 0x280,
249		.type = INTF_DSI,
250		.controller_id = MSM_DSI_CONTROLLER_0,
251		.prog_fetch_lines_worst_case = 21,
252		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
253		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
254	}, {
255		.name = "intf_2", .id = INTF_2,
256		.base = 0x6b000, .len = 0x280,
257		.type = INTF_DSI,
258		.controller_id = MSM_DSI_CONTROLLER_1,
259		.prog_fetch_lines_worst_case = 21,
260		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
261		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
262	}, {
263		.name = "intf_3", .id = INTF_3,
264		.base = 0x6b800, .len = 0x280,
265		.type = INTF_HDMI,
266		.prog_fetch_lines_worst_case = 21,
267		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
268		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
269	},
270};
271
272static const struct dpu_perf_cfg msm8998_perf_data = {
273	.max_bw_low = 6700000,
274	.max_bw_high = 6700000,
275	.min_core_ib = 2400000,
276	.min_llcc_ib = 800000,
277	.min_dram_ib = 800000,
278	.undersized_prefill_lines = 2,
279	.xtra_prefill_lines = 2,
280	.dest_scale_prefill_lines = 3,
281	.macrotile_prefill_lines = 4,
282	.yuv_nv12_prefill_lines = 8,
283	.linear_prefill_lines = 1,
284	.downscaling_prefill_lines = 1,
285	.amortizable_threshold = 25,
286	.min_prefill_lines = 25,
287	.danger_lut_tbl = {0xf, 0xffff, 0x0},
288	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
289	.qos_lut_tbl = {
290		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
291		.entries = msm8998_qos_linear
292		},
293		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
294		.entries = msm8998_qos_macrotile
295		},
296		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
297		.entries = msm8998_qos_nrt
298		},
299	},
300	.cdp_cfg = {
301		{.rd_enable = 1, .wr_enable = 1},
302		{.rd_enable = 1, .wr_enable = 0}
303	},
304	.clk_inefficiency_factor = 200,
305	.bw_inefficiency_factor = 120,
306};
307
308static const struct dpu_mdss_version msm8998_mdss_ver = {
309	.core_major_ver = 3,
310	.core_minor_ver = 0,
311};
312
313const struct dpu_mdss_cfg dpu_msm8998_cfg = {
314	.mdss_ver = &msm8998_mdss_ver,
315	.caps = &msm8998_dpu_caps,
316	.mdp = &msm8998_mdp,
317	.ctl_count = ARRAY_SIZE(msm8998_ctl),
318	.ctl = msm8998_ctl,
319	.sspp_count = ARRAY_SIZE(msm8998_sspp),
320	.sspp = msm8998_sspp,
321	.mixer_count = ARRAY_SIZE(msm8998_lm),
322	.mixer = msm8998_lm,
323	.dspp_count = ARRAY_SIZE(msm8998_dspp),
324	.dspp = msm8998_dspp,
325	.pingpong_count = ARRAY_SIZE(msm8998_pp),
326	.pingpong = msm8998_pp,
327	.dsc_count = ARRAY_SIZE(msm8998_dsc),
328	.dsc = msm8998_dsc,
329	.intf_count = ARRAY_SIZE(msm8998_intf),
330	.intf = msm8998_intf,
331	.vbif_count = ARRAY_SIZE(msm8998_vbif),
332	.vbif = msm8998_vbif,
333	.perf = &msm8998_perf_data,
334};
335
336#endif
337