1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5 */
6
7#ifndef _DPU_7_0_SM8350_H
8#define _DPU_7_0_SM8350_H
9
10static const struct dpu_caps sm8350_dpu_caps = {
11	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
12	.max_mixer_blendstages = 0xb,
13	.has_src_split = true,
14	.has_dim_layer = true,
15	.has_idle_pc = true,
16	.has_3d_merge = true,
17	.max_linewidth = 4096,
18	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
19};
20
21static const struct dpu_mdp_cfg sm8350_mdp = {
22	.name = "top_0",
23	.base = 0x0, .len = 0x494,
24	.clk_ctrls = {
25		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33		[DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
35	},
36};
37
38/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
39static const struct dpu_ctl_cfg sm8350_ctl[] = {
40	{
41		.name = "ctl_0", .id = CTL_0,
42		.base = 0x15000, .len = 0x1e8,
43		.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
44		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
45	}, {
46		.name = "ctl_1", .id = CTL_1,
47		.base = 0x16000, .len = 0x1e8,
48		.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
49		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
50	}, {
51		.name = "ctl_2", .id = CTL_2,
52		.base = 0x17000, .len = 0x1e8,
53		.features = CTL_SC7280_MASK,
54		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
55	}, {
56		.name = "ctl_3", .id = CTL_3,
57		.base = 0x18000, .len = 0x1e8,
58		.features = CTL_SC7280_MASK,
59		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
60	}, {
61		.name = "ctl_4", .id = CTL_4,
62		.base = 0x19000, .len = 0x1e8,
63		.features = CTL_SC7280_MASK,
64		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
65	}, {
66		.name = "ctl_5", .id = CTL_5,
67		.base = 0x1a000, .len = 0x1e8,
68		.features = CTL_SC7280_MASK,
69		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
70	},
71};
72
73static const struct dpu_sspp_cfg sm8350_sspp[] = {
74	{
75		.name = "sspp_0", .id = SSPP_VIG0,
76		.base = 0x4000, .len = 0x1f8,
77		.features = VIG_SDM845_MASK_SDMA,
78		.sblk = &dpu_vig_sblk_qseed3_3_0,
79		.xin_id = 0,
80		.type = SSPP_TYPE_VIG,
81		.clk_ctrl = DPU_CLK_CTRL_VIG0,
82	}, {
83		.name = "sspp_1", .id = SSPP_VIG1,
84		.base = 0x6000, .len = 0x1f8,
85		.features = VIG_SDM845_MASK_SDMA,
86		.sblk = &dpu_vig_sblk_qseed3_3_0,
87		.xin_id = 4,
88		.type = SSPP_TYPE_VIG,
89		.clk_ctrl = DPU_CLK_CTRL_VIG1,
90	}, {
91		.name = "sspp_2", .id = SSPP_VIG2,
92		.base = 0x8000, .len = 0x1f8,
93		.features = VIG_SDM845_MASK_SDMA,
94		.sblk = &dpu_vig_sblk_qseed3_3_0,
95		.xin_id = 8,
96		.type = SSPP_TYPE_VIG,
97		.clk_ctrl = DPU_CLK_CTRL_VIG2,
98	}, {
99		.name = "sspp_3", .id = SSPP_VIG3,
100		.base = 0xa000, .len = 0x1f8,
101		.features = VIG_SDM845_MASK_SDMA,
102		.sblk = &dpu_vig_sblk_qseed3_3_0,
103		.xin_id = 12,
104		.type = SSPP_TYPE_VIG,
105		.clk_ctrl = DPU_CLK_CTRL_VIG3,
106	}, {
107		.name = "sspp_8", .id = SSPP_DMA0,
108		.base = 0x24000, .len = 0x1f8,
109		.features = DMA_SDM845_MASK_SDMA,
110		.sblk = &dpu_dma_sblk,
111		.xin_id = 1,
112		.type = SSPP_TYPE_DMA,
113		.clk_ctrl = DPU_CLK_CTRL_DMA0,
114	}, {
115		.name = "sspp_9", .id = SSPP_DMA1,
116		.base = 0x26000, .len = 0x1f8,
117		.features = DMA_SDM845_MASK_SDMA,
118		.sblk = &dpu_dma_sblk,
119		.xin_id = 5,
120		.type = SSPP_TYPE_DMA,
121		.clk_ctrl = DPU_CLK_CTRL_DMA1,
122	}, {
123		.name = "sspp_10", .id = SSPP_DMA2,
124		.base = 0x28000, .len = 0x1f8,
125		.features = DMA_CURSOR_SDM845_MASK_SDMA,
126		.sblk = &dpu_dma_sblk,
127		.xin_id = 9,
128		.type = SSPP_TYPE_DMA,
129		.clk_ctrl = DPU_CLK_CTRL_DMA2,
130	}, {
131		.name = "sspp_11", .id = SSPP_DMA3,
132		.base = 0x2a000, .len = 0x1f8,
133		.features = DMA_CURSOR_SDM845_MASK_SDMA,
134		.sblk = &dpu_dma_sblk,
135		.xin_id = 13,
136		.type = SSPP_TYPE_DMA,
137		.clk_ctrl = DPU_CLK_CTRL_DMA3,
138	},
139};
140
141static const struct dpu_lm_cfg sm8350_lm[] = {
142	{
143		.name = "lm_0", .id = LM_0,
144		.base = 0x44000, .len = 0x320,
145		.features = MIXER_SDM845_MASK,
146		.sblk = &sdm845_lm_sblk,
147		.lm_pair = LM_1,
148		.pingpong = PINGPONG_0,
149		.dspp = DSPP_0,
150	}, {
151		.name = "lm_1", .id = LM_1,
152		.base = 0x45000, .len = 0x320,
153		.features = MIXER_SDM845_MASK,
154		.sblk = &sdm845_lm_sblk,
155		.lm_pair = LM_0,
156		.pingpong = PINGPONG_1,
157		.dspp = DSPP_1,
158	}, {
159		.name = "lm_2", .id = LM_2,
160		.base = 0x46000, .len = 0x320,
161		.features = MIXER_SDM845_MASK,
162		.sblk = &sdm845_lm_sblk,
163		.lm_pair = LM_3,
164		.pingpong = PINGPONG_2,
165	}, {
166		.name = "lm_3", .id = LM_3,
167		.base = 0x47000, .len = 0x320,
168		.features = MIXER_SDM845_MASK,
169		.sblk = &sdm845_lm_sblk,
170		.lm_pair = LM_2,
171		.pingpong = PINGPONG_3,
172	}, {
173		.name = "lm_4", .id = LM_4,
174		.base = 0x48000, .len = 0x320,
175		.features = MIXER_SDM845_MASK,
176		.sblk = &sdm845_lm_sblk,
177		.lm_pair = LM_5,
178		.pingpong = PINGPONG_4,
179	}, {
180		.name = "lm_5", .id = LM_5,
181		.base = 0x49000, .len = 0x320,
182		.features = MIXER_SDM845_MASK,
183		.sblk = &sdm845_lm_sblk,
184		.lm_pair = LM_4,
185		.pingpong = PINGPONG_5,
186	},
187};
188
189static const struct dpu_dspp_cfg sm8350_dspp[] = {
190	{
191		.name = "dspp_0", .id = DSPP_0,
192		.base = 0x54000, .len = 0x1800,
193		.features = DSPP_SC7180_MASK,
194		.sblk = &sdm845_dspp_sblk,
195	}, {
196		.name = "dspp_1", .id = DSPP_1,
197		.base = 0x56000, .len = 0x1800,
198		.features = DSPP_SC7180_MASK,
199		.sblk = &sdm845_dspp_sblk,
200	}, {
201		.name = "dspp_2", .id = DSPP_2,
202		.base = 0x58000, .len = 0x1800,
203		.features = DSPP_SC7180_MASK,
204		.sblk = &sdm845_dspp_sblk,
205	}, {
206		.name = "dspp_3", .id = DSPP_3,
207		.base = 0x5a000, .len = 0x1800,
208		.features = DSPP_SC7180_MASK,
209		.sblk = &sdm845_dspp_sblk,
210	},
211};
212
213static const struct dpu_pingpong_cfg sm8350_pp[] = {
214	{
215		.name = "pingpong_0", .id = PINGPONG_0,
216		.base = 0x69000, .len = 0,
217		.features = BIT(DPU_PINGPONG_DITHER),
218		.sblk = &sc7280_pp_sblk,
219		.merge_3d = MERGE_3D_0,
220		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
221	}, {
222		.name = "pingpong_1", .id = PINGPONG_1,
223		.base = 0x6a000, .len = 0,
224		.features = BIT(DPU_PINGPONG_DITHER),
225		.sblk = &sc7280_pp_sblk,
226		.merge_3d = MERGE_3D_0,
227		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
228	}, {
229		.name = "pingpong_2", .id = PINGPONG_2,
230		.base = 0x6b000, .len = 0,
231		.features = BIT(DPU_PINGPONG_DITHER),
232		.sblk = &sc7280_pp_sblk,
233		.merge_3d = MERGE_3D_1,
234		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
235	}, {
236		.name = "pingpong_3", .id = PINGPONG_3,
237		.base = 0x6c000, .len = 0,
238		.features = BIT(DPU_PINGPONG_DITHER),
239		.sblk = &sc7280_pp_sblk,
240		.merge_3d = MERGE_3D_1,
241		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
242	}, {
243		.name = "pingpong_4", .id = PINGPONG_4,
244		.base = 0x6d000, .len = 0,
245		.features = BIT(DPU_PINGPONG_DITHER),
246		.sblk = &sc7280_pp_sblk,
247		.merge_3d = MERGE_3D_2,
248		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
249	}, {
250		.name = "pingpong_5", .id = PINGPONG_5,
251		.base = 0x6e000, .len = 0,
252		.features = BIT(DPU_PINGPONG_DITHER),
253		.sblk = &sc7280_pp_sblk,
254		.merge_3d = MERGE_3D_2,
255		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
256	},
257};
258
259static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
260	{
261		.name = "merge_3d_0", .id = MERGE_3D_0,
262		.base = 0x4e000, .len = 0x8,
263	}, {
264		.name = "merge_3d_1", .id = MERGE_3D_1,
265		.base = 0x4f000, .len = 0x8,
266	}, {
267		.name = "merge_3d_2", .id = MERGE_3D_2,
268		.base = 0x50000, .len = 0x8,
269	},
270};
271
272/*
273 * NOTE: Each display compression engine (DCE) contains dual hard
274 * slice DSC encoders so both share same base address but with
275 * its own different sub block address.
276 */
277static const struct dpu_dsc_cfg sm8350_dsc[] = {
278	{
279		.name = "dce_0_0", .id = DSC_0,
280		.base = 0x80000, .len = 0x4,
281		.features = BIT(DPU_DSC_HW_REV_1_2),
282		.sblk = &dsc_sblk_0,
283	}, {
284		.name = "dce_0_1", .id = DSC_1,
285		.base = 0x80000, .len = 0x4,
286		.features = BIT(DPU_DSC_HW_REV_1_2),
287		.sblk = &dsc_sblk_1,
288	}, {
289		.name = "dce_1_0", .id = DSC_2,
290		.base = 0x81000, .len = 0x4,
291		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
292		.sblk = &dsc_sblk_0,
293	}, {
294		.name = "dce_1_1", .id = DSC_3,
295		.base = 0x81000, .len = 0x4,
296		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
297		.sblk = &dsc_sblk_1,
298	},
299};
300
301static const struct dpu_wb_cfg sm8350_wb[] = {
302	{
303		.name = "wb_2", .id = WB_2,
304		.base = 0x65000, .len = 0x2c8,
305		.features = WB_SM8250_MASK,
306		.format_list = wb2_formats_rgb,
307		.num_formats = ARRAY_SIZE(wb2_formats_rgb),
308		.clk_ctrl = DPU_CLK_CTRL_WB2,
309		.xin_id = 6,
310		.vbif_idx = VBIF_RT,
311		.maxlinewidth = 4096,
312		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
313	},
314};
315
316static const struct dpu_intf_cfg sm8350_intf[] = {
317	{
318		.name = "intf_0", .id = INTF_0,
319		.base = 0x34000, .len = 0x280,
320		.features = INTF_SC7280_MASK,
321		.type = INTF_DP,
322		.controller_id = MSM_DP_CONTROLLER_0,
323		.prog_fetch_lines_worst_case = 24,
324		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
325		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
326	}, {
327		.name = "intf_1", .id = INTF_1,
328		.base = 0x35000, .len = 0x2c4,
329		.features = INTF_SC7280_MASK,
330		.type = INTF_DSI,
331		.controller_id = MSM_DSI_CONTROLLER_0,
332		.prog_fetch_lines_worst_case = 24,
333		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
334		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
335		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
336	}, {
337		.name = "intf_2", .id = INTF_2,
338		.base = 0x36000, .len = 0x2c4,
339		.features = INTF_SC7280_MASK,
340		.type = INTF_DSI,
341		.controller_id = MSM_DSI_CONTROLLER_1,
342		.prog_fetch_lines_worst_case = 24,
343		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
344		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
345		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
346	}, {
347		.name = "intf_3", .id = INTF_3,
348		.base = 0x37000, .len = 0x280,
349		.features = INTF_SC7280_MASK,
350		.type = INTF_DP,
351		.controller_id = MSM_DP_CONTROLLER_1,
352		.prog_fetch_lines_worst_case = 24,
353		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
354		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
355	},
356};
357
358static const struct dpu_perf_cfg sm8350_perf_data = {
359	.max_bw_low = 11800000,
360	.max_bw_high = 15500000,
361	.min_core_ib = 2500000,
362	.min_llcc_ib = 0,
363	.min_dram_ib = 800000,
364	.min_prefill_lines = 40,
365	/* FIXME: lut tables */
366	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
367	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
368	.qos_lut_tbl = {
369		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
370		.entries = sc7180_qos_linear
371		},
372		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
373		.entries = sc7180_qos_macrotile
374		},
375		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
376		.entries = sc7180_qos_nrt
377		},
378		/* TODO: macrotile-qseed is different from macrotile */
379	},
380	.cdp_cfg = {
381		{.rd_enable = 1, .wr_enable = 1},
382		{.rd_enable = 1, .wr_enable = 0}
383	},
384	.clk_inefficiency_factor = 105,
385	.bw_inefficiency_factor = 120,
386};
387
388static const struct dpu_mdss_version sm8350_mdss_ver = {
389	.core_major_ver = 7,
390	.core_minor_ver = 0,
391};
392
393const struct dpu_mdss_cfg dpu_sm8350_cfg = {
394	.mdss_ver = &sm8350_mdss_ver,
395	.caps = &sm8350_dpu_caps,
396	.mdp = &sm8350_mdp,
397	.ctl_count = ARRAY_SIZE(sm8350_ctl),
398	.ctl = sm8350_ctl,
399	.sspp_count = ARRAY_SIZE(sm8350_sspp),
400	.sspp = sm8350_sspp,
401	.mixer_count = ARRAY_SIZE(sm8350_lm),
402	.mixer = sm8350_lm,
403	.dspp_count = ARRAY_SIZE(sm8350_dspp),
404	.dspp = sm8350_dspp,
405	.pingpong_count = ARRAY_SIZE(sm8350_pp),
406	.pingpong = sm8350_pp,
407	.dsc_count = ARRAY_SIZE(sm8350_dsc),
408	.dsc = sm8350_dsc,
409	.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
410	.merge_3d = sm8350_merge_3d,
411	.wb_count = ARRAY_SIZE(sm8350_wb),
412	.wb = sm8350_wb,
413	.intf_count = ARRAY_SIZE(sm8350_intf),
414	.intf = sm8350_intf,
415	.vbif_count = ARRAY_SIZE(sdm845_vbif),
416	.vbif = sdm845_vbif,
417	.perf = &sm8350_perf_data,
418};
419
420#endif
421