Searched refs:pwr (Results 1 - 22 of 22) sorted by relevance

/freebsd-11-stable/sys/dev/ath/ath_hal/ar9002/
H A Dar9280_olc.h39 uint8_t *calChans, uint16_t availPiers, uint8_t *pwr, uint8_t *pcdacIdx);
H A Dar9280_olc.c63 uint8_t *calChans, uint16_t availPiers, uint8_t *pwr, uint8_t *pcdacIdx)
81 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
84 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
220 * pdadc vs pwr table needs to be adjusted prior to writing to the
396 * pdadc vs pwr table needs to be adjusted prior to writing to the
60 ar9280olcGetTxGainIndex(struct ath_hal *ah, const struct ieee80211_channel *chan, struct calDataPerFreqOpLoop *rawDatasetOpLoop, uint8_t *calChans, uint16_t availPiers, uint8_t *pwr, uint8_t *pcdacIdx) argument
H A Dar9280_attach.c161 uint8_t pwr; local
317 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr);
318 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) {
329 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5212/
H A Dar5111.c405 int16_t pwr; local
492 pwr = (uint16_t)(PWR_STEP *
497 for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++) {
503 while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
505 pwr += PWR_STEP;
507 while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
508 (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
511 scaledPcdac = (uint16_t)(interpolate(pwr,
547 uint16_t lPwr, uPwr; /* lower and upper temp pwr value
[all...]
/freebsd-11-stable/crypto/openssl/crypto/bn/asm/
H A Dsparct4-mont.pl355 my ($ptbl,$pwr,$ccr,$skip_wr)=@_;
357 srl $pwr, 2, %o4
358 and $pwr, 3, %o5
432 # const u64 *pwrtbl,int pwr,int stride);
436 my ($tp,$np,$pwrtbl,$pwr,$sentinel)=map("%g$_",(1..5));
484 sllx %i5,32,$pwr
485 or %i4,$pwr,$pwr
529 # load pwrtbl[pwr] ########################################################
533 srlx $pwr, 3
[all...]
H A Drsaz-x86_64.pl918 my ($out,$ap,$bp,$mod,$n0,$pwr) = ("%rdi","%rsi","%rdx","%rcx","%r8","%r9d");
947 movd $pwr,%xmm8
1370 my ($out,$ap,$mod,$n0,$tbl,$pwr) = ("%rdi","%rsi","%rdx","%rcx","%r8","%r9d");
1383 mov $pwr, $pwr
1386 leaq ($tbl,$pwr,8), $tbl
/freebsd-11-stable/stand/ficl/
H A Dvm.c667 int pwr; local
673 pwr = isPowerOfTwo((FICL_UNS)radix);
680 else if (pwr != 0)
683 FICL_UNS mask = (FICL_UNS) ~(-1 << pwr);
687 v >>= pwr; local
/freebsd-11-stable/sys/arm/lpc/
H A Dlpc_pwr.c71 if (!ofw_bus_is_compatible(dev, "lpc,pwr"))
124 "pwr",
129 DRIVER_MODULE(pwr, simplebus, lpc_pwr_driver, lpc_pwr_devclass, 0, 0);
H A Dlpc_mmc.c628 uint32_t clkdiv = 0, pwr = 0; local
651 pwr |= LPC_SD_POWER_CTRL_OFF;
654 pwr |= LPC_SD_POWER_CTRL_UP;
657 pwr |= LPC_SD_POWER_CTRL_ON;
662 pwr |= LPC_SD_POWER_OPENDRAIN;
664 lpc_mmc_write_4(sc, LPC_SD_POWER, pwr);
/freebsd-11-stable/sys/arm/ti/am335x/
H A Dam335x_pmic.c229 char pwr[4][11] = {"Battery", "USB", "AC", "USB and AC"}; local
254 pwr[status_reg.usbpwr | (status_reg.acpwr << 1)]);
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_reset.c1385 int16_t pwr; local
1445 pwr = (uint16_t)(PWR_STEP * ((minScaledPwr - PWR_MIN + PWR_STEP / 2) / PWR_STEP) + PWR_MIN);
1449 for (i = 0; i < (2 * (pwr - PWR_MIN) / EEP_SCALE + 1); i++)
1453 while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1]) {
1454 pwr += PWR_STEP;
1456 while (pwr < pScaledUpDbm[pcdacStruct.numPcdacValues - 1] &&
1457 (pwr - pScaledUpDbm[i])*(pwr - pScaledUpDbm[i+1]) > 0)
1460 scaledPcdac = (uint16_t)(ar5211GetInterpolatedValue(pwr,
1700 uint16_t lPwr, uPwr; /* lower and upper temp pwr value
[all...]
/freebsd-11-stable/sys/dev/sound/pci/
H A Dcsa.c773 int i, j, pwr; local
780 pwr = 1;
784 pwr = 0;
805 if (!pwr)
817 if (!pwr)
/freebsd-11-stable/sys/dev/sdhci/
H A Dsdhci.c416 uint8_t pwr; local
424 pwr = 0;
425 WR1(slot, SDHCI_POWER_CONTROL, pwr);
432 pwr |= SDHCI_POWER_180;
436 pwr |= SDHCI_POWER_300;
440 pwr |= SDHCI_POWER_330;
443 WR1(slot, SDHCI_POWER_CONTROL, pwr);
449 pwr |= SDHCI_POWER_ON;
451 WR1(slot, SDHCI_POWER_CONTROL, pwr);
460 WR1(slot, SDHCI_POWER_CONTROL, pwr |
[all...]
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_spectral.c219 int pwr; member in struct:nf_cal
292 return nf_cal_table[i].chain[ch].pwr;
298 "no nf pwr offset found for freq %d chain %d\n",
/freebsd-11-stable/sys/dev/wpi/
H A Dif_wpi.c3720 int pwr, idx; local
3723 pwr = group->maxpwr / 2;
3728 pwr -= is_chan_5ghz ? 5 : 0;
3731 pwr -= is_chan_5ghz ? 10 : 7;
3734 pwr -= is_chan_5ghz ? 12 : 9;
3739 pwr = min(pwr, sc->maxpwr[chan]);
3743 if (pwr > sample[1].power)
3746 idx = interpolate(pwr, sample[0].power, sample[0].index,
/freebsd-11-stable/sys/dev/urtwn/
H A Dif_urtwn.c4601 power[ridx] = base->pwr[0][ridx];
4605 power[ridx] = base->pwr[0][ridx];
4616 power[ridx] = base->pwr[group][ridx];
4618 power[ridx] = base->pwr[0][ridx];
4700 power[ridx] = base->pwr[0][ridx];
4704 power[ridx] = base->pwr[0][ridx];
4707 power[ridx] = base->pwr[group][ridx];
4709 power[ridx] = base->pwr[0][ridx];
H A Dif_urtwnreg.h2070 uint8_t pwr[3][28]; member in struct:urtwn_txpwr
2074 uint8_t pwr[6][28]; member in struct:urtwn_r88e_txpwr
/freebsd-11-stable/sys/dev/nfe/
H A Dif_nfe.c873 uint32_t pwr; local
883 pwr = NFE_READ(sc, NFE_PWR2_CTL);
884 pwr &= ~NFE_PWR2_WAKEUP_MASK;
888 pwr |= NFE_PWR2_REVA3;
889 NFE_WRITE(sc, NFE_PWR2_CTL, pwr);
/freebsd-11-stable/sys/dev/rtwn/
H A Dif_rtwn.c2600 power[ridx] = base->pwr[0][ridx];
2604 power[ridx] = base->pwr[0][ridx];
2615 power[ridx] = base->pwr[group][ridx];
2617 power[ridx] = base->pwr[0][ridx];
H A Dif_rtwnreg.h2023 uint8_t pwr[3][28]; member in struct:rtwn_txpwr
/freebsd-11-stable/sys/dev/iwn/
H A Dif_iwn.c5582 int maxchpwr, pwr, ridx, idx; local
5609 pwr = maxpwr;
5613 pwr -= 15; /* OFDM48: -7.5dB */
5615 pwr -= 17; /* OFDM54: -8.5dB */
5617 pwr -= 20; /* OFDM60: -10dB */
5619 pwr -= 10; /* Others: -5dB */
5622 if (pwr > maxchpwr)
5623 pwr = maxchpwr;
5625 idx = gain - (pwr - power) - tdiff - vdiff;
/freebsd-11-stable/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_core.c3739 /* We disable enabled TX pwr ctl, save it's state */
3817 /* Recover TX pwr ctl state */
4176 int32_t num, den, pwr; local
4339 pwr = max((4 * num + den / 2) / den, -8);
4341 pwr = max(pwr, target[c] + 1);
4342 regval[i] = pwr;
6621 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
6622 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */

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