1/* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ 2 3/*- 4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp> 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: stable/11/sys/dev/nfe/if_nfe.c 342294 2018-12-21 02:26:08Z markj $"); 25 26#ifdef HAVE_KERNEL_OPTION_HEADERS 27#include "opt_device_polling.h" 28#endif 29 30#include <sys/param.h> 31#include <sys/endian.h> 32#include <sys/systm.h> 33#include <sys/sockio.h> 34#include <sys/mbuf.h> 35#include <sys/malloc.h> 36#include <sys/module.h> 37#include <sys/kernel.h> 38#include <sys/queue.h> 39#include <sys/socket.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <net/if.h> 44#include <net/if_var.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_types.h> 50#include <net/if_vlan_var.h> 51 52#include <net/bpf.h> 53 54#include <machine/bus.h> 55#include <machine/resource.h> 56#include <sys/bus.h> 57#include <sys/rman.h> 58 59#include <dev/mii/mii.h> 60#include <dev/mii/miivar.h> 61 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcivar.h> 64 65#include <dev/nfe/if_nfereg.h> 66#include <dev/nfe/if_nfevar.h> 67 68MODULE_DEPEND(nfe, pci, 1, 1, 1); 69MODULE_DEPEND(nfe, ether, 1, 1, 1); 70MODULE_DEPEND(nfe, miibus, 1, 1, 1); 71 72/* "device miibus" required. See GENERIC if you get errors here. */ 73#include "miibus_if.h" 74 75static int nfe_probe(device_t); 76static int nfe_attach(device_t); 77static int nfe_detach(device_t); 78static int nfe_suspend(device_t); 79static int nfe_resume(device_t); 80static int nfe_shutdown(device_t); 81static int nfe_can_use_msix(struct nfe_softc *); 82static int nfe_detect_msik9(struct nfe_softc *); 83static void nfe_power(struct nfe_softc *); 84static int nfe_miibus_readreg(device_t, int, int); 85static int nfe_miibus_writereg(device_t, int, int, int); 86static void nfe_miibus_statchg(device_t); 87static void nfe_mac_config(struct nfe_softc *, struct mii_data *); 88static void nfe_set_intr(struct nfe_softc *); 89static __inline void nfe_enable_intr(struct nfe_softc *); 90static __inline void nfe_disable_intr(struct nfe_softc *); 91static int nfe_ioctl(if_t, u_long, caddr_t); 92static void nfe_alloc_msix(struct nfe_softc *, int); 93static int nfe_intr(void *); 94static void nfe_int_task(void *, int); 95static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); 96static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); 97static int nfe_newbuf(struct nfe_softc *, int); 98static int nfe_jnewbuf(struct nfe_softc *, int); 99static int nfe_rxeof(struct nfe_softc *, int, int *); 100static int nfe_jrxeof(struct nfe_softc *, int, int *); 101static void nfe_txeof(struct nfe_softc *); 102static int nfe_encap(struct nfe_softc *, struct mbuf **); 103static void nfe_setmulti(struct nfe_softc *); 104static void nfe_start(if_t); 105static void nfe_start_locked(if_t); 106static void nfe_watchdog(if_t); 107static void nfe_init(void *); 108static void nfe_init_locked(void *); 109static void nfe_stop(if_t); 110static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 111static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 112static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 113static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 114static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 115static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 116static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 117static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 118static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 119static int nfe_ifmedia_upd(if_t); 120static void nfe_ifmedia_sts(if_t, struct ifmediareq *); 121static void nfe_tick(void *); 122static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 123static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); 124static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); 125 126static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 127static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); 128static void nfe_sysctl_node(struct nfe_softc *); 129static void nfe_stats_clear(struct nfe_softc *); 130static void nfe_stats_update(struct nfe_softc *); 131static void nfe_set_linkspeed(struct nfe_softc *); 132static void nfe_set_wol(struct nfe_softc *); 133 134#ifdef NFE_DEBUG 135static int nfedebug = 0; 136#define DPRINTF(sc, ...) do { \ 137 if (nfedebug) \ 138 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 139} while (0) 140#define DPRINTFN(sc, n, ...) do { \ 141 if (nfedebug >= (n)) \ 142 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 143} while (0) 144#else 145#define DPRINTF(sc, ...) 146#define DPRINTFN(sc, n, ...) 147#endif 148 149#define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) 150#define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) 151#define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) 152 153/* Tunables. */ 154static int msi_disable = 0; 155static int msix_disable = 0; 156static int jumbo_disable = 0; 157TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); 158TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); 159TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); 160 161static device_method_t nfe_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, nfe_probe), 164 DEVMETHOD(device_attach, nfe_attach), 165 DEVMETHOD(device_detach, nfe_detach), 166 DEVMETHOD(device_suspend, nfe_suspend), 167 DEVMETHOD(device_resume, nfe_resume), 168 DEVMETHOD(device_shutdown, nfe_shutdown), 169 170 /* MII interface */ 171 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 172 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 173 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 174 175 DEVMETHOD_END 176}; 177 178static driver_t nfe_driver = { 179 "nfe", 180 nfe_methods, 181 sizeof(struct nfe_softc) 182}; 183 184static devclass_t nfe_devclass; 185 186DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); 187DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 188 189static struct nfe_type nfe_devs[] = { 190 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 191 "NVIDIA nForce MCP Networking Adapter"}, 192 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 193 "NVIDIA nForce2 MCP2 Networking Adapter"}, 194 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, 195 "NVIDIA nForce2 400 MCP4 Networking Adapter"}, 196 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, 197 "NVIDIA nForce2 400 MCP5 Networking Adapter"}, 198 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 199 "NVIDIA nForce3 MCP3 Networking Adapter"}, 200 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, 201 "NVIDIA nForce3 250 MCP6 Networking Adapter"}, 202 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 203 "NVIDIA nForce3 MCP7 Networking Adapter"}, 204 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, 205 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, 206 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, 207 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, 208 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 209 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ 210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 211 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ 212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, 213 "NVIDIA nForce 430 MCP12 Networking Adapter"}, 214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, 215 "NVIDIA nForce 430 MCP13 Networking Adapter"}, 216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 217 "NVIDIA nForce MCP55 Networking Adapter"}, 218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 219 "NVIDIA nForce MCP55 Networking Adapter"}, 220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 221 "NVIDIA nForce MCP61 Networking Adapter"}, 222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 223 "NVIDIA nForce MCP61 Networking Adapter"}, 224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 225 "NVIDIA nForce MCP61 Networking Adapter"}, 226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 227 "NVIDIA nForce MCP61 Networking Adapter"}, 228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 229 "NVIDIA nForce MCP65 Networking Adapter"}, 230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 231 "NVIDIA nForce MCP65 Networking Adapter"}, 232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 233 "NVIDIA nForce MCP65 Networking Adapter"}, 234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 235 "NVIDIA nForce MCP65 Networking Adapter"}, 236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 237 "NVIDIA nForce MCP67 Networking Adapter"}, 238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 239 "NVIDIA nForce MCP67 Networking Adapter"}, 240 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 241 "NVIDIA nForce MCP67 Networking Adapter"}, 242 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 243 "NVIDIA nForce MCP67 Networking Adapter"}, 244 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1, 245 "NVIDIA nForce MCP73 Networking Adapter"}, 246 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2, 247 "NVIDIA nForce MCP73 Networking Adapter"}, 248 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3, 249 "NVIDIA nForce MCP73 Networking Adapter"}, 250 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4, 251 "NVIDIA nForce MCP73 Networking Adapter"}, 252 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1, 253 "NVIDIA nForce MCP77 Networking Adapter"}, 254 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2, 255 "NVIDIA nForce MCP77 Networking Adapter"}, 256 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3, 257 "NVIDIA nForce MCP77 Networking Adapter"}, 258 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4, 259 "NVIDIA nForce MCP77 Networking Adapter"}, 260 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1, 261 "NVIDIA nForce MCP79 Networking Adapter"}, 262 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2, 263 "NVIDIA nForce MCP79 Networking Adapter"}, 264 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3, 265 "NVIDIA nForce MCP79 Networking Adapter"}, 266 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4, 267 "NVIDIA nForce MCP79 Networking Adapter"}, 268 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP89_LAN, 269 "NVIDIA nForce MCP89 Networking Adapter"}, 270 {0, 0, NULL} 271}; 272 273 274/* Probe for supported hardware ID's */ 275static int 276nfe_probe(device_t dev) 277{ 278 struct nfe_type *t; 279 280 t = nfe_devs; 281 /* Check for matching PCI DEVICE ID's */ 282 while (t->name != NULL) { 283 if ((pci_get_vendor(dev) == t->vid_id) && 284 (pci_get_device(dev) == t->dev_id)) { 285 device_set_desc(dev, t->name); 286 return (BUS_PROBE_DEFAULT); 287 } 288 t++; 289 } 290 291 return (ENXIO); 292} 293 294static void 295nfe_alloc_msix(struct nfe_softc *sc, int count) 296{ 297 int rid; 298 299 rid = PCIR_BAR(2); 300 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, 301 &rid, RF_ACTIVE); 302 if (sc->nfe_msix_res == NULL) { 303 device_printf(sc->nfe_dev, 304 "couldn't allocate MSIX table resource\n"); 305 return; 306 } 307 rid = PCIR_BAR(3); 308 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, 309 SYS_RES_MEMORY, &rid, RF_ACTIVE); 310 if (sc->nfe_msix_pba_res == NULL) { 311 device_printf(sc->nfe_dev, 312 "couldn't allocate MSIX PBA resource\n"); 313 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), 314 sc->nfe_msix_res); 315 sc->nfe_msix_res = NULL; 316 return; 317 } 318 319 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { 320 if (count == NFE_MSI_MESSAGES) { 321 if (bootverbose) 322 device_printf(sc->nfe_dev, 323 "Using %d MSIX messages\n", count); 324 sc->nfe_msix = 1; 325 } else { 326 if (bootverbose) 327 device_printf(sc->nfe_dev, 328 "couldn't allocate MSIX\n"); 329 pci_release_msi(sc->nfe_dev); 330 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 331 PCIR_BAR(3), sc->nfe_msix_pba_res); 332 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 333 PCIR_BAR(2), sc->nfe_msix_res); 334 sc->nfe_msix_pba_res = NULL; 335 sc->nfe_msix_res = NULL; 336 } 337 } 338} 339 340 341static int 342nfe_detect_msik9(struct nfe_softc *sc) 343{ 344 static const char *maker = "MSI"; 345 static const char *product = "K9N6PGM2-V2 (MS-7309)"; 346 char *m, *p; 347 int found; 348 349 found = 0; 350 m = kern_getenv("smbios.planar.maker"); 351 p = kern_getenv("smbios.planar.product"); 352 if (m != NULL && p != NULL) { 353 if (strcmp(m, maker) == 0 && strcmp(p, product) == 0) 354 found = 1; 355 } 356 if (m != NULL) 357 freeenv(m); 358 if (p != NULL) 359 freeenv(p); 360 361 return (found); 362} 363 364 365static int 366nfe_attach(device_t dev) 367{ 368 struct nfe_softc *sc; 369 if_t ifp; 370 bus_addr_t dma_addr_max; 371 int error = 0, i, msic, phyloc, reg, rid; 372 373 sc = device_get_softc(dev); 374 sc->nfe_dev = dev; 375 376 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 377 MTX_DEF); 378 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); 379 380 pci_enable_busmaster(dev); 381 382 rid = PCIR_BAR(0); 383 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 384 RF_ACTIVE); 385 if (sc->nfe_res[0] == NULL) { 386 device_printf(dev, "couldn't map memory resources\n"); 387 mtx_destroy(&sc->nfe_mtx); 388 return (ENXIO); 389 } 390 391 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 392 uint16_t v, width; 393 394 v = pci_read_config(dev, reg + 0x08, 2); 395 /* Change max. read request size to 4096. */ 396 v &= ~(7 << 12); 397 v |= (5 << 12); 398 pci_write_config(dev, reg + 0x08, v, 2); 399 400 v = pci_read_config(dev, reg + 0x0c, 2); 401 /* link capability */ 402 v = (v >> 4) & 0x0f; 403 width = pci_read_config(dev, reg + 0x12, 2); 404 /* negotiated link width */ 405 width = (width >> 4) & 0x3f; 406 if (v != width) 407 device_printf(sc->nfe_dev, 408 "warning, negotiated width of link(x%d) != " 409 "max. width of link(x%d)\n", width, v); 410 } 411 412 if (nfe_can_use_msix(sc) == 0) { 413 device_printf(sc->nfe_dev, 414 "MSI/MSI-X capability black-listed, will use INTx\n"); 415 msix_disable = 1; 416 msi_disable = 1; 417 } 418 419 /* Allocate interrupt */ 420 if (msix_disable == 0 || msi_disable == 0) { 421 if (msix_disable == 0 && 422 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) 423 nfe_alloc_msix(sc, msic); 424 if (msi_disable == 0 && sc->nfe_msix == 0 && 425 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && 426 pci_alloc_msi(dev, &msic) == 0) { 427 if (msic == NFE_MSI_MESSAGES) { 428 if (bootverbose) 429 device_printf(dev, 430 "Using %d MSI messages\n", msic); 431 sc->nfe_msi = 1; 432 } else 433 pci_release_msi(dev); 434 } 435 } 436 437 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { 438 rid = 0; 439 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 440 RF_SHAREABLE | RF_ACTIVE); 441 if (sc->nfe_irq[0] == NULL) { 442 device_printf(dev, "couldn't allocate IRQ resources\n"); 443 error = ENXIO; 444 goto fail; 445 } 446 } else { 447 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 448 sc->nfe_irq[i] = bus_alloc_resource_any(dev, 449 SYS_RES_IRQ, &rid, RF_ACTIVE); 450 if (sc->nfe_irq[i] == NULL) { 451 device_printf(dev, 452 "couldn't allocate IRQ resources for " 453 "message %d\n", rid); 454 error = ENXIO; 455 goto fail; 456 } 457 } 458 /* Map interrupts to vector 0. */ 459 if (sc->nfe_msix != 0) { 460 NFE_WRITE(sc, NFE_MSIX_MAP0, 0); 461 NFE_WRITE(sc, NFE_MSIX_MAP1, 0); 462 } else if (sc->nfe_msi != 0) { 463 NFE_WRITE(sc, NFE_MSI_MAP0, 0); 464 NFE_WRITE(sc, NFE_MSI_MAP1, 0); 465 } 466 } 467 468 /* Set IRQ status/mask register. */ 469 sc->nfe_irq_status = NFE_IRQ_STATUS; 470 sc->nfe_irq_mask = NFE_IRQ_MASK; 471 sc->nfe_intrs = NFE_IRQ_WANTED; 472 sc->nfe_nointrs = 0; 473 if (sc->nfe_msix != 0) { 474 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; 475 sc->nfe_nointrs = NFE_IRQ_WANTED; 476 } else if (sc->nfe_msi != 0) { 477 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; 478 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; 479 } 480 481 sc->nfe_devid = pci_get_device(dev); 482 sc->nfe_revid = pci_get_revid(dev); 483 sc->nfe_flags = 0; 484 485 switch (sc->nfe_devid) { 486 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 487 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 488 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 489 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 490 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 491 break; 492 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 493 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 494 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1; 495 break; 496 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 497 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 498 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 499 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 500 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 501 NFE_MIB_V1; 502 break; 503 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 504 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 505 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 506 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 507 break; 508 509 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 510 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 511 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 512 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 513 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 514 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 515 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 516 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 517 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 518 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 519 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 520 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 521 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | 522 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 523 break; 524 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 525 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 526 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 527 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 528 /* XXX flow control */ 529 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT | 530 NFE_CORRECT_MACADDR | NFE_MIB_V3; 531 break; 532 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 533 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 534 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 535 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 536 case PCI_PRODUCT_NVIDIA_MCP89_LAN: 537 /* XXX flow control */ 538 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 539 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3; 540 break; 541 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 542 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 543 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 544 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 545 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 546 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | 547 NFE_MIB_V2; 548 break; 549 } 550 551 nfe_power(sc); 552 /* Check for reversed ethernet address */ 553 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 554 sc->nfe_flags |= NFE_CORRECT_MACADDR; 555 nfe_get_macaddr(sc, sc->eaddr); 556 /* 557 * Allocate the parent bus DMA tag appropriate for PCI. 558 */ 559 dma_addr_max = BUS_SPACE_MAXADDR_32BIT; 560 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) 561 dma_addr_max = NFE_DMA_MAXADDR; 562 error = bus_dma_tag_create( 563 bus_get_dma_tag(sc->nfe_dev), /* parent */ 564 1, 0, /* alignment, boundary */ 565 dma_addr_max, /* lowaddr */ 566 BUS_SPACE_MAXADDR, /* highaddr */ 567 NULL, NULL, /* filter, filterarg */ 568 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 569 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 570 0, /* flags */ 571 NULL, NULL, /* lockfunc, lockarg */ 572 &sc->nfe_parent_tag); 573 if (error) 574 goto fail; 575 576 ifp = sc->nfe_ifp = if_gethandle(IFT_ETHER); 577 if (ifp == NULL) { 578 device_printf(dev, "can not if_gethandle()\n"); 579 error = ENOSPC; 580 goto fail; 581 } 582 583 /* 584 * Allocate Tx and Rx rings. 585 */ 586 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) 587 goto fail; 588 589 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) 590 goto fail; 591 592 nfe_alloc_jrx_ring(sc, &sc->jrxq); 593 /* Create sysctl node. */ 594 nfe_sysctl_node(sc); 595 596 if_setsoftc(ifp, sc); 597 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 598 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 599 if_setioctlfn(ifp, nfe_ioctl); 600 if_setstartfn(ifp, nfe_start); 601 if_sethwassist(ifp, 0); 602 if_setcapabilities(ifp, 0); 603 if_setinitfn(ifp, nfe_init); 604 if_setsendqlen(ifp, NFE_TX_RING_COUNT - 1); 605 if_setsendqready(ifp); 606 607 608 if (sc->nfe_flags & NFE_HW_CSUM) { 609 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 610 if_sethwassistbits(ifp, NFE_CSUM_FEATURES | CSUM_TSO, 0); 611 } 612 if_setcapenable(ifp, if_getcapabilities(ifp)); 613 614 sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS; 615 /* VLAN capability setup. */ 616 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 617 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { 618 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 619 if ((if_getcapabilities(ifp) & IFCAP_HWCSUM) != 0) 620 if_setcapabilitiesbit(ifp, 621 (IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO), 0); 622 } 623 624 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) 625 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 626 if_setcapenable(ifp, if_getcapabilities(ifp)); 627 628 /* 629 * Tell the upper layer(s) we support long frames. 630 * Must appear after the call to ether_ifattach() because 631 * ether_ifattach() sets ifi_hdrlen to the default value. 632 */ 633 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 634 635#ifdef DEVICE_POLLING 636 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 637#endif 638 639 /* Do MII setup */ 640 phyloc = MII_PHY_ANY; 641 if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 || 642 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 || 643 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 || 644 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) { 645 if (nfe_detect_msik9(sc) != 0) 646 phyloc = 0; 647 } 648 error = mii_attach(dev, &sc->nfe_miibus, ifp, 649 (ifm_change_cb_t)nfe_ifmedia_upd, (ifm_stat_cb_t)nfe_ifmedia_sts, 650 BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, MIIF_DOPAUSE); 651 if (error != 0) { 652 device_printf(dev, "attaching PHYs failed\n"); 653 goto fail; 654 } 655 ether_ifattach(ifp, sc->eaddr); 656 657 TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); 658 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, 659 taskqueue_thread_enqueue, &sc->nfe_tq); 660 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", 661 device_get_nameunit(sc->nfe_dev)); 662 error = 0; 663 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 664 error = bus_setup_intr(dev, sc->nfe_irq[0], 665 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 666 &sc->nfe_intrhand[0]); 667 } else { 668 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 669 error = bus_setup_intr(dev, sc->nfe_irq[i], 670 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 671 &sc->nfe_intrhand[i]); 672 if (error != 0) 673 break; 674 } 675 } 676 if (error) { 677 device_printf(dev, "couldn't set up irq\n"); 678 taskqueue_free(sc->nfe_tq); 679 sc->nfe_tq = NULL; 680 ether_ifdetach(ifp); 681 goto fail; 682 } 683 684fail: 685 if (error) 686 nfe_detach(dev); 687 688 return (error); 689} 690 691 692static int 693nfe_detach(device_t dev) 694{ 695 struct nfe_softc *sc; 696 if_t ifp; 697 uint8_t eaddr[ETHER_ADDR_LEN]; 698 int i, rid; 699 700 sc = device_get_softc(dev); 701 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); 702 ifp = sc->nfe_ifp; 703 704#ifdef DEVICE_POLLING 705 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 706 ether_poll_deregister(ifp); 707#endif 708 if (device_is_attached(dev)) { 709 NFE_LOCK(sc); 710 nfe_stop(ifp); 711 if_setflagbits(ifp, 0, IFF_UP); 712 NFE_UNLOCK(sc); 713 callout_drain(&sc->nfe_stat_ch); 714 ether_ifdetach(ifp); 715 } 716 717 if (ifp) { 718 /* restore ethernet address */ 719 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 720 for (i = 0; i < ETHER_ADDR_LEN; i++) { 721 eaddr[i] = sc->eaddr[5 - i]; 722 } 723 } else 724 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); 725 nfe_set_macaddr(sc, eaddr); 726 if_free(ifp); 727 } 728 if (sc->nfe_miibus) 729 device_delete_child(dev, sc->nfe_miibus); 730 bus_generic_detach(dev); 731 if (sc->nfe_tq != NULL) { 732 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); 733 taskqueue_free(sc->nfe_tq); 734 sc->nfe_tq = NULL; 735 } 736 737 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 738 if (sc->nfe_intrhand[i] != NULL) { 739 bus_teardown_intr(dev, sc->nfe_irq[i], 740 sc->nfe_intrhand[i]); 741 sc->nfe_intrhand[i] = NULL; 742 } 743 } 744 745 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 746 if (sc->nfe_irq[0] != NULL) 747 bus_release_resource(dev, SYS_RES_IRQ, 0, 748 sc->nfe_irq[0]); 749 } else { 750 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 751 if (sc->nfe_irq[i] != NULL) { 752 bus_release_resource(dev, SYS_RES_IRQ, rid, 753 sc->nfe_irq[i]); 754 sc->nfe_irq[i] = NULL; 755 } 756 } 757 pci_release_msi(dev); 758 } 759 if (sc->nfe_msix_pba_res != NULL) { 760 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), 761 sc->nfe_msix_pba_res); 762 sc->nfe_msix_pba_res = NULL; 763 } 764 if (sc->nfe_msix_res != NULL) { 765 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), 766 sc->nfe_msix_res); 767 sc->nfe_msix_res = NULL; 768 } 769 if (sc->nfe_res[0] != NULL) { 770 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 771 sc->nfe_res[0]); 772 sc->nfe_res[0] = NULL; 773 } 774 775 nfe_free_tx_ring(sc, &sc->txq); 776 nfe_free_rx_ring(sc, &sc->rxq); 777 nfe_free_jrx_ring(sc, &sc->jrxq); 778 779 if (sc->nfe_parent_tag) { 780 bus_dma_tag_destroy(sc->nfe_parent_tag); 781 sc->nfe_parent_tag = NULL; 782 } 783 784 mtx_destroy(&sc->nfe_mtx); 785 786 return (0); 787} 788 789 790static int 791nfe_suspend(device_t dev) 792{ 793 struct nfe_softc *sc; 794 795 sc = device_get_softc(dev); 796 797 NFE_LOCK(sc); 798 nfe_stop(sc->nfe_ifp); 799 nfe_set_wol(sc); 800 sc->nfe_suspended = 1; 801 NFE_UNLOCK(sc); 802 803 return (0); 804} 805 806 807static int 808nfe_resume(device_t dev) 809{ 810 struct nfe_softc *sc; 811 if_t ifp; 812 813 sc = device_get_softc(dev); 814 815 NFE_LOCK(sc); 816 nfe_power(sc); 817 ifp = sc->nfe_ifp; 818 if (if_getflags(ifp) & IFF_UP) 819 nfe_init_locked(sc); 820 sc->nfe_suspended = 0; 821 NFE_UNLOCK(sc); 822 823 return (0); 824} 825 826 827static int 828nfe_can_use_msix(struct nfe_softc *sc) 829{ 830 static struct msix_blacklist { 831 char *maker; 832 char *product; 833 } msix_blacklists[] = { 834 { "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" } 835 }; 836 837 struct msix_blacklist *mblp; 838 char *maker, *product; 839 int count, n, use_msix; 840 841 /* 842 * Search base board manufacturer and product name table 843 * to see this system has a known MSI/MSI-X issue. 844 */ 845 maker = kern_getenv("smbios.planar.maker"); 846 product = kern_getenv("smbios.planar.product"); 847 use_msix = 1; 848 if (maker != NULL && product != NULL) { 849 count = nitems(msix_blacklists); 850 mblp = msix_blacklists; 851 for (n = 0; n < count; n++) { 852 if (strcmp(maker, mblp->maker) == 0 && 853 strcmp(product, mblp->product) == 0) { 854 use_msix = 0; 855 break; 856 } 857 mblp++; 858 } 859 } 860 if (maker != NULL) 861 freeenv(maker); 862 if (product != NULL) 863 freeenv(product); 864 865 return (use_msix); 866} 867 868 869/* Take PHY/NIC out of powerdown, from Linux */ 870static void 871nfe_power(struct nfe_softc *sc) 872{ 873 uint32_t pwr; 874 875 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) 876 return; 877 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 878 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 879 DELAY(100); 880 NFE_WRITE(sc, NFE_MAC_RESET, 0); 881 DELAY(100); 882 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 883 pwr = NFE_READ(sc, NFE_PWR2_CTL); 884 pwr &= ~NFE_PWR2_WAKEUP_MASK; 885 if (sc->nfe_revid >= 0xa3 && 886 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || 887 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) 888 pwr |= NFE_PWR2_REVA3; 889 NFE_WRITE(sc, NFE_PWR2_CTL, pwr); 890} 891 892 893static void 894nfe_miibus_statchg(device_t dev) 895{ 896 struct nfe_softc *sc; 897 struct mii_data *mii; 898 if_t ifp; 899 uint32_t rxctl, txctl; 900 901 sc = device_get_softc(dev); 902 903 mii = device_get_softc(sc->nfe_miibus); 904 ifp = sc->nfe_ifp; 905 906 sc->nfe_link = 0; 907 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 908 (IFM_ACTIVE | IFM_AVALID)) { 909 switch (IFM_SUBTYPE(mii->mii_media_active)) { 910 case IFM_10_T: 911 case IFM_100_TX: 912 case IFM_1000_T: 913 sc->nfe_link = 1; 914 break; 915 default: 916 break; 917 } 918 } 919 920 nfe_mac_config(sc, mii); 921 txctl = NFE_READ(sc, NFE_TX_CTL); 922 rxctl = NFE_READ(sc, NFE_RX_CTL); 923 if (sc->nfe_link != 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 924 txctl |= NFE_TX_START; 925 rxctl |= NFE_RX_START; 926 } else { 927 txctl &= ~NFE_TX_START; 928 rxctl &= ~NFE_RX_START; 929 } 930 NFE_WRITE(sc, NFE_TX_CTL, txctl); 931 NFE_WRITE(sc, NFE_RX_CTL, rxctl); 932} 933 934 935static void 936nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii) 937{ 938 uint32_t link, misc, phy, seed; 939 uint32_t val; 940 941 NFE_LOCK_ASSERT(sc); 942 943 phy = NFE_READ(sc, NFE_PHY_IFACE); 944 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 945 946 seed = NFE_READ(sc, NFE_RNDSEED); 947 seed &= ~NFE_SEED_MASK; 948 949 misc = NFE_MISC1_MAGIC; 950 link = NFE_MEDIA_SET; 951 952 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) { 953 phy |= NFE_PHY_HDX; /* half-duplex */ 954 misc |= NFE_MISC1_HDX; 955 } 956 957 switch (IFM_SUBTYPE(mii->mii_media_active)) { 958 case IFM_1000_T: /* full-duplex only */ 959 link |= NFE_MEDIA_1000T; 960 seed |= NFE_SEED_1000T; 961 phy |= NFE_PHY_1000T; 962 break; 963 case IFM_100_TX: 964 link |= NFE_MEDIA_100TX; 965 seed |= NFE_SEED_100TX; 966 phy |= NFE_PHY_100TX; 967 break; 968 case IFM_10_T: 969 link |= NFE_MEDIA_10T; 970 seed |= NFE_SEED_10T; 971 break; 972 } 973 974 if ((phy & 0x10000000) != 0) { 975 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 976 val = NFE_R1_MAGIC_1000; 977 else 978 val = NFE_R1_MAGIC_10_100; 979 } else 980 val = NFE_R1_MAGIC_DEFAULT; 981 NFE_WRITE(sc, NFE_SETUP_R1, val); 982 983 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 984 985 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 986 NFE_WRITE(sc, NFE_MISC1, misc); 987 NFE_WRITE(sc, NFE_LINKSPEED, link); 988 989 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 990 /* It seems all hardwares supports Rx pause frames. */ 991 val = NFE_READ(sc, NFE_RXFILTER); 992 if ((IFM_OPTIONS(mii->mii_media_active) & 993 IFM_ETH_RXPAUSE) != 0) 994 val |= NFE_PFF_RX_PAUSE; 995 else 996 val &= ~NFE_PFF_RX_PAUSE; 997 NFE_WRITE(sc, NFE_RXFILTER, val); 998 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 999 val = NFE_READ(sc, NFE_MISC1); 1000 if ((IFM_OPTIONS(mii->mii_media_active) & 1001 IFM_ETH_TXPAUSE) != 0) { 1002 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1003 NFE_TX_PAUSE_FRAME_ENABLE); 1004 val |= NFE_MISC1_TX_PAUSE; 1005 } else { 1006 val &= ~NFE_MISC1_TX_PAUSE; 1007 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1008 NFE_TX_PAUSE_FRAME_DISABLE); 1009 } 1010 NFE_WRITE(sc, NFE_MISC1, val); 1011 } 1012 } else { 1013 /* disable rx/tx pause frames */ 1014 val = NFE_READ(sc, NFE_RXFILTER); 1015 val &= ~NFE_PFF_RX_PAUSE; 1016 NFE_WRITE(sc, NFE_RXFILTER, val); 1017 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 1018 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1019 NFE_TX_PAUSE_FRAME_DISABLE); 1020 val = NFE_READ(sc, NFE_MISC1); 1021 val &= ~NFE_MISC1_TX_PAUSE; 1022 NFE_WRITE(sc, NFE_MISC1, val); 1023 } 1024 } 1025} 1026 1027 1028static int 1029nfe_miibus_readreg(device_t dev, int phy, int reg) 1030{ 1031 struct nfe_softc *sc = device_get_softc(dev); 1032 uint32_t val; 1033 int ntries; 1034 1035 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1036 1037 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1038 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1039 DELAY(100); 1040 } 1041 1042 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 1043 1044 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1045 DELAY(100); 1046 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1047 break; 1048 } 1049 if (ntries == NFE_TIMEOUT) { 1050 DPRINTFN(sc, 2, "timeout waiting for PHY\n"); 1051 return 0; 1052 } 1053 1054 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 1055 DPRINTFN(sc, 2, "could not read PHY\n"); 1056 return 0; 1057 } 1058 1059 val = NFE_READ(sc, NFE_PHY_DATA); 1060 if (val != 0xffffffff && val != 0) 1061 sc->mii_phyaddr = phy; 1062 1063 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 1064 1065 return (val); 1066} 1067 1068 1069static int 1070nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 1071{ 1072 struct nfe_softc *sc = device_get_softc(dev); 1073 uint32_t ctl; 1074 int ntries; 1075 1076 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1077 1078 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1079 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1080 DELAY(100); 1081 } 1082 1083 NFE_WRITE(sc, NFE_PHY_DATA, val); 1084 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 1085 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 1086 1087 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1088 DELAY(100); 1089 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1090 break; 1091 } 1092#ifdef NFE_DEBUG 1093 if (nfedebug >= 2 && ntries == NFE_TIMEOUT) 1094 device_printf(sc->nfe_dev, "could not write to PHY\n"); 1095#endif 1096 return (0); 1097} 1098 1099struct nfe_dmamap_arg { 1100 bus_addr_t nfe_busaddr; 1101}; 1102 1103static int 1104nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1105{ 1106 struct nfe_dmamap_arg ctx; 1107 struct nfe_rx_data *data; 1108 void *desc; 1109 int i, error, descsize; 1110 1111 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1112 desc = ring->desc64; 1113 descsize = sizeof (struct nfe_desc64); 1114 } else { 1115 desc = ring->desc32; 1116 descsize = sizeof (struct nfe_desc32); 1117 } 1118 1119 ring->cur = ring->next = 0; 1120 1121 error = bus_dma_tag_create(sc->nfe_parent_tag, 1122 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1123 BUS_SPACE_MAXADDR, /* lowaddr */ 1124 BUS_SPACE_MAXADDR, /* highaddr */ 1125 NULL, NULL, /* filter, filterarg */ 1126 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1127 NFE_RX_RING_COUNT * descsize, /* maxsegsize */ 1128 0, /* flags */ 1129 NULL, NULL, /* lockfunc, lockarg */ 1130 &ring->rx_desc_tag); 1131 if (error != 0) { 1132 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1133 goto fail; 1134 } 1135 1136 /* allocate memory to desc */ 1137 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | 1138 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); 1139 if (error != 0) { 1140 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1141 goto fail; 1142 } 1143 if (sc->nfe_flags & NFE_40BIT_ADDR) 1144 ring->desc64 = desc; 1145 else 1146 ring->desc32 = desc; 1147 1148 /* map desc to device visible address space */ 1149 ctx.nfe_busaddr = 0; 1150 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, 1151 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1152 if (error != 0) { 1153 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1154 goto fail; 1155 } 1156 ring->physaddr = ctx.nfe_busaddr; 1157 1158 error = bus_dma_tag_create(sc->nfe_parent_tag, 1159 1, 0, /* alignment, boundary */ 1160 BUS_SPACE_MAXADDR, /* lowaddr */ 1161 BUS_SPACE_MAXADDR, /* highaddr */ 1162 NULL, NULL, /* filter, filterarg */ 1163 MCLBYTES, 1, /* maxsize, nsegments */ 1164 MCLBYTES, /* maxsegsize */ 1165 0, /* flags */ 1166 NULL, NULL, /* lockfunc, lockarg */ 1167 &ring->rx_data_tag); 1168 if (error != 0) { 1169 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); 1170 goto fail; 1171 } 1172 1173 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); 1174 if (error != 0) { 1175 device_printf(sc->nfe_dev, 1176 "could not create Rx DMA spare map\n"); 1177 goto fail; 1178 } 1179 1180 /* 1181 * Pre-allocate Rx buffers and populate Rx ring. 1182 */ 1183 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1184 data = &sc->rxq.data[i]; 1185 data->rx_data_map = NULL; 1186 data->m = NULL; 1187 error = bus_dmamap_create(ring->rx_data_tag, 0, 1188 &data->rx_data_map); 1189 if (error != 0) { 1190 device_printf(sc->nfe_dev, 1191 "could not create Rx DMA map\n"); 1192 goto fail; 1193 } 1194 } 1195 1196fail: 1197 return (error); 1198} 1199 1200 1201static void 1202nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1203{ 1204 struct nfe_dmamap_arg ctx; 1205 struct nfe_rx_data *data; 1206 void *desc; 1207 int i, error, descsize; 1208 1209 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1210 return; 1211 if (jumbo_disable != 0) { 1212 device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); 1213 sc->nfe_jumbo_disable = 1; 1214 return; 1215 } 1216 1217 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1218 desc = ring->jdesc64; 1219 descsize = sizeof (struct nfe_desc64); 1220 } else { 1221 desc = ring->jdesc32; 1222 descsize = sizeof (struct nfe_desc32); 1223 } 1224 1225 ring->jcur = ring->jnext = 0; 1226 1227 /* Create DMA tag for jumbo Rx ring. */ 1228 error = bus_dma_tag_create(sc->nfe_parent_tag, 1229 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1230 BUS_SPACE_MAXADDR, /* lowaddr */ 1231 BUS_SPACE_MAXADDR, /* highaddr */ 1232 NULL, NULL, /* filter, filterarg */ 1233 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ 1234 1, /* nsegments */ 1235 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ 1236 0, /* flags */ 1237 NULL, NULL, /* lockfunc, lockarg */ 1238 &ring->jrx_desc_tag); 1239 if (error != 0) { 1240 device_printf(sc->nfe_dev, 1241 "could not create jumbo ring DMA tag\n"); 1242 goto fail; 1243 } 1244 1245 /* Create DMA tag for jumbo Rx buffers. */ 1246 error = bus_dma_tag_create(sc->nfe_parent_tag, 1247 1, 0, /* alignment, boundary */ 1248 BUS_SPACE_MAXADDR, /* lowaddr */ 1249 BUS_SPACE_MAXADDR, /* highaddr */ 1250 NULL, NULL, /* filter, filterarg */ 1251 MJUM9BYTES, /* maxsize */ 1252 1, /* nsegments */ 1253 MJUM9BYTES, /* maxsegsize */ 1254 0, /* flags */ 1255 NULL, NULL, /* lockfunc, lockarg */ 1256 &ring->jrx_data_tag); 1257 if (error != 0) { 1258 device_printf(sc->nfe_dev, 1259 "could not create jumbo Rx buffer DMA tag\n"); 1260 goto fail; 1261 } 1262 1263 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 1264 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | 1265 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); 1266 if (error != 0) { 1267 device_printf(sc->nfe_dev, 1268 "could not allocate DMA'able memory for jumbo Rx ring\n"); 1269 goto fail; 1270 } 1271 if (sc->nfe_flags & NFE_40BIT_ADDR) 1272 ring->jdesc64 = desc; 1273 else 1274 ring->jdesc32 = desc; 1275 1276 ctx.nfe_busaddr = 0; 1277 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, 1278 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1279 if (error != 0) { 1280 device_printf(sc->nfe_dev, 1281 "could not load DMA'able memory for jumbo Rx ring\n"); 1282 goto fail; 1283 } 1284 ring->jphysaddr = ctx.nfe_busaddr; 1285 1286 /* Create DMA maps for jumbo Rx buffers. */ 1287 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); 1288 if (error != 0) { 1289 device_printf(sc->nfe_dev, 1290 "could not create jumbo Rx DMA spare map\n"); 1291 goto fail; 1292 } 1293 1294 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1295 data = &sc->jrxq.jdata[i]; 1296 data->rx_data_map = NULL; 1297 data->m = NULL; 1298 error = bus_dmamap_create(ring->jrx_data_tag, 0, 1299 &data->rx_data_map); 1300 if (error != 0) { 1301 device_printf(sc->nfe_dev, 1302 "could not create jumbo Rx DMA map\n"); 1303 goto fail; 1304 } 1305 } 1306 1307 return; 1308 1309fail: 1310 /* 1311 * Running without jumbo frame support is ok for most cases 1312 * so don't fail on creating dma tag/map for jumbo frame. 1313 */ 1314 nfe_free_jrx_ring(sc, ring); 1315 device_printf(sc->nfe_dev, "disabling jumbo frame support due to " 1316 "resource shortage\n"); 1317 sc->nfe_jumbo_disable = 1; 1318} 1319 1320 1321static int 1322nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1323{ 1324 void *desc; 1325 size_t descsize; 1326 int i; 1327 1328 ring->cur = ring->next = 0; 1329 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1330 desc = ring->desc64; 1331 descsize = sizeof (struct nfe_desc64); 1332 } else { 1333 desc = ring->desc32; 1334 descsize = sizeof (struct nfe_desc32); 1335 } 1336 bzero(desc, descsize * NFE_RX_RING_COUNT); 1337 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1338 if (nfe_newbuf(sc, i) != 0) 1339 return (ENOBUFS); 1340 } 1341 1342 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, 1343 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1344 1345 return (0); 1346} 1347 1348 1349static int 1350nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1351{ 1352 void *desc; 1353 size_t descsize; 1354 int i; 1355 1356 ring->jcur = ring->jnext = 0; 1357 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1358 desc = ring->jdesc64; 1359 descsize = sizeof (struct nfe_desc64); 1360 } else { 1361 desc = ring->jdesc32; 1362 descsize = sizeof (struct nfe_desc32); 1363 } 1364 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT); 1365 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1366 if (nfe_jnewbuf(sc, i) != 0) 1367 return (ENOBUFS); 1368 } 1369 1370 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, 1371 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1372 1373 return (0); 1374} 1375 1376 1377static void 1378nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1379{ 1380 struct nfe_rx_data *data; 1381 void *desc; 1382 int i; 1383 1384 if (sc->nfe_flags & NFE_40BIT_ADDR) 1385 desc = ring->desc64; 1386 else 1387 desc = ring->desc32; 1388 1389 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1390 data = &ring->data[i]; 1391 if (data->rx_data_map != NULL) { 1392 bus_dmamap_destroy(ring->rx_data_tag, 1393 data->rx_data_map); 1394 data->rx_data_map = NULL; 1395 } 1396 if (data->m != NULL) { 1397 m_freem(data->m); 1398 data->m = NULL; 1399 } 1400 } 1401 if (ring->rx_data_tag != NULL) { 1402 if (ring->rx_spare_map != NULL) { 1403 bus_dmamap_destroy(ring->rx_data_tag, 1404 ring->rx_spare_map); 1405 ring->rx_spare_map = NULL; 1406 } 1407 bus_dma_tag_destroy(ring->rx_data_tag); 1408 ring->rx_data_tag = NULL; 1409 } 1410 1411 if (desc != NULL) { 1412 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); 1413 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); 1414 ring->desc64 = NULL; 1415 ring->desc32 = NULL; 1416 } 1417 if (ring->rx_desc_tag != NULL) { 1418 bus_dma_tag_destroy(ring->rx_desc_tag); 1419 ring->rx_desc_tag = NULL; 1420 } 1421} 1422 1423 1424static void 1425nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1426{ 1427 struct nfe_rx_data *data; 1428 void *desc; 1429 int i, descsize; 1430 1431 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1432 return; 1433 1434 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1435 desc = ring->jdesc64; 1436 descsize = sizeof (struct nfe_desc64); 1437 } else { 1438 desc = ring->jdesc32; 1439 descsize = sizeof (struct nfe_desc32); 1440 } 1441 1442 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1443 data = &ring->jdata[i]; 1444 if (data->rx_data_map != NULL) { 1445 bus_dmamap_destroy(ring->jrx_data_tag, 1446 data->rx_data_map); 1447 data->rx_data_map = NULL; 1448 } 1449 if (data->m != NULL) { 1450 m_freem(data->m); 1451 data->m = NULL; 1452 } 1453 } 1454 if (ring->jrx_data_tag != NULL) { 1455 if (ring->jrx_spare_map != NULL) { 1456 bus_dmamap_destroy(ring->jrx_data_tag, 1457 ring->jrx_spare_map); 1458 ring->jrx_spare_map = NULL; 1459 } 1460 bus_dma_tag_destroy(ring->jrx_data_tag); 1461 ring->jrx_data_tag = NULL; 1462 } 1463 1464 if (desc != NULL) { 1465 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); 1466 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); 1467 ring->jdesc64 = NULL; 1468 ring->jdesc32 = NULL; 1469 } 1470 1471 if (ring->jrx_desc_tag != NULL) { 1472 bus_dma_tag_destroy(ring->jrx_desc_tag); 1473 ring->jrx_desc_tag = NULL; 1474 } 1475} 1476 1477 1478static int 1479nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1480{ 1481 struct nfe_dmamap_arg ctx; 1482 int i, error; 1483 void *desc; 1484 int descsize; 1485 1486 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1487 desc = ring->desc64; 1488 descsize = sizeof (struct nfe_desc64); 1489 } else { 1490 desc = ring->desc32; 1491 descsize = sizeof (struct nfe_desc32); 1492 } 1493 1494 ring->queued = 0; 1495 ring->cur = ring->next = 0; 1496 1497 error = bus_dma_tag_create(sc->nfe_parent_tag, 1498 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1499 BUS_SPACE_MAXADDR, /* lowaddr */ 1500 BUS_SPACE_MAXADDR, /* highaddr */ 1501 NULL, NULL, /* filter, filterarg */ 1502 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1503 NFE_TX_RING_COUNT * descsize, /* maxsegsize */ 1504 0, /* flags */ 1505 NULL, NULL, /* lockfunc, lockarg */ 1506 &ring->tx_desc_tag); 1507 if (error != 0) { 1508 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1509 goto fail; 1510 } 1511 1512 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | 1513 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); 1514 if (error != 0) { 1515 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1516 goto fail; 1517 } 1518 if (sc->nfe_flags & NFE_40BIT_ADDR) 1519 ring->desc64 = desc; 1520 else 1521 ring->desc32 = desc; 1522 1523 ctx.nfe_busaddr = 0; 1524 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, 1525 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1526 if (error != 0) { 1527 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1528 goto fail; 1529 } 1530 ring->physaddr = ctx.nfe_busaddr; 1531 1532 error = bus_dma_tag_create(sc->nfe_parent_tag, 1533 1, 0, 1534 BUS_SPACE_MAXADDR, 1535 BUS_SPACE_MAXADDR, 1536 NULL, NULL, 1537 NFE_TSO_MAXSIZE, 1538 NFE_MAX_SCATTER, 1539 NFE_TSO_MAXSGSIZE, 1540 0, 1541 NULL, NULL, 1542 &ring->tx_data_tag); 1543 if (error != 0) { 1544 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); 1545 goto fail; 1546 } 1547 1548 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1549 error = bus_dmamap_create(ring->tx_data_tag, 0, 1550 &ring->data[i].tx_data_map); 1551 if (error != 0) { 1552 device_printf(sc->nfe_dev, 1553 "could not create Tx DMA map\n"); 1554 goto fail; 1555 } 1556 } 1557 1558fail: 1559 return (error); 1560} 1561 1562 1563static void 1564nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1565{ 1566 void *desc; 1567 size_t descsize; 1568 1569 sc->nfe_force_tx = 0; 1570 ring->queued = 0; 1571 ring->cur = ring->next = 0; 1572 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1573 desc = ring->desc64; 1574 descsize = sizeof (struct nfe_desc64); 1575 } else { 1576 desc = ring->desc32; 1577 descsize = sizeof (struct nfe_desc32); 1578 } 1579 bzero(desc, descsize * NFE_TX_RING_COUNT); 1580 1581 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1582 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1583} 1584 1585 1586static void 1587nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1588{ 1589 struct nfe_tx_data *data; 1590 void *desc; 1591 int i, descsize; 1592 1593 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1594 desc = ring->desc64; 1595 descsize = sizeof (struct nfe_desc64); 1596 } else { 1597 desc = ring->desc32; 1598 descsize = sizeof (struct nfe_desc32); 1599 } 1600 1601 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1602 data = &ring->data[i]; 1603 1604 if (data->m != NULL) { 1605 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, 1606 BUS_DMASYNC_POSTWRITE); 1607 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); 1608 m_freem(data->m); 1609 data->m = NULL; 1610 } 1611 if (data->tx_data_map != NULL) { 1612 bus_dmamap_destroy(ring->tx_data_tag, 1613 data->tx_data_map); 1614 data->tx_data_map = NULL; 1615 } 1616 } 1617 1618 if (ring->tx_data_tag != NULL) { 1619 bus_dma_tag_destroy(ring->tx_data_tag); 1620 ring->tx_data_tag = NULL; 1621 } 1622 1623 if (desc != NULL) { 1624 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1625 BUS_DMASYNC_POSTWRITE); 1626 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); 1627 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); 1628 ring->desc64 = NULL; 1629 ring->desc32 = NULL; 1630 bus_dma_tag_destroy(ring->tx_desc_tag); 1631 ring->tx_desc_tag = NULL; 1632 } 1633} 1634 1635#ifdef DEVICE_POLLING 1636static poll_handler_t nfe_poll; 1637 1638 1639static int 1640nfe_poll(if_t ifp, enum poll_cmd cmd, int count) 1641{ 1642 struct nfe_softc *sc = if_getsoftc(ifp); 1643 uint32_t r; 1644 int rx_npkts = 0; 1645 1646 NFE_LOCK(sc); 1647 1648 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1649 NFE_UNLOCK(sc); 1650 return (rx_npkts); 1651 } 1652 1653 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1654 rx_npkts = nfe_jrxeof(sc, count, &rx_npkts); 1655 else 1656 rx_npkts = nfe_rxeof(sc, count, &rx_npkts); 1657 nfe_txeof(sc); 1658 if (!if_sendq_empty(ifp)) 1659 nfe_start_locked(ifp); 1660 1661 if (cmd == POLL_AND_CHECK_STATUS) { 1662 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1663 NFE_UNLOCK(sc); 1664 return (rx_npkts); 1665 } 1666 NFE_WRITE(sc, sc->nfe_irq_status, r); 1667 1668 if (r & NFE_IRQ_LINK) { 1669 NFE_READ(sc, NFE_PHY_STATUS); 1670 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1671 DPRINTF(sc, "link state changed\n"); 1672 } 1673 } 1674 NFE_UNLOCK(sc); 1675 return (rx_npkts); 1676} 1677#endif /* DEVICE_POLLING */ 1678 1679static void 1680nfe_set_intr(struct nfe_softc *sc) 1681{ 1682 1683 if (sc->nfe_msi != 0) 1684 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1685} 1686 1687 1688/* In MSIX, a write to mask reegisters behaves as XOR. */ 1689static __inline void 1690nfe_enable_intr(struct nfe_softc *sc) 1691{ 1692 1693 if (sc->nfe_msix != 0) { 1694 /* XXX Should have a better way to enable interrupts! */ 1695 if (NFE_READ(sc, sc->nfe_irq_mask) == 0) 1696 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1697 } else 1698 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1699} 1700 1701 1702static __inline void 1703nfe_disable_intr(struct nfe_softc *sc) 1704{ 1705 1706 if (sc->nfe_msix != 0) { 1707 /* XXX Should have a better way to disable interrupts! */ 1708 if (NFE_READ(sc, sc->nfe_irq_mask) != 0) 1709 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1710 } else 1711 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1712} 1713 1714 1715static int 1716nfe_ioctl(if_t ifp, u_long cmd, caddr_t data) 1717{ 1718 struct nfe_softc *sc; 1719 struct ifreq *ifr; 1720 struct mii_data *mii; 1721 int error, init, mask; 1722 1723 sc = if_getsoftc(ifp); 1724 ifr = (struct ifreq *) data; 1725 error = 0; 1726 init = 0; 1727 switch (cmd) { 1728 case SIOCSIFMTU: 1729 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) 1730 error = EINVAL; 1731 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1732 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || 1733 (sc->nfe_jumbo_disable != 0)) && 1734 ifr->ifr_mtu > ETHERMTU) 1735 error = EINVAL; 1736 else { 1737 NFE_LOCK(sc); 1738 if_setmtu(ifp, ifr->ifr_mtu); 1739 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1740 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1741 nfe_init_locked(sc); 1742 } 1743 NFE_UNLOCK(sc); 1744 } 1745 } 1746 break; 1747 case SIOCSIFFLAGS: 1748 NFE_LOCK(sc); 1749 if (if_getflags(ifp) & IFF_UP) { 1750 /* 1751 * If only the PROMISC or ALLMULTI flag changes, then 1752 * don't do a full re-init of the chip, just update 1753 * the Rx filter. 1754 */ 1755 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) && 1756 ((if_getflags(ifp) ^ sc->nfe_if_flags) & 1757 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1758 nfe_setmulti(sc); 1759 else 1760 nfe_init_locked(sc); 1761 } else { 1762 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1763 nfe_stop(ifp); 1764 } 1765 sc->nfe_if_flags = if_getflags(ifp); 1766 NFE_UNLOCK(sc); 1767 error = 0; 1768 break; 1769 case SIOCADDMULTI: 1770 case SIOCDELMULTI: 1771 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1772 NFE_LOCK(sc); 1773 nfe_setmulti(sc); 1774 NFE_UNLOCK(sc); 1775 error = 0; 1776 } 1777 break; 1778 case SIOCSIFMEDIA: 1779 case SIOCGIFMEDIA: 1780 mii = device_get_softc(sc->nfe_miibus); 1781 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1782 break; 1783 case SIOCSIFCAP: 1784 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1785#ifdef DEVICE_POLLING 1786 if ((mask & IFCAP_POLLING) != 0) { 1787 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1788 error = ether_poll_register(nfe_poll, ifp); 1789 if (error) 1790 break; 1791 NFE_LOCK(sc); 1792 nfe_disable_intr(sc); 1793 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1794 NFE_UNLOCK(sc); 1795 } else { 1796 error = ether_poll_deregister(ifp); 1797 /* Enable interrupt even in error case */ 1798 NFE_LOCK(sc); 1799 nfe_enable_intr(sc); 1800 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1801 NFE_UNLOCK(sc); 1802 } 1803 } 1804#endif /* DEVICE_POLLING */ 1805 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1806 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1807 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1808 if ((mask & IFCAP_TXCSUM) != 0 && 1809 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1810 if_togglecapenable(ifp, IFCAP_TXCSUM); 1811 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1812 if_sethwassistbits(ifp, NFE_CSUM_FEATURES, 0); 1813 else 1814 if_sethwassistbits(ifp, 0, NFE_CSUM_FEATURES); 1815 } 1816 if ((mask & IFCAP_RXCSUM) != 0 && 1817 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1818 if_togglecapenable(ifp, IFCAP_RXCSUM); 1819 init++; 1820 } 1821 if ((mask & IFCAP_TSO4) != 0 && 1822 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1823 if_togglecapenable(ifp, IFCAP_TSO4); 1824 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1825 if_sethwassistbits(ifp, CSUM_TSO, 0); 1826 else 1827 if_sethwassistbits(ifp, 0, CSUM_TSO); 1828 } 1829 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1830 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1831 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1832 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1833 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1834 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1835 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1836 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1837 init++; 1838 } 1839 /* 1840 * XXX 1841 * It seems that VLAN stripping requires Rx checksum offload. 1842 * Unfortunately FreeBSD has no way to disable only Rx side 1843 * VLAN stripping. So when we know Rx checksum offload is 1844 * disabled turn entire hardware VLAN assist off. 1845 */ 1846 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) == 0) { 1847 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 1848 init++; 1849 if_setcapenablebit(ifp, 0, 1850 (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO)); 1851 } 1852 if (init > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1853 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1854 nfe_init(sc); 1855 } 1856 if_vlancap(ifp); 1857 break; 1858 default: 1859 error = ether_ioctl(ifp, cmd, data); 1860 break; 1861 } 1862 1863 return (error); 1864} 1865 1866 1867static int 1868nfe_intr(void *arg) 1869{ 1870 struct nfe_softc *sc; 1871 uint32_t status; 1872 1873 sc = (struct nfe_softc *)arg; 1874 1875 status = NFE_READ(sc, sc->nfe_irq_status); 1876 if (status == 0 || status == 0xffffffff) 1877 return (FILTER_STRAY); 1878 nfe_disable_intr(sc); 1879 taskqueue_enqueue(sc->nfe_tq, &sc->nfe_int_task); 1880 1881 return (FILTER_HANDLED); 1882} 1883 1884 1885static void 1886nfe_int_task(void *arg, int pending) 1887{ 1888 struct nfe_softc *sc = arg; 1889 if_t ifp = sc->nfe_ifp; 1890 uint32_t r; 1891 int domore; 1892 1893 NFE_LOCK(sc); 1894 1895 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1896 nfe_enable_intr(sc); 1897 NFE_UNLOCK(sc); 1898 return; /* not for us */ 1899 } 1900 NFE_WRITE(sc, sc->nfe_irq_status, r); 1901 1902 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); 1903 1904#ifdef DEVICE_POLLING 1905 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1906 NFE_UNLOCK(sc); 1907 return; 1908 } 1909#endif 1910 1911 if (r & NFE_IRQ_LINK) { 1912 NFE_READ(sc, NFE_PHY_STATUS); 1913 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1914 DPRINTF(sc, "link state changed\n"); 1915 } 1916 1917 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1918 NFE_UNLOCK(sc); 1919 nfe_disable_intr(sc); 1920 return; 1921 } 1922 1923 domore = 0; 1924 /* check Rx ring */ 1925 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1926 domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL); 1927 else 1928 domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL); 1929 /* check Tx ring */ 1930 nfe_txeof(sc); 1931 1932 if (!if_sendq_empty(ifp)) 1933 nfe_start_locked(ifp); 1934 1935 NFE_UNLOCK(sc); 1936 1937 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { 1938 taskqueue_enqueue(sc->nfe_tq, &sc->nfe_int_task); 1939 return; 1940 } 1941 1942 /* Reenable interrupts. */ 1943 nfe_enable_intr(sc); 1944} 1945 1946 1947static __inline void 1948nfe_discard_rxbuf(struct nfe_softc *sc, int idx) 1949{ 1950 struct nfe_desc32 *desc32; 1951 struct nfe_desc64 *desc64; 1952 struct nfe_rx_data *data; 1953 struct mbuf *m; 1954 1955 data = &sc->rxq.data[idx]; 1956 m = data->m; 1957 1958 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1959 desc64 = &sc->rxq.desc64[idx]; 1960 /* VLAN packet may have overwritten it. */ 1961 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1962 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1963 desc64->length = htole16(m->m_len); 1964 desc64->flags = htole16(NFE_RX_READY); 1965 } else { 1966 desc32 = &sc->rxq.desc32[idx]; 1967 desc32->length = htole16(m->m_len); 1968 desc32->flags = htole16(NFE_RX_READY); 1969 } 1970} 1971 1972 1973static __inline void 1974nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) 1975{ 1976 struct nfe_desc32 *desc32; 1977 struct nfe_desc64 *desc64; 1978 struct nfe_rx_data *data; 1979 struct mbuf *m; 1980 1981 data = &sc->jrxq.jdata[idx]; 1982 m = data->m; 1983 1984 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1985 desc64 = &sc->jrxq.jdesc64[idx]; 1986 /* VLAN packet may have overwritten it. */ 1987 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1988 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1989 desc64->length = htole16(m->m_len); 1990 desc64->flags = htole16(NFE_RX_READY); 1991 } else { 1992 desc32 = &sc->jrxq.jdesc32[idx]; 1993 desc32->length = htole16(m->m_len); 1994 desc32->flags = htole16(NFE_RX_READY); 1995 } 1996} 1997 1998 1999static int 2000nfe_newbuf(struct nfe_softc *sc, int idx) 2001{ 2002 struct nfe_rx_data *data; 2003 struct nfe_desc32 *desc32; 2004 struct nfe_desc64 *desc64; 2005 struct mbuf *m; 2006 bus_dma_segment_t segs[1]; 2007 bus_dmamap_t map; 2008 int nsegs; 2009 2010 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2011 if (m == NULL) 2012 return (ENOBUFS); 2013 2014 m->m_len = m->m_pkthdr.len = MCLBYTES; 2015 m_adj(m, ETHER_ALIGN); 2016 2017 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, 2018 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2019 m_freem(m); 2020 return (ENOBUFS); 2021 } 2022 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2023 2024 data = &sc->rxq.data[idx]; 2025 if (data->m != NULL) { 2026 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2027 BUS_DMASYNC_POSTREAD); 2028 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); 2029 } 2030 map = data->rx_data_map; 2031 data->rx_data_map = sc->rxq.rx_spare_map; 2032 sc->rxq.rx_spare_map = map; 2033 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2034 BUS_DMASYNC_PREREAD); 2035 data->paddr = segs[0].ds_addr; 2036 data->m = m; 2037 /* update mapping address in h/w descriptor */ 2038 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2039 desc64 = &sc->rxq.desc64[idx]; 2040 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2041 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2042 desc64->length = htole16(segs[0].ds_len); 2043 desc64->flags = htole16(NFE_RX_READY); 2044 } else { 2045 desc32 = &sc->rxq.desc32[idx]; 2046 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2047 desc32->length = htole16(segs[0].ds_len); 2048 desc32->flags = htole16(NFE_RX_READY); 2049 } 2050 2051 return (0); 2052} 2053 2054 2055static int 2056nfe_jnewbuf(struct nfe_softc *sc, int idx) 2057{ 2058 struct nfe_rx_data *data; 2059 struct nfe_desc32 *desc32; 2060 struct nfe_desc64 *desc64; 2061 struct mbuf *m; 2062 bus_dma_segment_t segs[1]; 2063 bus_dmamap_t map; 2064 int nsegs; 2065 2066 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2067 if (m == NULL) 2068 return (ENOBUFS); 2069 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 2070 m_adj(m, ETHER_ALIGN); 2071 2072 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, 2073 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2074 m_freem(m); 2075 return (ENOBUFS); 2076 } 2077 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2078 2079 data = &sc->jrxq.jdata[idx]; 2080 if (data->m != NULL) { 2081 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2082 BUS_DMASYNC_POSTREAD); 2083 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); 2084 } 2085 map = data->rx_data_map; 2086 data->rx_data_map = sc->jrxq.jrx_spare_map; 2087 sc->jrxq.jrx_spare_map = map; 2088 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2089 BUS_DMASYNC_PREREAD); 2090 data->paddr = segs[0].ds_addr; 2091 data->m = m; 2092 /* update mapping address in h/w descriptor */ 2093 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2094 desc64 = &sc->jrxq.jdesc64[idx]; 2095 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2096 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2097 desc64->length = htole16(segs[0].ds_len); 2098 desc64->flags = htole16(NFE_RX_READY); 2099 } else { 2100 desc32 = &sc->jrxq.jdesc32[idx]; 2101 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2102 desc32->length = htole16(segs[0].ds_len); 2103 desc32->flags = htole16(NFE_RX_READY); 2104 } 2105 2106 return (0); 2107} 2108 2109 2110static int 2111nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2112{ 2113 if_t ifp = sc->nfe_ifp; 2114 struct nfe_desc32 *desc32; 2115 struct nfe_desc64 *desc64; 2116 struct nfe_rx_data *data; 2117 struct mbuf *m; 2118 uint16_t flags; 2119 int len, prog, rx_npkts; 2120 uint32_t vtag = 0; 2121 2122 rx_npkts = 0; 2123 NFE_LOCK_ASSERT(sc); 2124 2125 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2126 BUS_DMASYNC_POSTREAD); 2127 2128 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { 2129 if (count <= 0) 2130 break; 2131 count--; 2132 2133 data = &sc->rxq.data[sc->rxq.cur]; 2134 2135 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2136 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 2137 vtag = le32toh(desc64->physaddr[1]); 2138 flags = le16toh(desc64->flags); 2139 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2140 } else { 2141 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 2142 flags = le16toh(desc32->flags); 2143 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2144 } 2145 2146 if (flags & NFE_RX_READY) 2147 break; 2148 prog++; 2149 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2150 if (!(flags & NFE_RX_VALID_V1)) { 2151 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2152 nfe_discard_rxbuf(sc, sc->rxq.cur); 2153 continue; 2154 } 2155 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2156 flags &= ~NFE_RX_ERROR; 2157 len--; /* fix buffer length */ 2158 } 2159 } else { 2160 if (!(flags & NFE_RX_VALID_V2)) { 2161 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2162 nfe_discard_rxbuf(sc, sc->rxq.cur); 2163 continue; 2164 } 2165 2166 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2167 flags &= ~NFE_RX_ERROR; 2168 len--; /* fix buffer length */ 2169 } 2170 } 2171 2172 if (flags & NFE_RX_ERROR) { 2173 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2174 nfe_discard_rxbuf(sc, sc->rxq.cur); 2175 continue; 2176 } 2177 2178 m = data->m; 2179 if (nfe_newbuf(sc, sc->rxq.cur) != 0) { 2180 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2181 nfe_discard_rxbuf(sc, sc->rxq.cur); 2182 continue; 2183 } 2184 2185 if ((vtag & NFE_RX_VTAG) != 0 && 2186 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2187 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2188 m->m_flags |= M_VLANTAG; 2189 } 2190 2191 m->m_pkthdr.len = m->m_len = len; 2192 m->m_pkthdr.rcvif = ifp; 2193 2194 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 2195 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2196 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2197 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2198 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2199 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2200 m->m_pkthdr.csum_flags |= 2201 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2202 m->m_pkthdr.csum_data = 0xffff; 2203 } 2204 } 2205 } 2206 2207 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2208 2209 NFE_UNLOCK(sc); 2210 if_input(ifp, m); 2211 NFE_LOCK(sc); 2212 rx_npkts++; 2213 } 2214 2215 if (prog > 0) 2216 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2217 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2218 2219 if (rx_npktsp != NULL) 2220 *rx_npktsp = rx_npkts; 2221 return (count > 0 ? 0 : EAGAIN); 2222} 2223 2224 2225static int 2226nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2227{ 2228 if_t ifp = sc->nfe_ifp; 2229 struct nfe_desc32 *desc32; 2230 struct nfe_desc64 *desc64; 2231 struct nfe_rx_data *data; 2232 struct mbuf *m; 2233 uint16_t flags; 2234 int len, prog, rx_npkts; 2235 uint32_t vtag = 0; 2236 2237 rx_npkts = 0; 2238 NFE_LOCK_ASSERT(sc); 2239 2240 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2241 BUS_DMASYNC_POSTREAD); 2242 2243 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), 2244 vtag = 0) { 2245 if (count <= 0) 2246 break; 2247 count--; 2248 2249 data = &sc->jrxq.jdata[sc->jrxq.jcur]; 2250 2251 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2252 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; 2253 vtag = le32toh(desc64->physaddr[1]); 2254 flags = le16toh(desc64->flags); 2255 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2256 } else { 2257 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; 2258 flags = le16toh(desc32->flags); 2259 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2260 } 2261 2262 if (flags & NFE_RX_READY) 2263 break; 2264 prog++; 2265 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2266 if (!(flags & NFE_RX_VALID_V1)) { 2267 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2268 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2269 continue; 2270 } 2271 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2272 flags &= ~NFE_RX_ERROR; 2273 len--; /* fix buffer length */ 2274 } 2275 } else { 2276 if (!(flags & NFE_RX_VALID_V2)) { 2277 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2278 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2279 continue; 2280 } 2281 2282 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2283 flags &= ~NFE_RX_ERROR; 2284 len--; /* fix buffer length */ 2285 } 2286 } 2287 2288 if (flags & NFE_RX_ERROR) { 2289 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2290 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2291 continue; 2292 } 2293 2294 m = data->m; 2295 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { 2296 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2297 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2298 continue; 2299 } 2300 2301 if ((vtag & NFE_RX_VTAG) != 0 && 2302 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2303 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2304 m->m_flags |= M_VLANTAG; 2305 } 2306 2307 m->m_pkthdr.len = m->m_len = len; 2308 m->m_pkthdr.rcvif = ifp; 2309 2310 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 2311 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2312 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2313 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2314 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2315 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2316 m->m_pkthdr.csum_flags |= 2317 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2318 m->m_pkthdr.csum_data = 0xffff; 2319 } 2320 } 2321 } 2322 2323 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2324 2325 NFE_UNLOCK(sc); 2326 if_input(ifp, m); 2327 NFE_LOCK(sc); 2328 rx_npkts++; 2329 } 2330 2331 if (prog > 0) 2332 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2333 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2334 2335 if (rx_npktsp != NULL) 2336 *rx_npktsp = rx_npkts; 2337 return (count > 0 ? 0 : EAGAIN); 2338} 2339 2340 2341static void 2342nfe_txeof(struct nfe_softc *sc) 2343{ 2344 if_t ifp = sc->nfe_ifp; 2345 struct nfe_desc32 *desc32; 2346 struct nfe_desc64 *desc64; 2347 struct nfe_tx_data *data = NULL; 2348 uint16_t flags; 2349 int cons, prog; 2350 2351 NFE_LOCK_ASSERT(sc); 2352 2353 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2354 BUS_DMASYNC_POSTREAD); 2355 2356 prog = 0; 2357 for (cons = sc->txq.next; cons != sc->txq.cur; 2358 NFE_INC(cons, NFE_TX_RING_COUNT)) { 2359 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2360 desc64 = &sc->txq.desc64[cons]; 2361 flags = le16toh(desc64->flags); 2362 } else { 2363 desc32 = &sc->txq.desc32[cons]; 2364 flags = le16toh(desc32->flags); 2365 } 2366 2367 if (flags & NFE_TX_VALID) 2368 break; 2369 2370 prog++; 2371 sc->txq.queued--; 2372 data = &sc->txq.data[cons]; 2373 2374 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2375 if ((flags & NFE_TX_LASTFRAG_V1) == 0) 2376 continue; 2377 if ((flags & NFE_TX_ERROR_V1) != 0) { 2378 device_printf(sc->nfe_dev, 2379 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); 2380 2381 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2382 } else 2383 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2384 } else { 2385 if ((flags & NFE_TX_LASTFRAG_V2) == 0) 2386 continue; 2387 if ((flags & NFE_TX_ERROR_V2) != 0) { 2388 device_printf(sc->nfe_dev, 2389 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); 2390 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2391 } else 2392 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2393 } 2394 2395 /* last fragment of the mbuf chain transmitted */ 2396 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); 2397 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, 2398 BUS_DMASYNC_POSTWRITE); 2399 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); 2400 m_freem(data->m); 2401 data->m = NULL; 2402 } 2403 2404 if (prog > 0) { 2405 sc->nfe_force_tx = 0; 2406 sc->txq.next = cons; 2407 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2408 if (sc->txq.queued == 0) 2409 sc->nfe_watchdog_timer = 0; 2410 } 2411} 2412 2413static int 2414nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) 2415{ 2416 struct nfe_desc32 *desc32 = NULL; 2417 struct nfe_desc64 *desc64 = NULL; 2418 bus_dmamap_t map; 2419 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 2420 int error, i, nsegs, prod, si; 2421 uint32_t tsosegsz; 2422 uint16_t cflags, flags; 2423 struct mbuf *m; 2424 2425 prod = si = sc->txq.cur; 2426 map = sc->txq.data[prod].tx_data_map; 2427 2428 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, 2429 &nsegs, BUS_DMA_NOWAIT); 2430 if (error == EFBIG) { 2431 m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER); 2432 if (m == NULL) { 2433 m_freem(*m_head); 2434 *m_head = NULL; 2435 return (ENOBUFS); 2436 } 2437 *m_head = m; 2438 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, 2439 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2440 if (error != 0) { 2441 m_freem(*m_head); 2442 *m_head = NULL; 2443 return (ENOBUFS); 2444 } 2445 } else if (error != 0) 2446 return (error); 2447 if (nsegs == 0) { 2448 m_freem(*m_head); 2449 *m_head = NULL; 2450 return (EIO); 2451 } 2452 2453 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { 2454 bus_dmamap_unload(sc->txq.tx_data_tag, map); 2455 return (ENOBUFS); 2456 } 2457 2458 m = *m_head; 2459 cflags = flags = 0; 2460 tsosegsz = 0; 2461 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2462 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 2463 NFE_TX_TSO_SHIFT; 2464 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 2465 cflags |= NFE_TX_TSO; 2466 } else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { 2467 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2468 cflags |= NFE_TX_IP_CSUM; 2469 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2470 cflags |= NFE_TX_TCP_UDP_CSUM; 2471 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2472 cflags |= NFE_TX_TCP_UDP_CSUM; 2473 } 2474 2475 for (i = 0; i < nsegs; i++) { 2476 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2477 desc64 = &sc->txq.desc64[prod]; 2478 desc64->physaddr[0] = 2479 htole32(NFE_ADDR_HI(segs[i].ds_addr)); 2480 desc64->physaddr[1] = 2481 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2482 desc64->vtag = 0; 2483 desc64->length = htole16(segs[i].ds_len - 1); 2484 desc64->flags = htole16(flags); 2485 } else { 2486 desc32 = &sc->txq.desc32[prod]; 2487 desc32->physaddr = 2488 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2489 desc32->length = htole16(segs[i].ds_len - 1); 2490 desc32->flags = htole16(flags); 2491 } 2492 2493 /* 2494 * Setting of the valid bit in the first descriptor is 2495 * deferred until the whole chain is fully setup. 2496 */ 2497 flags |= NFE_TX_VALID; 2498 2499 sc->txq.queued++; 2500 NFE_INC(prod, NFE_TX_RING_COUNT); 2501 } 2502 2503 /* 2504 * the whole mbuf chain has been DMA mapped, fix last/first descriptor. 2505 * csum flags, vtag and TSO belong to the first fragment only. 2506 */ 2507 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2508 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 2509 desc64 = &sc->txq.desc64[si]; 2510 if ((m->m_flags & M_VLANTAG) != 0) 2511 desc64->vtag = htole32(NFE_TX_VTAG | 2512 m->m_pkthdr.ether_vtag); 2513 if (tsosegsz != 0) { 2514 /* 2515 * XXX 2516 * The following indicates the descriptor element 2517 * is a 32bit quantity. 2518 */ 2519 desc64->length |= htole16((uint16_t)tsosegsz); 2520 desc64->flags |= htole16(tsosegsz >> 16); 2521 } 2522 /* 2523 * finally, set the valid/checksum/TSO bit in the first 2524 * descriptor. 2525 */ 2526 desc64->flags |= htole16(NFE_TX_VALID | cflags); 2527 } else { 2528 if (sc->nfe_flags & NFE_JUMBO_SUP) 2529 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); 2530 else 2531 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); 2532 desc32 = &sc->txq.desc32[si]; 2533 if (tsosegsz != 0) { 2534 /* 2535 * XXX 2536 * The following indicates the descriptor element 2537 * is a 32bit quantity. 2538 */ 2539 desc32->length |= htole16((uint16_t)tsosegsz); 2540 desc32->flags |= htole16(tsosegsz >> 16); 2541 } 2542 /* 2543 * finally, set the valid/checksum/TSO bit in the first 2544 * descriptor. 2545 */ 2546 desc32->flags |= htole16(NFE_TX_VALID | cflags); 2547 } 2548 2549 sc->txq.cur = prod; 2550 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; 2551 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; 2552 sc->txq.data[prod].tx_data_map = map; 2553 sc->txq.data[prod].m = m; 2554 2555 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); 2556 2557 return (0); 2558} 2559 2560 2561static void 2562nfe_setmulti(struct nfe_softc *sc) 2563{ 2564 if_t ifp = sc->nfe_ifp; 2565 int i, mc_count, mcnt; 2566 uint32_t filter; 2567 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; 2568 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { 2569 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2570 }; 2571 uint8_t *mta; 2572 2573 NFE_LOCK_ASSERT(sc); 2574 2575 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2576 bzero(addr, ETHER_ADDR_LEN); 2577 bzero(mask, ETHER_ADDR_LEN); 2578 goto done; 2579 } 2580 2581 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); 2582 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); 2583 2584 mc_count = if_multiaddr_count(ifp, -1); 2585 mta = malloc(sizeof(uint8_t) * ETHER_ADDR_LEN * mc_count, M_DEVBUF, 2586 M_NOWAIT); 2587 2588 /* Unable to get memory - process without filtering */ 2589 if (mta == NULL) { 2590 device_printf(sc->nfe_dev, "nfe_setmulti: failed to allocate" 2591 "temp multicast buffer!\n"); 2592 2593 bzero(addr, ETHER_ADDR_LEN); 2594 bzero(mask, ETHER_ADDR_LEN); 2595 goto done; 2596 } 2597 2598 if_multiaddr_array(ifp, mta, &mcnt, mc_count); 2599 2600 for (i = 0; i < mcnt; i++) { 2601 uint8_t *addrp; 2602 int j; 2603 2604 addrp = mta + (i * ETHER_ADDR_LEN); 2605 for (j = 0; j < ETHER_ADDR_LEN; j++) { 2606 u_int8_t mcaddr = addrp[j]; 2607 addr[j] &= mcaddr; 2608 mask[j] &= ~mcaddr; 2609 } 2610 } 2611 2612 free(mta, M_DEVBUF); 2613 2614 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2615 mask[i] |= addr[i]; 2616 } 2617 2618done: 2619 addr[0] |= 0x01; /* make sure multicast bit is set */ 2620 2621 NFE_WRITE(sc, NFE_MULTIADDR_HI, 2622 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 2623 NFE_WRITE(sc, NFE_MULTIADDR_LO, 2624 addr[5] << 8 | addr[4]); 2625 NFE_WRITE(sc, NFE_MULTIMASK_HI, 2626 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); 2627 NFE_WRITE(sc, NFE_MULTIMASK_LO, 2628 mask[5] << 8 | mask[4]); 2629 2630 filter = NFE_READ(sc, NFE_RXFILTER); 2631 filter &= NFE_PFF_RX_PAUSE; 2632 filter |= NFE_RXFILTER_MAGIC; 2633 filter |= (if_getflags(ifp) & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; 2634 NFE_WRITE(sc, NFE_RXFILTER, filter); 2635} 2636 2637 2638static void 2639nfe_start(if_t ifp) 2640{ 2641 struct nfe_softc *sc = if_getsoftc(ifp); 2642 2643 NFE_LOCK(sc); 2644 nfe_start_locked(ifp); 2645 NFE_UNLOCK(sc); 2646} 2647 2648static void 2649nfe_start_locked(if_t ifp) 2650{ 2651 struct nfe_softc *sc = if_getsoftc(ifp); 2652 struct mbuf *m0; 2653 int enq = 0; 2654 2655 NFE_LOCK_ASSERT(sc); 2656 2657 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2658 IFF_DRV_RUNNING || sc->nfe_link == 0) 2659 return; 2660 2661 while (!if_sendq_empty(ifp)) { 2662 m0 = if_dequeue(ifp); 2663 2664 if (m0 == NULL) 2665 break; 2666 2667 if (nfe_encap(sc, &m0) != 0) { 2668 if (m0 == NULL) 2669 break; 2670 if_sendq_prepend(ifp, m0); 2671 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2672 break; 2673 } 2674 enq++; 2675 if_etherbpfmtap(ifp, m0); 2676 } 2677 2678 if (enq > 0) { 2679 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2681 2682 /* kick Tx */ 2683 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2684 2685 /* 2686 * Set a timeout in case the chip goes out to lunch. 2687 */ 2688 sc->nfe_watchdog_timer = 5; 2689 } 2690} 2691 2692 2693static void 2694nfe_watchdog(if_t ifp) 2695{ 2696 struct nfe_softc *sc = if_getsoftc(ifp); 2697 2698 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) 2699 return; 2700 2701 /* Check if we've lost Tx completion interrupt. */ 2702 nfe_txeof(sc); 2703 if (sc->txq.queued == 0) { 2704 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2705 "-- recovering\n"); 2706 if (!if_sendq_empty(ifp)) 2707 nfe_start_locked(ifp); 2708 return; 2709 } 2710 /* Check if we've lost start Tx command. */ 2711 sc->nfe_force_tx++; 2712 if (sc->nfe_force_tx <= 3) { 2713 /* 2714 * If this is the case for watchdog timeout, the following 2715 * code should go to nfe_txeof(). 2716 */ 2717 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2718 return; 2719 } 2720 sc->nfe_force_tx = 0; 2721 2722 if_printf(ifp, "watchdog timeout\n"); 2723 2724 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2725 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2726 nfe_init_locked(sc); 2727} 2728 2729 2730static void 2731nfe_init(void *xsc) 2732{ 2733 struct nfe_softc *sc = xsc; 2734 2735 NFE_LOCK(sc); 2736 nfe_init_locked(sc); 2737 NFE_UNLOCK(sc); 2738} 2739 2740 2741static void 2742nfe_init_locked(void *xsc) 2743{ 2744 struct nfe_softc *sc = xsc; 2745 if_t ifp = sc->nfe_ifp; 2746 struct mii_data *mii; 2747 uint32_t val; 2748 int error; 2749 2750 NFE_LOCK_ASSERT(sc); 2751 2752 mii = device_get_softc(sc->nfe_miibus); 2753 2754 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2755 return; 2756 2757 nfe_stop(ifp); 2758 2759 sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS; 2760 2761 nfe_init_tx_ring(sc, &sc->txq); 2762 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) 2763 error = nfe_init_jrx_ring(sc, &sc->jrxq); 2764 else 2765 error = nfe_init_rx_ring(sc, &sc->rxq); 2766 if (error != 0) { 2767 device_printf(sc->nfe_dev, 2768 "initialization failed: no memory for rx buffers\n"); 2769 nfe_stop(ifp); 2770 return; 2771 } 2772 2773 val = 0; 2774 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) 2775 val |= NFE_MAC_ADDR_INORDER; 2776 NFE_WRITE(sc, NFE_TX_UNK, val); 2777 NFE_WRITE(sc, NFE_STATUS, 0); 2778 2779 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) 2780 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); 2781 2782 sc->rxtxctl = NFE_RXTX_BIT2; 2783 if (sc->nfe_flags & NFE_40BIT_ADDR) 2784 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 2785 else if (sc->nfe_flags & NFE_JUMBO_SUP) 2786 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 2787 2788 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2789 sc->rxtxctl |= NFE_RXTX_RXCSUM; 2790 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2791 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 2792 2793 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 2794 DELAY(10); 2795 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2796 2797 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2798 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 2799 else 2800 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 2801 2802 NFE_WRITE(sc, NFE_SETUP_R6, 0); 2803 2804 /* set MAC address */ 2805 nfe_set_macaddr(sc, if_getlladdr(ifp)); 2806 2807 /* tell MAC where rings are in memory */ 2808 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { 2809 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2810 NFE_ADDR_HI(sc->jrxq.jphysaddr)); 2811 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2812 NFE_ADDR_LO(sc->jrxq.jphysaddr)); 2813 } else { 2814 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2815 NFE_ADDR_HI(sc->rxq.physaddr)); 2816 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2817 NFE_ADDR_LO(sc->rxq.physaddr)); 2818 } 2819 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); 2820 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); 2821 2822 NFE_WRITE(sc, NFE_RING_SIZE, 2823 (NFE_RX_RING_COUNT - 1) << 16 | 2824 (NFE_TX_RING_COUNT - 1)); 2825 2826 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); 2827 2828 /* force MAC to wakeup */ 2829 val = NFE_READ(sc, NFE_PWR_STATE); 2830 if ((val & NFE_PWR_WAKEUP) == 0) 2831 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); 2832 DELAY(10); 2833 val = NFE_READ(sc, NFE_PWR_STATE); 2834 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); 2835 2836#if 1 2837 /* configure interrupts coalescing/mitigation */ 2838 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 2839#else 2840 /* no interrupt mitigation: one interrupt per packet */ 2841 NFE_WRITE(sc, NFE_IMTIMER, 970); 2842#endif 2843 2844 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); 2845 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 2846 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 2847 2848 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 2849 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 2850 2851 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 2852 /* Disable WOL. */ 2853 NFE_WRITE(sc, NFE_WOL_CTL, 0); 2854 2855 sc->rxtxctl &= ~NFE_RXTX_BIT2; 2856 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2857 DELAY(10); 2858 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 2859 2860 /* set Rx filter */ 2861 nfe_setmulti(sc); 2862 2863 /* enable Rx */ 2864 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 2865 2866 /* enable Tx */ 2867 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 2868 2869 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 2870 2871 /* Clear hardware stats. */ 2872 nfe_stats_clear(sc); 2873 2874#ifdef DEVICE_POLLING 2875 if (if_getcapenable(ifp) & IFCAP_POLLING) 2876 nfe_disable_intr(sc); 2877 else 2878#endif 2879 nfe_set_intr(sc); 2880 nfe_enable_intr(sc); /* enable interrupts */ 2881 2882 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2883 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2884 2885 sc->nfe_link = 0; 2886 mii_mediachg(mii); 2887 2888 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2889} 2890 2891 2892static void 2893nfe_stop(if_t ifp) 2894{ 2895 struct nfe_softc *sc = if_getsoftc(ifp); 2896 struct nfe_rx_ring *rx_ring; 2897 struct nfe_jrx_ring *jrx_ring; 2898 struct nfe_tx_ring *tx_ring; 2899 struct nfe_rx_data *rdata; 2900 struct nfe_tx_data *tdata; 2901 int i; 2902 2903 NFE_LOCK_ASSERT(sc); 2904 2905 sc->nfe_watchdog_timer = 0; 2906 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2907 2908 callout_stop(&sc->nfe_stat_ch); 2909 2910 /* abort Tx */ 2911 NFE_WRITE(sc, NFE_TX_CTL, 0); 2912 2913 /* disable Rx */ 2914 NFE_WRITE(sc, NFE_RX_CTL, 0); 2915 2916 /* disable interrupts */ 2917 nfe_disable_intr(sc); 2918 2919 sc->nfe_link = 0; 2920 2921 /* free Rx and Tx mbufs still in the queues. */ 2922 rx_ring = &sc->rxq; 2923 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2924 rdata = &rx_ring->data[i]; 2925 if (rdata->m != NULL) { 2926 bus_dmamap_sync(rx_ring->rx_data_tag, 2927 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2928 bus_dmamap_unload(rx_ring->rx_data_tag, 2929 rdata->rx_data_map); 2930 m_freem(rdata->m); 2931 rdata->m = NULL; 2932 } 2933 } 2934 2935 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { 2936 jrx_ring = &sc->jrxq; 2937 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 2938 rdata = &jrx_ring->jdata[i]; 2939 if (rdata->m != NULL) { 2940 bus_dmamap_sync(jrx_ring->jrx_data_tag, 2941 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2942 bus_dmamap_unload(jrx_ring->jrx_data_tag, 2943 rdata->rx_data_map); 2944 m_freem(rdata->m); 2945 rdata->m = NULL; 2946 } 2947 } 2948 } 2949 2950 tx_ring = &sc->txq; 2951 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2952 tdata = &tx_ring->data[i]; 2953 if (tdata->m != NULL) { 2954 bus_dmamap_sync(tx_ring->tx_data_tag, 2955 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); 2956 bus_dmamap_unload(tx_ring->tx_data_tag, 2957 tdata->tx_data_map); 2958 m_freem(tdata->m); 2959 tdata->m = NULL; 2960 } 2961 } 2962 /* Update hardware stats. */ 2963 nfe_stats_update(sc); 2964} 2965 2966 2967static int 2968nfe_ifmedia_upd(if_t ifp) 2969{ 2970 struct nfe_softc *sc = if_getsoftc(ifp); 2971 struct mii_data *mii; 2972 2973 NFE_LOCK(sc); 2974 mii = device_get_softc(sc->nfe_miibus); 2975 mii_mediachg(mii); 2976 NFE_UNLOCK(sc); 2977 2978 return (0); 2979} 2980 2981 2982static void 2983nfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2984{ 2985 struct nfe_softc *sc; 2986 struct mii_data *mii; 2987 2988 sc = if_getsoftc(ifp); 2989 2990 NFE_LOCK(sc); 2991 mii = device_get_softc(sc->nfe_miibus); 2992 mii_pollstat(mii); 2993 2994 ifmr->ifm_active = mii->mii_media_active; 2995 ifmr->ifm_status = mii->mii_media_status; 2996 NFE_UNLOCK(sc); 2997} 2998 2999 3000void 3001nfe_tick(void *xsc) 3002{ 3003 struct nfe_softc *sc; 3004 struct mii_data *mii; 3005 if_t ifp; 3006 3007 sc = (struct nfe_softc *)xsc; 3008 3009 NFE_LOCK_ASSERT(sc); 3010 3011 ifp = sc->nfe_ifp; 3012 3013 mii = device_get_softc(sc->nfe_miibus); 3014 mii_tick(mii); 3015 nfe_stats_update(sc); 3016 nfe_watchdog(ifp); 3017 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 3018} 3019 3020 3021static int 3022nfe_shutdown(device_t dev) 3023{ 3024 3025 return (nfe_suspend(dev)); 3026} 3027 3028 3029static void 3030nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 3031{ 3032 uint32_t val; 3033 3034 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 3035 val = NFE_READ(sc, NFE_MACADDR_LO); 3036 addr[0] = (val >> 8) & 0xff; 3037 addr[1] = (val & 0xff); 3038 3039 val = NFE_READ(sc, NFE_MACADDR_HI); 3040 addr[2] = (val >> 24) & 0xff; 3041 addr[3] = (val >> 16) & 0xff; 3042 addr[4] = (val >> 8) & 0xff; 3043 addr[5] = (val & 0xff); 3044 } else { 3045 val = NFE_READ(sc, NFE_MACADDR_LO); 3046 addr[5] = (val >> 8) & 0xff; 3047 addr[4] = (val & 0xff); 3048 3049 val = NFE_READ(sc, NFE_MACADDR_HI); 3050 addr[3] = (val >> 24) & 0xff; 3051 addr[2] = (val >> 16) & 0xff; 3052 addr[1] = (val >> 8) & 0xff; 3053 addr[0] = (val & 0xff); 3054 } 3055} 3056 3057 3058static void 3059nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) 3060{ 3061 3062 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); 3063 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | 3064 addr[1] << 8 | addr[0]); 3065} 3066 3067 3068/* 3069 * Map a single buffer address. 3070 */ 3071 3072static void 3073nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3074{ 3075 struct nfe_dmamap_arg *ctx; 3076 3077 if (error != 0) 3078 return; 3079 3080 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 3081 3082 ctx = (struct nfe_dmamap_arg *)arg; 3083 ctx->nfe_busaddr = segs[0].ds_addr; 3084} 3085 3086 3087static int 3088sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3089{ 3090 int error, value; 3091 3092 if (!arg1) 3093 return (EINVAL); 3094 value = *(int *)arg1; 3095 error = sysctl_handle_int(oidp, &value, 0, req); 3096 if (error || !req->newptr) 3097 return (error); 3098 if (value < low || value > high) 3099 return (EINVAL); 3100 *(int *)arg1 = value; 3101 3102 return (0); 3103} 3104 3105 3106static int 3107sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) 3108{ 3109 3110 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, 3111 NFE_PROC_MAX)); 3112} 3113 3114 3115#define NFE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 3116 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3117#define NFE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 3118 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 3119 3120static void 3121nfe_sysctl_node(struct nfe_softc *sc) 3122{ 3123 struct sysctl_ctx_list *ctx; 3124 struct sysctl_oid_list *child, *parent; 3125 struct sysctl_oid *tree; 3126 struct nfe_hw_stats *stats; 3127 int error; 3128 3129 stats = &sc->nfe_stats; 3130 ctx = device_get_sysctl_ctx(sc->nfe_dev); 3131 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev)); 3132 SYSCTL_ADD_PROC(ctx, child, 3133 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 3134 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", 3135 "max number of Rx events to process"); 3136 3137 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3138 error = resource_int_value(device_get_name(sc->nfe_dev), 3139 device_get_unit(sc->nfe_dev), "process_limit", 3140 &sc->nfe_process_limit); 3141 if (error == 0) { 3142 if (sc->nfe_process_limit < NFE_PROC_MIN || 3143 sc->nfe_process_limit > NFE_PROC_MAX) { 3144 device_printf(sc->nfe_dev, 3145 "process_limit value out of range; " 3146 "using default: %d\n", NFE_PROC_DEFAULT); 3147 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3148 } 3149 } 3150 3151 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3152 return; 3153 3154 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 3155 NULL, "NFE statistics"); 3156 parent = SYSCTL_CHILDREN(tree); 3157 3158 /* Rx statistics. */ 3159 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 3160 NULL, "Rx MAC statistics"); 3161 child = SYSCTL_CHILDREN(tree); 3162 3163 NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors", 3164 &stats->rx_frame_errors, "Framing Errors"); 3165 NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes", 3166 &stats->rx_extra_bytes, "Extra Bytes"); 3167 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3168 &stats->rx_late_cols, "Late Collisions"); 3169 NFE_SYSCTL_STAT_ADD32(ctx, child, "runts", 3170 &stats->rx_runts, "Runts"); 3171 NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos", 3172 &stats->rx_jumbos, "Jumbos"); 3173 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns", 3174 &stats->rx_fifo_overuns, "FIFO Overruns"); 3175 NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors", 3176 &stats->rx_crc_errors, "CRC Errors"); 3177 NFE_SYSCTL_STAT_ADD32(ctx, child, "fae", 3178 &stats->rx_fae, "Frame Alignment Errors"); 3179 NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors", 3180 &stats->rx_len_errors, "Length Errors"); 3181 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3182 &stats->rx_unicast, "Unicast Frames"); 3183 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3184 &stats->rx_multicast, "Multicast Frames"); 3185 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3186 &stats->rx_broadcast, "Broadcast Frames"); 3187 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3188 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3189 &stats->rx_octets, "Octets"); 3190 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3191 &stats->rx_pause, "Pause frames"); 3192 NFE_SYSCTL_STAT_ADD32(ctx, child, "drops", 3193 &stats->rx_drops, "Drop frames"); 3194 } 3195 3196 /* Tx statistics. */ 3197 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 3198 NULL, "Tx MAC statistics"); 3199 child = SYSCTL_CHILDREN(tree); 3200 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3201 &stats->tx_octets, "Octets"); 3202 NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits", 3203 &stats->tx_zero_rexmits, "Zero Retransmits"); 3204 NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits", 3205 &stats->tx_one_rexmits, "One Retransmits"); 3206 NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits", 3207 &stats->tx_multi_rexmits, "Multiple Retransmits"); 3208 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3209 &stats->tx_late_cols, "Late Collisions"); 3210 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns", 3211 &stats->tx_fifo_underuns, "FIFO Underruns"); 3212 NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts", 3213 &stats->tx_carrier_losts, "Carrier Losts"); 3214 NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals", 3215 &stats->tx_excess_deferals, "Excess Deferrals"); 3216 NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors", 3217 &stats->tx_retry_errors, "Retry Errors"); 3218 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3219 NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals", 3220 &stats->tx_deferals, "Deferrals"); 3221 NFE_SYSCTL_STAT_ADD32(ctx, child, "frames", 3222 &stats->tx_frames, "Frames"); 3223 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3224 &stats->tx_pause, "Pause Frames"); 3225 } 3226 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3227 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3228 &stats->tx_deferals, "Unicast Frames"); 3229 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3230 &stats->tx_frames, "Multicast Frames"); 3231 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3232 &stats->tx_pause, "Broadcast Frames"); 3233 } 3234} 3235 3236#undef NFE_SYSCTL_STAT_ADD32 3237#undef NFE_SYSCTL_STAT_ADD64 3238 3239static void 3240nfe_stats_clear(struct nfe_softc *sc) 3241{ 3242 int i, mib_cnt; 3243 3244 if ((sc->nfe_flags & NFE_MIB_V1) != 0) 3245 mib_cnt = NFE_NUM_MIB_STATV1; 3246 else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0) 3247 mib_cnt = NFE_NUM_MIB_STATV2; 3248 else 3249 return; 3250 3251 for (i = 0; i < mib_cnt; i++) 3252 NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t)); 3253 3254 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3255 NFE_READ(sc, NFE_TX_UNICAST); 3256 NFE_READ(sc, NFE_TX_MULTICAST); 3257 NFE_READ(sc, NFE_TX_BROADCAST); 3258 } 3259} 3260 3261static void 3262nfe_stats_update(struct nfe_softc *sc) 3263{ 3264 struct nfe_hw_stats *stats; 3265 3266 NFE_LOCK_ASSERT(sc); 3267 3268 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3269 return; 3270 3271 stats = &sc->nfe_stats; 3272 stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET); 3273 stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT); 3274 stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT); 3275 stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT); 3276 stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL); 3277 stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN); 3278 stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST); 3279 stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL); 3280 stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR); 3281 stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR); 3282 stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES); 3283 stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL); 3284 stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT); 3285 stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO); 3286 stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN); 3287 stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR); 3288 stats->rx_fae += NFE_READ(sc, NFE_RX_FAE); 3289 stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR); 3290 stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST); 3291 stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST); 3292 stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST); 3293 3294 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3295 stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL); 3296 stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME); 3297 stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET); 3298 stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE); 3299 stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE); 3300 stats->rx_drops += NFE_READ(sc, NFE_RX_DROP); 3301 } 3302 3303 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3304 stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST); 3305 stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST); 3306 stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST); 3307 } 3308} 3309 3310 3311static void 3312nfe_set_linkspeed(struct nfe_softc *sc) 3313{ 3314 struct mii_softc *miisc; 3315 struct mii_data *mii; 3316 int aneg, i, phyno; 3317 3318 NFE_LOCK_ASSERT(sc); 3319 3320 mii = device_get_softc(sc->nfe_miibus); 3321 mii_pollstat(mii); 3322 aneg = 0; 3323 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3324 (IFM_ACTIVE | IFM_AVALID)) { 3325 switch IFM_SUBTYPE(mii->mii_media_active) { 3326 case IFM_10_T: 3327 case IFM_100_TX: 3328 return; 3329 case IFM_1000_T: 3330 aneg++; 3331 break; 3332 default: 3333 break; 3334 } 3335 } 3336 miisc = LIST_FIRST(&mii->mii_phys); 3337 phyno = miisc->mii_phy; 3338 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3339 PHY_RESET(miisc); 3340 nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0); 3341 nfe_miibus_writereg(sc->nfe_dev, phyno, 3342 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3343 nfe_miibus_writereg(sc->nfe_dev, phyno, 3344 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 3345 DELAY(1000); 3346 if (aneg != 0) { 3347 /* 3348 * Poll link state until nfe(4) get a 10/100Mbps link. 3349 */ 3350 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3351 mii_pollstat(mii); 3352 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3353 == (IFM_ACTIVE | IFM_AVALID)) { 3354 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3355 case IFM_10_T: 3356 case IFM_100_TX: 3357 nfe_mac_config(sc, mii); 3358 return; 3359 default: 3360 break; 3361 } 3362 } 3363 NFE_UNLOCK(sc); 3364 pause("nfelnk", hz); 3365 NFE_LOCK(sc); 3366 } 3367 if (i == MII_ANEGTICKS_GIGE) 3368 device_printf(sc->nfe_dev, 3369 "establishing a link failed, WOL may not work!"); 3370 } 3371 /* 3372 * No link, force MAC to have 100Mbps, full-duplex link. 3373 * This is the last resort and may/may not work. 3374 */ 3375 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3376 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3377 nfe_mac_config(sc, mii); 3378} 3379 3380 3381static void 3382nfe_set_wol(struct nfe_softc *sc) 3383{ 3384 if_t ifp; 3385 uint32_t wolctl; 3386 int pmc; 3387 uint16_t pmstat; 3388 3389 NFE_LOCK_ASSERT(sc); 3390 3391 if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) 3392 return; 3393 ifp = sc->nfe_ifp; 3394 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3395 wolctl = NFE_WOL_MAGIC; 3396 else 3397 wolctl = 0; 3398 NFE_WRITE(sc, NFE_WOL_CTL, wolctl); 3399 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 3400 nfe_set_linkspeed(sc); 3401 if ((sc->nfe_flags & NFE_PWR_MGMT) != 0) 3402 NFE_WRITE(sc, NFE_PWR2_CTL, 3403 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS); 3404 /* Enable RX. */ 3405 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0); 3406 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0); 3407 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) | 3408 NFE_RX_START); 3409 } 3410 /* Request PME if WOL is requested. */ 3411 pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2); 3412 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3413 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3414 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3415 pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3416} 3417